1config ARM64 2 def_bool y 3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_SG_CHAIN 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_USE_CMPXCHG_LOCKREF 8 select ARCH_SUPPORTS_ATOMIC_RMW 9 select ARCH_WANT_OPTIONAL_GPIOLIB 10 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 11 select ARCH_WANT_FRAME_POINTERS 12 select ARM_AMBA 13 select ARM_ARCH_TIMER 14 select ARM_GIC 15 select AUDIT_ARCH_COMPAT_GENERIC 16 select ARM_GIC_V3 17 select BUILDTIME_EXTABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select CPU_PM if (SUSPEND || CPU_IDLE) 21 select DCACHE_WORD_ACCESS 22 select GENERIC_ALLOCATOR 23 select GENERIC_CLOCKEVENTS 24 select GENERIC_CLOCKEVENTS_BROADCAST 25 select GENERIC_CPU_AUTOPROBE 26 select GENERIC_EARLY_IOREMAP 27 select GENERIC_IOMAP 28 select GENERIC_IRQ_PROBE 29 select GENERIC_IRQ_SHOW 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select GENERIC_TIME_VSYSCALL 35 select HANDLE_DOMAIN_IRQ 36 select HARDIRQS_SW_RESEND 37 select HAVE_ARCH_AUDITSYSCALL 38 select HAVE_ARCH_HARDENED_USERCOPY 39 select HAVE_ARCH_JUMP_LABEL 40 select HAVE_ARCH_KGDB 41 select HAVE_ARCH_MMAP_RND_BITS 42 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 43 select HAVE_ARCH_SECCOMP_FILTER 44 select HAVE_ARCH_TRACEHOOK 45 select HAVE_BPF_JIT 46 select HAVE_C_RECORDMCOUNT 47 select HAVE_CC_STACKPROTECTOR 48 select HAVE_DEBUG_BUGVERBOSE 49 select HAVE_DEBUG_KMEMLEAK 50 select HAVE_DMA_API_DEBUG 51 select HAVE_DMA_ATTRS 52 select HAVE_DMA_CONTIGUOUS 53 select HAVE_DYNAMIC_FTRACE 54 select HAVE_EFFICIENT_UNALIGNED_ACCESS 55 select HAVE_FTRACE_MCOUNT_RECORD 56 select HAVE_FUNCTION_TRACER 57 select HAVE_FUNCTION_GRAPH_TRACER 58 select HAVE_GENERIC_DMA_COHERENT 59 select HAVE_HW_BREAKPOINT if PERF_EVENTS 60 select HAVE_MEMBLOCK 61 select HAVE_PATA_PLATFORM 62 select HAVE_PERF_EVENTS 63 select HAVE_PERF_REGS 64 select HAVE_PERF_USER_STACK_DUMP 65 select HAVE_RCU_TABLE_FREE 66 select HAVE_SYSCALL_TRACEPOINTS 67 select IRQ_DOMAIN 68 select MODULES_USE_ELF_RELA 69 select NO_BOOTMEM 70 select OF 71 select OF_EARLY_FLATTREE 72 select OF_RESERVED_MEM 73 select PERF_USE_VMALLOC 74 select POWER_RESET 75 select POWER_SUPPLY 76 select RTC_LIB 77 select SPARSE_IRQ 78 select SYSCTL_EXCEPTION_TRACE 79 select HAVE_CONTEXT_TRACKING 80 help 81 ARM 64-bit (AArch64) Linux support. 82 83config 64BIT 84 def_bool y 85 86config ARCH_PHYS_ADDR_T_64BIT 87 def_bool y 88 89config MMU 90 def_bool y 91 92config ARCH_MMAP_RND_BITS_MIN 93 default 14 if ARM64_64K_PAGES 94 default 16 if ARM64_16K_PAGES 95 default 18 96 97# max bits determined by the following formula: 98# VA_BITS - PAGE_SHIFT - 3 99config ARCH_MMAP_RND_BITS_MAX 100 default 19 if ARM64_VA_BITS=36 101 default 24 if ARM64_VA_BITS=39 102 default 27 if ARM64_VA_BITS=42 103 default 30 if ARM64_VA_BITS=47 104 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 105 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 106 default 33 if ARM64_VA_BITS=48 107 default 14 if ARM64_64K_PAGES 108 default 16 if ARM64_16K_PAGES 109 default 18 110 111config ARCH_MMAP_RND_COMPAT_BITS_MIN 112 default 7 if ARM64_64K_PAGES 113 default 9 if ARM64_16K_PAGES 114 default 11 115 116config ARCH_MMAP_RND_COMPAT_BITS_MAX 117 default 16 118 119config NO_IOPORT_MAP 120 def_bool y if !PCI 121 122config ILLEGAL_POINTER_VALUE 123 hex 124 default 0xdead000000000000 125 126config STACKTRACE_SUPPORT 127 def_bool y 128 129config ILLEGAL_POINTER_VALUE 130 hex 131 default 0xdead000000000000 132 133config LOCKDEP_SUPPORT 134 def_bool y 135 136config TRACE_IRQFLAGS_SUPPORT 137 def_bool y 138 139config RWSEM_XCHGADD_ALGORITHM 140 def_bool y 141 142config GENERIC_HWEIGHT 143 def_bool y 144 145config GENERIC_CSUM 146 def_bool y 147 148config GENERIC_CALIBRATE_DELAY 149 def_bool y 150 151config ZONE_DMA 152 def_bool y 153 154config HAVE_GENERIC_RCU_GUP 155 def_bool y 156 157config ARCH_DMA_ADDR_T_64BIT 158 def_bool y 159 160config NEED_DMA_MAP_STATE 161 def_bool y 162 163config NEED_SG_DMA_LENGTH 164 def_bool y 165 166config SMP 167 def_bool y 168 169config SWIOTLB 170 def_bool y 171 172config IOMMU_HELPER 173 def_bool SWIOTLB 174 175config KERNEL_MODE_NEON 176 def_bool y 177 178config FIX_EARLYCON_MEM 179 def_bool y 180 181config PGTABLE_LEVELS 182 int 183 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 184 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 185 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 186 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 187 188source "init/Kconfig" 189 190source "kernel/Kconfig.freezer" 191 192menu "Platform selection" 193 194config ARCH_THUNDER 195 bool "Cavium Inc. Thunder SoC Family" 196 help 197 This enables support for Cavium's Thunder Family of SoCs. 198 199config ARCH_VEXPRESS 200 bool "ARMv8 software model (Versatile Express)" 201 select ARCH_REQUIRE_GPIOLIB 202 select COMMON_CLK_VERSATILE 203 select POWER_RESET_VEXPRESS 204 select VEXPRESS_CONFIG 205 help 206 This enables support for the ARMv8 software model (Versatile 207 Express). 208 209config ARCH_XGENE 210 bool "AppliedMicro X-Gene SOC Family" 211 help 212 This enables support for AppliedMicro X-Gene SOC Family 213 214endmenu 215 216menu "Bus support" 217 218config ARM_AMBA 219 bool 220 221config PCI 222 bool "PCI support" 223 help 224 This feature enables support for PCI bus system. If you say Y 225 here, the kernel will include drivers and infrastructure code 226 to support PCI bus devices. 227 228config PCI_DOMAINS 229 def_bool PCI 230 231config PCI_DOMAINS_GENERIC 232 def_bool PCI 233 234config PCI_SYSCALL 235 def_bool PCI 236 237source "drivers/pci/Kconfig" 238source "drivers/pci/pcie/Kconfig" 239source "drivers/pci/hotplug/Kconfig" 240 241endmenu 242 243menu "Kernel Features" 244 245menu "ARM errata workarounds via the alternatives framework" 246 247config ARM64_ERRATUM_826319 248 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 249 default y 250 help 251 This option adds an alternative code sequence to work around ARM 252 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 253 AXI master interface and an L2 cache. 254 255 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 256 and is unable to accept a certain write via this interface, it will 257 not progress on read data presented on the read data channel and the 258 system can deadlock. 259 260 The workaround promotes data cache clean instructions to 261 data cache clean-and-invalidate. 262 Please note that this does not necessarily enable the workaround, 263 as it depends on the alternative framework, which will only patch 264 the kernel if an affected CPU is detected. 265 266 If unsure, say Y. 267 268config ARM64_ERRATUM_827319 269 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 270 default y 271 help 272 This option adds an alternative code sequence to work around ARM 273 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 274 master interface and an L2 cache. 275 276 Under certain conditions this erratum can cause a clean line eviction 277 to occur at the same time as another transaction to the same address 278 on the AMBA 5 CHI interface, which can cause data corruption if the 279 interconnect reorders the two transactions. 280 281 The workaround promotes data cache clean instructions to 282 data cache clean-and-invalidate. 283 Please note that this does not necessarily enable the workaround, 284 as it depends on the alternative framework, which will only patch 285 the kernel if an affected CPU is detected. 286 287 If unsure, say Y. 288 289config ARM64_ERRATUM_824069 290 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 291 default y 292 help 293 This option adds an alternative code sequence to work around ARM 294 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 295 to a coherent interconnect. 296 297 If a Cortex-A53 processor is executing a store or prefetch for 298 write instruction at the same time as a processor in another 299 cluster is executing a cache maintenance operation to the same 300 address, then this erratum might cause a clean cache line to be 301 incorrectly marked as dirty. 302 303 The workaround promotes data cache clean instructions to 304 data cache clean-and-invalidate. 305 Please note that this option does not necessarily enable the 306 workaround, as it depends on the alternative framework, which will 307 only patch the kernel if an affected CPU is detected. 308 309 If unsure, say Y. 310 311config ARM64_ERRATUM_819472 312 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 313 default y 314 help 315 This option adds an alternative code sequence to work around ARM 316 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 317 present when it is connected to a coherent interconnect. 318 319 If the processor is executing a load and store exclusive sequence at 320 the same time as a processor in another cluster is executing a cache 321 maintenance operation to the same address, then this erratum might 322 cause data corruption. 323 324 The workaround promotes data cache clean instructions to 325 data cache clean-and-invalidate. 326 Please note that this does not necessarily enable the workaround, 327 as it depends on the alternative framework, which will only patch 328 the kernel if an affected CPU is detected. 329 330 If unsure, say Y. 331 332config ARM64_ERRATUM_832075 333 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 334 default y 335 help 336 This option adds an alternative code sequence to work around ARM 337 erratum 832075 on Cortex-A57 parts up to r1p2. 338 339 Affected Cortex-A57 parts might deadlock when exclusive load/store 340 instructions to Write-Back memory are mixed with Device loads. 341 342 The workaround is to promote device loads to use Load-Acquire 343 semantics. 344 Please note that this does not necessarily enable the workaround, 345 as it depends on the alternative framework, which will only patch 346 the kernel if an affected CPU is detected. 347 348 If unsure, say Y. 349 350config ARM64_ERRATUM_845719 351 bool "Cortex-A53: 845719: a load might read incorrect data" 352 depends on COMPAT 353 default y 354 help 355 This option adds an alternative code sequence to work around ARM 356 erratum 845719 on Cortex-A53 parts up to r0p4. 357 358 When running a compat (AArch32) userspace on an affected Cortex-A53 359 part, a load at EL0 from a virtual address that matches the bottom 32 360 bits of the virtual address used by a recent load at (AArch64) EL1 361 might return incorrect data. 362 363 The workaround is to write the contextidr_el1 register on exception 364 return to a 32-bit task. 365 Please note that this does not necessarily enable the workaround, 366 as it depends on the alternative framework, which will only patch 367 the kernel if an affected CPU is detected. 368 369 If unsure, say Y. 370 371endmenu 372 373 374choice 375 prompt "Page size" 376 default ARM64_4K_PAGES 377 help 378 Page size (translation granule) configuration. 379 380config ARM64_4K_PAGES 381 bool "4KB" 382 help 383 This feature enables 4KB pages support. 384 385config ARM64_64K_PAGES 386 bool "64KB" 387 help 388 This feature enables 64KB pages support (4KB by default) 389 allowing only two levels of page tables and faster TLB 390 look-up. AArch32 emulation is not available when this feature 391 is enabled. 392 393endchoice 394 395choice 396 prompt "Virtual address space size" 397 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 398 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 399 help 400 Allows choosing one of multiple possible virtual address 401 space sizes. The level of translation table is determined by 402 a combination of page size and virtual address space size. 403 404config ARM64_VA_BITS_39 405 bool "39-bit" 406 depends on ARM64_4K_PAGES 407 408config ARM64_VA_BITS_42 409 bool "42-bit" 410 depends on ARM64_64K_PAGES 411 412config ARM64_VA_BITS_48 413 bool "48-bit" 414 depends on !ARM_SMMU 415 416endchoice 417 418config ARM64_VA_BITS 419 int 420 default 39 if ARM64_VA_BITS_39 421 default 42 if ARM64_VA_BITS_42 422 default 48 if ARM64_VA_BITS_48 423 424config CPU_BIG_ENDIAN 425 bool "Build big-endian kernel" 426 help 427 Say Y if you plan on running a kernel in big-endian mode. 428 429config SCHED_MC 430 bool "Multi-core scheduler support" 431 help 432 Multi-core scheduler support improves the CPU scheduler's decision 433 making when dealing with multi-core CPU chips at a cost of slightly 434 increased overhead in some places. If unsure say N here. 435 436config SCHED_SMT 437 bool "SMT scheduler support" 438 help 439 Improves the CPU scheduler's decision making when dealing with 440 MultiThreading at a cost of slightly increased overhead in some 441 places. If unsure say N here. 442 443config NR_CPUS 444 int "Maximum number of CPUs (2-64)" 445 # These have to remain sorted largest to smallest 446 default "64" 447 448config HOTPLUG_CPU 449 bool "Support for hot-pluggable CPUs" 450 help 451 Say Y here to experiment with turning CPUs off and on. CPUs 452 can be controlled through /sys/devices/system/cpu. 453 454source kernel/Kconfig.preempt 455 456config HZ 457 int 458 default 100 459 460config ARCH_HAS_HOLES_MEMORYMODEL 461 def_bool y if SPARSEMEM 462 463config ARCH_SPARSEMEM_ENABLE 464 def_bool y 465 select SPARSEMEM_VMEMMAP_ENABLE 466 467config ARCH_SPARSEMEM_DEFAULT 468 def_bool ARCH_SPARSEMEM_ENABLE 469 470config ARCH_SELECT_MEMORY_MODEL 471 def_bool ARCH_SPARSEMEM_ENABLE 472 473config HAVE_ARCH_PFN_VALID 474 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 475 476config HW_PERF_EVENTS 477 bool "Enable hardware performance counter support for perf events" 478 depends on PERF_EVENTS 479 default y 480 help 481 Enable hardware performance counter support for perf events. If 482 disabled, perf events will use software events only. 483 484config SYS_SUPPORTS_HUGETLBFS 485 def_bool y 486 487config ARCH_WANT_GENERAL_HUGETLB 488 def_bool y 489 490config ARCH_WANT_HUGE_PMD_SHARE 491 def_bool y if !ARM64_64K_PAGES 492 493config HAVE_ARCH_TRANSPARENT_HUGEPAGE 494 def_bool y 495 496config ARCH_HAS_CACHE_LINE_SIZE 497 def_bool y 498 499source "mm/Kconfig" 500 501config SECCOMP 502 bool "Enable seccomp to safely compute untrusted bytecode" 503 ---help--- 504 This kernel feature is useful for number crunching applications 505 that may need to compute untrusted bytecode during their 506 execution. By using pipes or other transports made available to 507 the process as file descriptors supporting the read/write 508 syscalls, it's possible to isolate those applications in 509 their own address space using seccomp. Once seccomp is 510 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 511 and the task is only allowed to execute a few safe syscalls 512 defined by each seccomp mode. 513 514config XEN_DOM0 515 def_bool y 516 depends on XEN 517 518config XEN 519 bool "Xen guest support on ARM64" 520 depends on ARM64 && OF 521 select SWIOTLB_XEN 522 help 523 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 524 525config FORCE_MAX_ZONEORDER 526 int 527 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 528 default "11" 529 530config UNMAP_KERNEL_AT_EL0 531 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 532 default y 533 help 534 Speculation attacks against some high-performance processors can 535 be used to bypass MMU permission checks and leak kernel data to 536 userspace. This can be defended against by unmapping the kernel 537 when running in userspace, mapping it back in on exception entry 538 via a trampoline page in the vector table. 539 540 If unsure, say Y. 541 542menuconfig ARMV8_DEPRECATED 543 bool "Emulate deprecated/obsolete ARMv8 instructions" 544 depends on COMPAT 545 help 546 Legacy software support may require certain instructions 547 that have been deprecated or obsoleted in the architecture. 548 549 Enable this config to enable selective emulation of these 550 features. 551 552 If unsure, say Y 553 554if ARMV8_DEPRECATED 555 556config SWP_EMULATION 557 bool "Emulate SWP/SWPB instructions" 558 help 559 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 560 they are always undefined. Say Y here to enable software 561 emulation of these instructions for userspace using LDXR/STXR. 562 563 In some older versions of glibc [<=2.8] SWP is used during futex 564 trylock() operations with the assumption that the code will not 565 be preempted. This invalid assumption may be more likely to fail 566 with SWP emulation enabled, leading to deadlock of the user 567 application. 568 569 NOTE: when accessing uncached shared regions, LDXR/STXR rely 570 on an external transaction monitoring block called a global 571 monitor to maintain update atomicity. If your system does not 572 implement a global monitor, this option can cause programs that 573 perform SWP operations to uncached memory to deadlock. 574 575 If unsure, say Y 576 577config CP15_BARRIER_EMULATION 578 bool "Emulate CP15 Barrier instructions" 579 help 580 The CP15 barrier instructions - CP15ISB, CP15DSB, and 581 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 582 strongly recommended to use the ISB, DSB, and DMB 583 instructions instead. 584 585 Say Y here to enable software emulation of these 586 instructions for AArch32 userspace code. When this option is 587 enabled, CP15 barrier usage is traced which can help 588 identify software that needs updating. 589 590 If unsure, say Y 591 592config SETEND_EMULATION 593 bool "Emulate SETEND instruction" 594 help 595 The SETEND instruction alters the data-endianness of the 596 AArch32 EL0, and is deprecated in ARMv8. 597 598 Say Y here to enable software emulation of the instruction 599 for AArch32 userspace code. 600 601 Note: All the cpus on the system must have mixed endian support at EL0 602 for this feature to be enabled. If a new CPU - which doesn't support mixed 603 endian - is hotplugged in after this feature has been enabled, there could 604 be unexpected results in the applications. 605 606 If unsure, say Y 607 608endif 609 610config ARM64_SW_TTBR0_PAN 611 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 612 help 613 Enabling this option prevents the kernel from accessing 614 user-space memory directly by pointing TTBR0_EL1 to a reserved 615 zeroed area and reserved ASID. The user access routines 616 restore the valid TTBR0_EL1 temporarily. 617 618menu "ARMv8.1 architectural features" 619 620config ARM64_PAN 621 bool "Enable support for Privileged Access Never (PAN)" 622 default y 623 help 624 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 625 prevents the kernel or hypervisor from accessing user-space (EL0) 626 memory directly. 627 628 Choosing this option will cause any unprotected (not using 629 copy_to_user et al) memory access to fail with a permission fault. 630 631 The feature is detected at runtime, and will remain as a 'nop' 632 instruction if the cpu does not implement the feature. 633 634endmenu 635 636config ARM64_UAO 637 bool "Enable support for User Access Override (UAO)" 638 default y 639 help 640 User Access Override (UAO; part of the ARMv8.2 Extensions) 641 causes the 'unprivileged' variant of the load/store instructions to 642 be overriden to be privileged. 643 644 This option changes get_user() and friends to use the 'unprivileged' 645 variant of the load/store instructions. This ensures that user-space 646 really did have access to the supplied memory. When addr_limit is 647 set to kernel memory the UAO bit will be set, allowing privileged 648 access to kernel memory. 649 650 Choosing this option will cause copy_to_user() et al to use user-space 651 memory permissions. 652 653 The feature is detected at runtime, the kernel will use the 654 regular load/store instructions if the cpu does not implement the 655 feature. 656 657endmenu 658 659menu "Boot options" 660 661config CMDLINE 662 string "Default kernel command string" 663 default "" 664 help 665 Provide a set of default command-line options at build time by 666 entering them here. As a minimum, you should specify the the 667 root device (e.g. root=/dev/nfs). 668 669choice 670 prompt "Kernel command line type" if CMDLINE != "" 671 default CMDLINE_FROM_BOOTLOADER 672 673config CMDLINE_FROM_BOOTLOADER 674 bool "Use bootloader kernel arguments if available" 675 help 676 Uses the command-line options passed by the boot loader. If 677 the boot loader doesn't provide any, the default kernel command 678 string provided in CMDLINE will be used. 679 680config CMDLINE_EXTEND 681 bool "Extend bootloader kernel arguments" 682 help 683 The command-line arguments provided by the boot loader will be 684 appended to the default kernel command string. 685 686config CMDLINE_FORCE 687 bool "Always use the default kernel command string" 688 help 689 Always use the default kernel command string, even if the boot 690 loader passes other arguments to the kernel. 691 This is useful if you cannot or don't want to change the 692 command-line options your boot loader passes to the kernel. 693endchoice 694 695config EFI_STUB 696 bool 697 698config EFI 699 bool "UEFI runtime support" 700 depends on OF && !CPU_BIG_ENDIAN 701 select LIBFDT 702 select UCS2_STRING 703 select EFI_PARAMS_FROM_FDT 704 select EFI_RUNTIME_WRAPPERS 705 select EFI_STUB 706 select EFI_ARMSTUB 707 default y 708 help 709 This option provides support for runtime services provided 710 by UEFI firmware (such as non-volatile variables, realtime 711 clock, and platform reset). A UEFI stub is also provided to 712 allow the kernel to be booted as an EFI application. This 713 is only useful on systems that have UEFI firmware. 714 715config BUILD_ARM64_APPENDED_DTB_IMAGE 716 bool "Build a concatenated Image.gz/dtb by default" 717 depends on OF 718 help 719 Enabling this option will cause a concatenated Image.gz and list of 720 DTBs to be built by default (instead of a standalone Image.gz.) 721 The image will built in arch/arm64/boot/Image.gz-dtb 722 723config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES 724 string "Default dtb names" 725 depends on BUILD_ARM64_APPENDED_DTB_IMAGE 726 help 727 Space separated list of names of dtbs to append when 728 building a concatenated Image.gz-dtb. 729 730config DMI 731 bool "Enable support for SMBIOS (DMI) tables" 732 depends on EFI 733 default y 734 help 735 This enables SMBIOS/DMI feature for systems. 736 737 This option is only useful on systems that have UEFI firmware. 738 However, even with this option, the resultant kernel should 739 continue to boot on existing non-UEFI platforms. 740 741endmenu 742 743menu "Userspace binary formats" 744 745source "fs/Kconfig.binfmt" 746 747config COMPAT 748 bool "Kernel support for 32-bit EL0" 749 depends on !ARM64_64K_PAGES 750 select COMPAT_BINFMT_ELF 751 select HAVE_UID16 752 select OLD_SIGSUSPEND3 753 select COMPAT_OLD_SIGACTION 754 help 755 This option enables support for a 32-bit EL0 running under a 64-bit 756 kernel at EL1. AArch32-specific components such as system calls, 757 the user helper functions, VFP support and the ptrace interface are 758 handled appropriately by the kernel. 759 760 If you want to execute 32-bit userspace applications, say Y. 761 762config SYSVIPC_COMPAT 763 def_bool y 764 depends on COMPAT && SYSVIPC 765 766endmenu 767 768menu "Power management options" 769 770source "kernel/power/Kconfig" 771 772config ARCH_SUSPEND_POSSIBLE 773 def_bool y 774 775config ARM64_CPU_SUSPEND 776 def_bool PM_SLEEP 777 778endmenu 779 780menu "CPU Power Management" 781 782source "drivers/cpuidle/Kconfig" 783 784source "drivers/cpufreq/Kconfig" 785 786config ARM64_ERRATUM_843419 787 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 788 depends on MODULES 789 default y 790 help 791 This option builds kernel modules using the large memory model in 792 order to avoid the use of the ADRP instruction, which can cause 793 a subsequent memory access to use an incorrect address on Cortex-A53 794 parts up to r0p4. 795 796 Note that the kernel itself must be linked with a version of ld 797 which fixes potentially affected ADRP instructions through the 798 use of veneers. 799 800 If unsure, say Y. 801 802endmenu 803 804source "net/Kconfig" 805 806source "drivers/Kconfig" 807 808source "drivers/firmware/Kconfig" 809 810source "fs/Kconfig" 811 812source "arch/arm64/kvm/Kconfig" 813 814source "arch/arm64/Kconfig.debug" 815 816source "security/Kconfig" 817 818source "crypto/Kconfig" 819if CRYPTO 820source "arch/arm64/crypto/Kconfig" 821endif 822 823source "lib/Kconfig" 824