1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/war.h>
20
21 /*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25 #ifndef __STR
26 #define __STR(x) #x
27 #endif
28 #ifndef STR
29 #define STR(x) __STR(x)
30 #endif
31
32 /*
33 * Configure language
34 */
35 #ifdef __ASSEMBLY__
36 #define _ULCAST_
37 #else
38 #define _ULCAST_ (unsigned long)
39 #endif
40
41 /*
42 * Coprocessor 0 register names
43 */
44 #define CP0_INDEX $0
45 #define CP0_RANDOM $1
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
48 #define CP0_CONF $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
51 #define CP0_WIRED $6
52 #define CP0_INFO $7
53 #define CP0_BADVADDR $8
54 #define CP0_COUNT $9
55 #define CP0_ENTRYHI $10
56 #define CP0_COMPARE $11
57 #define CP0_STATUS $12
58 #define CP0_CAUSE $13
59 #define CP0_EPC $14
60 #define CP0_PRID $15
61 #define CP0_CONFIG $16
62 #define CP0_LLADDR $17
63 #define CP0_WATCHLO $18
64 #define CP0_WATCHHI $19
65 #define CP0_XCONTEXT $20
66 #define CP0_FRAMEMASK $21
67 #define CP0_DIAGNOSTIC $22
68 #define CP0_DEBUG $23
69 #define CP0_DEPC $24
70 #define CP0_PERFORMANCE $25
71 #define CP0_ECC $26
72 #define CP0_CACHEERR $27
73 #define CP0_TAGLO $28
74 #define CP0_TAGHI $29
75 #define CP0_ERROREPC $30
76 #define CP0_DESAVE $31
77
78 /*
79 * R4640/R4650 cp0 register names. These registers are listed
80 * here only for completeness; without MMU these CPUs are not useable
81 * by Linux. A future ELKS port might take make Linux run on them
82 * though ...
83 */
84 #define CP0_IBASE $0
85 #define CP0_IBOUND $1
86 #define CP0_DBASE $2
87 #define CP0_DBOUND $3
88 #define CP0_CALG $17
89 #define CP0_IWATCH $18
90 #define CP0_DWATCH $19
91
92 /*
93 * Coprocessor 0 Set 1 register names
94 */
95 #define CP0_S1_DERRADDR0 $26
96 #define CP0_S1_DERRADDR1 $27
97 #define CP0_S1_INTCONTROL $20
98
99 /*
100 * Coprocessor 0 Set 2 register names
101 */
102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
103
104 /*
105 * Coprocessor 0 Set 3 register names
106 */
107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
108
109 /*
110 * TX39 Series
111 */
112 #define CP0_TX39_CACHE $7
113
114
115 /*
116 * Values for PageMask register
117 */
118 #ifdef CONFIG_CPU_VR41XX
119
120 /* Why doesn't stupidity hurt ... */
121
122 #define PM_1K 0x00000000
123 #define PM_4K 0x00001800
124 #define PM_16K 0x00007800
125 #define PM_64K 0x0001f800
126 #define PM_256K 0x0007f800
127
128 #else
129
130 #define PM_4K 0x00000000
131 #define PM_8K 0x00002000
132 #define PM_16K 0x00006000
133 #define PM_32K 0x0000e000
134 #define PM_64K 0x0001e000
135 #define PM_128K 0x0003e000
136 #define PM_256K 0x0007e000
137 #define PM_512K 0x000fe000
138 #define PM_1M 0x001fe000
139 #define PM_2M 0x003fe000
140 #define PM_4M 0x007fe000
141 #define PM_8M 0x00ffe000
142 #define PM_16M 0x01ffe000
143 #define PM_32M 0x03ffe000
144 #define PM_64M 0x07ffe000
145 #define PM_256M 0x1fffe000
146 #define PM_1G 0x7fffe000
147
148 #endif
149
150 /*
151 * Default page size for a given kernel configuration
152 */
153 #ifdef CONFIG_PAGE_SIZE_4KB
154 #define PM_DEFAULT_MASK PM_4K
155 #elif defined(CONFIG_PAGE_SIZE_8KB)
156 #define PM_DEFAULT_MASK PM_8K
157 #elif defined(CONFIG_PAGE_SIZE_16KB)
158 #define PM_DEFAULT_MASK PM_16K
159 #elif defined(CONFIG_PAGE_SIZE_32KB)
160 #define PM_DEFAULT_MASK PM_32K
161 #elif defined(CONFIG_PAGE_SIZE_64KB)
162 #define PM_DEFAULT_MASK PM_64K
163 #else
164 #error Bad page size configuration!
165 #endif
166
167 /*
168 * Default huge tlb size for a given kernel configuration
169 */
170 #ifdef CONFIG_PAGE_SIZE_4KB
171 #define PM_HUGE_MASK PM_1M
172 #elif defined(CONFIG_PAGE_SIZE_8KB)
173 #define PM_HUGE_MASK PM_4M
174 #elif defined(CONFIG_PAGE_SIZE_16KB)
175 #define PM_HUGE_MASK PM_16M
176 #elif defined(CONFIG_PAGE_SIZE_32KB)
177 #define PM_HUGE_MASK PM_64M
178 #elif defined(CONFIG_PAGE_SIZE_64KB)
179 #define PM_HUGE_MASK PM_256M
180 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
181 #error Bad page size configuration for hugetlbfs!
182 #endif
183
184 /*
185 * Values used for computation of new tlb entries
186 */
187 #define PL_4K 12
188 #define PL_16K 14
189 #define PL_64K 16
190 #define PL_256K 18
191 #define PL_1M 20
192 #define PL_4M 22
193 #define PL_16M 24
194 #define PL_64M 26
195 #define PL_256M 28
196
197 /*
198 * PageGrain bits
199 */
200 #define PG_RIE (_ULCAST_(1) << 31)
201 #define PG_XIE (_ULCAST_(1) << 30)
202 #define PG_ELPA (_ULCAST_(1) << 29)
203 #define PG_ESP (_ULCAST_(1) << 28)
204 #define PG_IEC (_ULCAST_(1) << 27)
205
206 /*
207 * R4x00 interrupt enable / cause bits
208 */
209 #define IE_SW0 (_ULCAST_(1) << 8)
210 #define IE_SW1 (_ULCAST_(1) << 9)
211 #define IE_IRQ0 (_ULCAST_(1) << 10)
212 #define IE_IRQ1 (_ULCAST_(1) << 11)
213 #define IE_IRQ2 (_ULCAST_(1) << 12)
214 #define IE_IRQ3 (_ULCAST_(1) << 13)
215 #define IE_IRQ4 (_ULCAST_(1) << 14)
216 #define IE_IRQ5 (_ULCAST_(1) << 15)
217
218 /*
219 * R4x00 interrupt cause bits
220 */
221 #define C_SW0 (_ULCAST_(1) << 8)
222 #define C_SW1 (_ULCAST_(1) << 9)
223 #define C_IRQ0 (_ULCAST_(1) << 10)
224 #define C_IRQ1 (_ULCAST_(1) << 11)
225 #define C_IRQ2 (_ULCAST_(1) << 12)
226 #define C_IRQ3 (_ULCAST_(1) << 13)
227 #define C_IRQ4 (_ULCAST_(1) << 14)
228 #define C_IRQ5 (_ULCAST_(1) << 15)
229
230 /*
231 * Bitfields in the R4xx0 cp0 status register
232 */
233 #define ST0_IE 0x00000001
234 #define ST0_EXL 0x00000002
235 #define ST0_ERL 0x00000004
236 #define ST0_KSU 0x00000018
237 # define KSU_USER 0x00000010
238 # define KSU_SUPERVISOR 0x00000008
239 # define KSU_KERNEL 0x00000000
240 #define ST0_UX 0x00000020
241 #define ST0_SX 0x00000040
242 #define ST0_KX 0x00000080
243 #define ST0_DE 0x00010000
244 #define ST0_CE 0x00020000
245
246 /*
247 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
248 * cacheops in userspace. This bit exists only on RM7000 and RM9000
249 * processors.
250 */
251 #define ST0_CO 0x08000000
252
253 /*
254 * Bitfields in the R[23]000 cp0 status register.
255 */
256 #define ST0_IEC 0x00000001
257 #define ST0_KUC 0x00000002
258 #define ST0_IEP 0x00000004
259 #define ST0_KUP 0x00000008
260 #define ST0_IEO 0x00000010
261 #define ST0_KUO 0x00000020
262 /* bits 6 & 7 are reserved on R[23]000 */
263 #define ST0_ISC 0x00010000
264 #define ST0_SWC 0x00020000
265 #define ST0_CM 0x00080000
266
267 /*
268 * Bits specific to the R4640/R4650
269 */
270 #define ST0_UM (_ULCAST_(1) << 4)
271 #define ST0_IL (_ULCAST_(1) << 23)
272 #define ST0_DL (_ULCAST_(1) << 24)
273
274 /*
275 * Enable the MIPS MDMX and DSP ASEs
276 */
277 #define ST0_MX 0x01000000
278
279 /*
280 * Status register bits available in all MIPS CPUs.
281 */
282 #define ST0_IM 0x0000ff00
283 #define STATUSB_IP0 8
284 #define STATUSF_IP0 (_ULCAST_(1) << 8)
285 #define STATUSB_IP1 9
286 #define STATUSF_IP1 (_ULCAST_(1) << 9)
287 #define STATUSB_IP2 10
288 #define STATUSF_IP2 (_ULCAST_(1) << 10)
289 #define STATUSB_IP3 11
290 #define STATUSF_IP3 (_ULCAST_(1) << 11)
291 #define STATUSB_IP4 12
292 #define STATUSF_IP4 (_ULCAST_(1) << 12)
293 #define STATUSB_IP5 13
294 #define STATUSF_IP5 (_ULCAST_(1) << 13)
295 #define STATUSB_IP6 14
296 #define STATUSF_IP6 (_ULCAST_(1) << 14)
297 #define STATUSB_IP7 15
298 #define STATUSF_IP7 (_ULCAST_(1) << 15)
299 #define STATUSB_IP8 0
300 #define STATUSF_IP8 (_ULCAST_(1) << 0)
301 #define STATUSB_IP9 1
302 #define STATUSF_IP9 (_ULCAST_(1) << 1)
303 #define STATUSB_IP10 2
304 #define STATUSF_IP10 (_ULCAST_(1) << 2)
305 #define STATUSB_IP11 3
306 #define STATUSF_IP11 (_ULCAST_(1) << 3)
307 #define STATUSB_IP12 4
308 #define STATUSF_IP12 (_ULCAST_(1) << 4)
309 #define STATUSB_IP13 5
310 #define STATUSF_IP13 (_ULCAST_(1) << 5)
311 #define STATUSB_IP14 6
312 #define STATUSF_IP14 (_ULCAST_(1) << 6)
313 #define STATUSB_IP15 7
314 #define STATUSF_IP15 (_ULCAST_(1) << 7)
315 #define ST0_CH 0x00040000
316 #define ST0_NMI 0x00080000
317 #define ST0_SR 0x00100000
318 #define ST0_TS 0x00200000
319 #define ST0_BEV 0x00400000
320 #define ST0_RE 0x02000000
321 #define ST0_FR 0x04000000
322 #define ST0_CU 0xf0000000
323 #define ST0_CU0 0x10000000
324 #define ST0_CU1 0x20000000
325 #define ST0_CU2 0x40000000
326 #define ST0_CU3 0x80000000
327 #define ST0_XX 0x80000000 /* MIPS IV naming */
328
329 /*
330 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
331 */
332 #define INTCTLB_IPFDC 23
333 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
334 #define INTCTLB_IPPCI 26
335 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
336 #define INTCTLB_IPTI 29
337 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
338
339 /*
340 * Bitfields and bit numbers in the coprocessor 0 cause register.
341 *
342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
343 */
344 #define CAUSEB_EXCCODE 2
345 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
346 #define CAUSEB_IP 8
347 #define CAUSEF_IP (_ULCAST_(255) << 8)
348 #define CAUSEB_IP0 8
349 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
350 #define CAUSEB_IP1 9
351 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
352 #define CAUSEB_IP2 10
353 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
354 #define CAUSEB_IP3 11
355 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
356 #define CAUSEB_IP4 12
357 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
358 #define CAUSEB_IP5 13
359 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
360 #define CAUSEB_IP6 14
361 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
362 #define CAUSEB_IP7 15
363 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
364 #define CAUSEB_FDCI 21
365 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
366 #define CAUSEB_IV 23
367 #define CAUSEF_IV (_ULCAST_(1) << 23)
368 #define CAUSEB_PCI 26
369 #define CAUSEF_PCI (_ULCAST_(1) << 26)
370 #define CAUSEB_CE 28
371 #define CAUSEF_CE (_ULCAST_(3) << 28)
372 #define CAUSEB_TI 30
373 #define CAUSEF_TI (_ULCAST_(1) << 30)
374 #define CAUSEB_BD 31
375 #define CAUSEF_BD (_ULCAST_(1) << 31)
376
377 /*
378 * Bits in the coprocessor 0 config register.
379 */
380 /* Generic bits. */
381 #define CONF_CM_CACHABLE_NO_WA 0
382 #define CONF_CM_CACHABLE_WA 1
383 #define CONF_CM_UNCACHED 2
384 #define CONF_CM_CACHABLE_NONCOHERENT 3
385 #define CONF_CM_CACHABLE_CE 4
386 #define CONF_CM_CACHABLE_COW 5
387 #define CONF_CM_CACHABLE_CUW 6
388 #define CONF_CM_CACHABLE_ACCELERATED 7
389 #define CONF_CM_CMASK 7
390 #define CONF_BE (_ULCAST_(1) << 15)
391
392 /* Bits common to various processors. */
393 #define CONF_CU (_ULCAST_(1) << 3)
394 #define CONF_DB (_ULCAST_(1) << 4)
395 #define CONF_IB (_ULCAST_(1) << 5)
396 #define CONF_DC (_ULCAST_(7) << 6)
397 #define CONF_IC (_ULCAST_(7) << 9)
398 #define CONF_EB (_ULCAST_(1) << 13)
399 #define CONF_EM (_ULCAST_(1) << 14)
400 #define CONF_SM (_ULCAST_(1) << 16)
401 #define CONF_SC (_ULCAST_(1) << 17)
402 #define CONF_EW (_ULCAST_(3) << 18)
403 #define CONF_EP (_ULCAST_(15)<< 24)
404 #define CONF_EC (_ULCAST_(7) << 28)
405 #define CONF_CM (_ULCAST_(1) << 31)
406
407 /* Bits specific to the R4xx0. */
408 #define R4K_CONF_SW (_ULCAST_(1) << 20)
409 #define R4K_CONF_SS (_ULCAST_(1) << 21)
410 #define R4K_CONF_SB (_ULCAST_(3) << 22)
411
412 /* Bits specific to the R5000. */
413 #define R5K_CONF_SE (_ULCAST_(1) << 12)
414 #define R5K_CONF_SS (_ULCAST_(3) << 20)
415
416 /* Bits specific to the RM7000. */
417 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
418 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
419 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
420 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
421 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
422 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
423
424 /* Bits specific to the R10000. */
425 #define R10K_CONF_DN (_ULCAST_(3) << 3)
426 #define R10K_CONF_CT (_ULCAST_(1) << 5)
427 #define R10K_CONF_PE (_ULCAST_(1) << 6)
428 #define R10K_CONF_PM (_ULCAST_(3) << 7)
429 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
430 #define R10K_CONF_SB (_ULCAST_(1) << 13)
431 #define R10K_CONF_SK (_ULCAST_(1) << 14)
432 #define R10K_CONF_SS (_ULCAST_(7) << 16)
433 #define R10K_CONF_SC (_ULCAST_(7) << 19)
434 #define R10K_CONF_DC (_ULCAST_(7) << 26)
435 #define R10K_CONF_IC (_ULCAST_(7) << 29)
436
437 /* Bits specific to the VR41xx. */
438 #define VR41_CONF_CS (_ULCAST_(1) << 12)
439 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
440 #define VR41_CONF_BP (_ULCAST_(1) << 16)
441 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
442 #define VR41_CONF_AD (_ULCAST_(1) << 23)
443
444 /* Bits specific to the R30xx. */
445 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
446 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
447 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
448 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
449 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
450 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
451 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
452 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
453 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
454
455 /* Bits specific to the TX49. */
456 #define TX49_CONF_DC (_ULCAST_(1) << 16)
457 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
458 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
459 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
460
461 /* Bits specific to the MIPS32/64 PRA. */
462 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
463 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
464 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
465 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
466 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
467 #define MIPS_CONF_M (_ULCAST_(1) << 31)
468
469 /*
470 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
471 */
472 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
473 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
474 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
475 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
476 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
477 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
478 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
479 #define MIPS_CONF1_DA_SHF 7
480 #define MIPS_CONF1_DA_SZ 3
481 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
482 #define MIPS_CONF1_DL_SHF 10
483 #define MIPS_CONF1_DL_SZ 3
484 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
485 #define MIPS_CONF1_DS_SHF 13
486 #define MIPS_CONF1_DS_SZ 3
487 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
488 #define MIPS_CONF1_IA_SHF 16
489 #define MIPS_CONF1_IA_SZ 3
490 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
491 #define MIPS_CONF1_IL_SHF 19
492 #define MIPS_CONF1_IL_SZ 3
493 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
494 #define MIPS_CONF1_IS_SHF 22
495 #define MIPS_CONF1_IS_SZ 3
496 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
497 #define MIPS_CONF1_TLBS_SHIFT (25)
498 #define MIPS_CONF1_TLBS_SIZE (6)
499 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
500
501 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
502 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
503 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
504 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
505 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
506 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
507 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
508 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
509
510 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
511 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
512 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
513 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
514 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
515 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
516 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
517 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
518 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
519 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
520 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
521 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
522 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
523 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
524 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
525 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
526 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
527 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
528 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
529 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
530 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
531 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
532 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
533 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
534 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
535 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
536 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
537
538 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
539 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
540 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
541 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
542 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
543 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
544 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
545 /* bits 10:8 in FTLB-only configurations */
546 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
547 /* bits 12:8 in VTLB-FTLB only configurations */
548 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
549 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
550 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
551 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
552 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
553 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
554 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
555 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
556 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
557 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
558 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
559
560 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
561 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
562 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
563 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
564 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
565 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
566 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
567 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
568 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
569 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
570 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
571
572 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
573 /* proAptiv FTLB on/off bit */
574 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
575 /* FTLB probability bits */
576 #define MIPS_CONF6_FTLBP_SHIFT (16)
577
578 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
579
580 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
581
582 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
583 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
584
585 /* MAAR bit definitions */
586 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
587 #define MIPS_MAAR_ADDR_SHIFT 12
588 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
589 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
590
591 /* EntryHI bit definition */
592 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
593
594 /* R3000 EntryLo bit definitions */
595 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
596 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
597 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
598 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
599
600 /* R4000 compatible EntryLo bit definitions */
601 #define MIPS_ENTRYLO_G (_ULCAST_(1) << 0)
602 #define MIPS_ENTRYLO_V (_ULCAST_(1) << 1)
603 #define MIPS_ENTRYLO_D (_ULCAST_(1) << 2)
604 #define MIPS_ENTRYLO_C_SHIFT 3
605 #define MIPS_ENTRYLO_C (_ULCAST_(7) << MIPS_ENTRYLO_C_SHIFT)
606 #ifdef CONFIG_64BIT
607 /* as read by dmfc0 */
608 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
609 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
610 #else
611 /* as read by mfc0 */
612 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
613 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
614 #endif
615
616 /* CMGCRBase bit definitions */
617 #define MIPS_CMGCRB_BASE 11
618 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
619
620 /*
621 * Bits in the MIPS32 Memory Segmentation registers.
622 */
623 #define MIPS_SEGCFG_PA_SHIFT 9
624 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
625 #define MIPS_SEGCFG_AM_SHIFT 4
626 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
627 #define MIPS_SEGCFG_EU_SHIFT 3
628 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
629 #define MIPS_SEGCFG_C_SHIFT 0
630 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
631
632 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
633 #define MIPS_SEGCFG_USK _ULCAST_(5)
634 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
635 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
636 #define MIPS_SEGCFG_MSK _ULCAST_(2)
637 #define MIPS_SEGCFG_MK _ULCAST_(1)
638 #define MIPS_SEGCFG_UK _ULCAST_(0)
639
640 #define MIPS_PWFIELD_GDI_SHIFT 24
641 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
642 #define MIPS_PWFIELD_UDI_SHIFT 18
643 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
644 #define MIPS_PWFIELD_MDI_SHIFT 12
645 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
646 #define MIPS_PWFIELD_PTI_SHIFT 6
647 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
648 #define MIPS_PWFIELD_PTEI_SHIFT 0
649 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
650
651 #define MIPS_PWSIZE_GDW_SHIFT 24
652 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
653 #define MIPS_PWSIZE_UDW_SHIFT 18
654 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
655 #define MIPS_PWSIZE_MDW_SHIFT 12
656 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
657 #define MIPS_PWSIZE_PTW_SHIFT 6
658 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
659 #define MIPS_PWSIZE_PTEW_SHIFT 0
660 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
661
662 #define MIPS_PWCTL_PWEN_SHIFT 31
663 #define MIPS_PWCTL_PWEN_MASK 0x80000000
664 #define MIPS_PWCTL_DPH_SHIFT 7
665 #define MIPS_PWCTL_DPH_MASK 0x00000080
666 #define MIPS_PWCTL_HUGEPG_SHIFT 6
667 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
668 #define MIPS_PWCTL_PSN_SHIFT 0
669 #define MIPS_PWCTL_PSN_MASK 0x0000003f
670
671 /* CDMMBase register bit definitions */
672 #define MIPS_CDMMBASE_SIZE_SHIFT 0
673 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
674 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
675 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
676 #define MIPS_CDMMBASE_ADDR_SHIFT 11
677 #define MIPS_CDMMBASE_ADDR_START 15
678
679 /*
680 * Bitfields in the TX39 family CP0 Configuration Register 3
681 */
682 #define TX39_CONF_ICS_SHIFT 19
683 #define TX39_CONF_ICS_MASK 0x00380000
684 #define TX39_CONF_ICS_1KB 0x00000000
685 #define TX39_CONF_ICS_2KB 0x00080000
686 #define TX39_CONF_ICS_4KB 0x00100000
687 #define TX39_CONF_ICS_8KB 0x00180000
688 #define TX39_CONF_ICS_16KB 0x00200000
689
690 #define TX39_CONF_DCS_SHIFT 16
691 #define TX39_CONF_DCS_MASK 0x00070000
692 #define TX39_CONF_DCS_1KB 0x00000000
693 #define TX39_CONF_DCS_2KB 0x00010000
694 #define TX39_CONF_DCS_4KB 0x00020000
695 #define TX39_CONF_DCS_8KB 0x00030000
696 #define TX39_CONF_DCS_16KB 0x00040000
697
698 #define TX39_CONF_CWFON 0x00004000
699 #define TX39_CONF_WBON 0x00002000
700 #define TX39_CONF_RF_SHIFT 10
701 #define TX39_CONF_RF_MASK 0x00000c00
702 #define TX39_CONF_DOZE 0x00000200
703 #define TX39_CONF_HALT 0x00000100
704 #define TX39_CONF_LOCK 0x00000080
705 #define TX39_CONF_ICE 0x00000020
706 #define TX39_CONF_DCE 0x00000010
707 #define TX39_CONF_IRSIZE_SHIFT 2
708 #define TX39_CONF_IRSIZE_MASK 0x0000000c
709 #define TX39_CONF_DRSIZE_SHIFT 0
710 #define TX39_CONF_DRSIZE_MASK 0x00000003
711
712 /*
713 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
714 */
715 /* Disable Branch Target Address Cache */
716 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
717 /* Enable Branch Prediction Global History */
718 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
719 /* Disable Branch Return Cache */
720 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
721
722 /*
723 * Coprocessor 1 (FPU) register names
724 */
725 #define CP1_REVISION $0
726 #define CP1_UFR $1
727 #define CP1_UNFR $4
728 #define CP1_FCCR $25
729 #define CP1_FEXR $26
730 #define CP1_FENR $28
731 #define CP1_STATUS $31
732
733
734 /*
735 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
736 */
737 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
738 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
739 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
740 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
741 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
742 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
743 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
744 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
745 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
746 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
747
748 /*
749 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
750 */
751 #define MIPS_FCCR_CONDX_S 0
752 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
753 #define MIPS_FCCR_COND0_S 0
754 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
755 #define MIPS_FCCR_COND1_S 1
756 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
757 #define MIPS_FCCR_COND2_S 2
758 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
759 #define MIPS_FCCR_COND3_S 3
760 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
761 #define MIPS_FCCR_COND4_S 4
762 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
763 #define MIPS_FCCR_COND5_S 5
764 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
765 #define MIPS_FCCR_COND6_S 6
766 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
767 #define MIPS_FCCR_COND7_S 7
768 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
769
770 /*
771 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
772 */
773 #define MIPS_FENR_FS_S 2
774 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
775
776 /*
777 * FPU Status Register Values
778 */
779 #define FPU_CSR_COND_S 23 /* $fcc0 */
780 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
781
782 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
783 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
784
785 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
786 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
787 #define FPU_CSR_COND1_S 25 /* $fcc1 */
788 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
789 #define FPU_CSR_COND2_S 26 /* $fcc2 */
790 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
791 #define FPU_CSR_COND3_S 27 /* $fcc3 */
792 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
793 #define FPU_CSR_COND4_S 28 /* $fcc4 */
794 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
795 #define FPU_CSR_COND5_S 29 /* $fcc5 */
796 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
797 #define FPU_CSR_COND6_S 30 /* $fcc6 */
798 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
799 #define FPU_CSR_COND7_S 31 /* $fcc7 */
800 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
801
802 /*
803 * Bits 22:20 of the FPU Status Register will be read as 0,
804 * and should be written as zero.
805 */
806 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
807
808 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
809 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
810
811 /*
812 * X the exception cause indicator
813 * E the exception enable
814 * S the sticky/flag bit
815 */
816 #define FPU_CSR_ALL_X 0x0003f000
817 #define FPU_CSR_UNI_X 0x00020000
818 #define FPU_CSR_INV_X 0x00010000
819 #define FPU_CSR_DIV_X 0x00008000
820 #define FPU_CSR_OVF_X 0x00004000
821 #define FPU_CSR_UDF_X 0x00002000
822 #define FPU_CSR_INE_X 0x00001000
823
824 #define FPU_CSR_ALL_E 0x00000f80
825 #define FPU_CSR_INV_E 0x00000800
826 #define FPU_CSR_DIV_E 0x00000400
827 #define FPU_CSR_OVF_E 0x00000200
828 #define FPU_CSR_UDF_E 0x00000100
829 #define FPU_CSR_INE_E 0x00000080
830
831 #define FPU_CSR_ALL_S 0x0000007c
832 #define FPU_CSR_INV_S 0x00000040
833 #define FPU_CSR_DIV_S 0x00000020
834 #define FPU_CSR_OVF_S 0x00000010
835 #define FPU_CSR_UDF_S 0x00000008
836 #define FPU_CSR_INE_S 0x00000004
837
838 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
839 #define FPU_CSR_RM 0x00000003
840 #define FPU_CSR_RN 0x0 /* nearest */
841 #define FPU_CSR_RZ 0x1 /* towards zero */
842 #define FPU_CSR_RU 0x2 /* towards +Infinity */
843 #define FPU_CSR_RD 0x3 /* towards -Infinity */
844
845
846 #ifndef __ASSEMBLY__
847
848 /*
849 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
850 */
851 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
852 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
853 #define get_isa16_mode(x) ((x) & 0x1)
854 #define msk_isa16_mode(x) ((x) & ~0x1)
855 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
856 #else
857 #define get_isa16_mode(x) 0
858 #define msk_isa16_mode(x) (x)
859 #define set_isa16_mode(x) do { } while(0)
860 #endif
861
862 /*
863 * microMIPS instructions can be 16-bit or 32-bit in length. This
864 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
865 */
mm_insn_16bit(u16 insn)866 static inline int mm_insn_16bit(u16 insn)
867 {
868 u16 opcode = (insn >> 10) & 0x7;
869
870 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
871 }
872
873 /*
874 * TLB Invalidate Flush
875 */
tlbinvf(void)876 static inline void tlbinvf(void)
877 {
878 __asm__ __volatile__(
879 ".set push\n\t"
880 ".set noreorder\n\t"
881 ".word 0x42000004\n\t" /* tlbinvf */
882 ".set pop");
883 }
884
885
886 /*
887 * Functions to access the R10000 performance counters. These are basically
888 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
889 * performance counter number encoded into bits 1 ... 5 of the instruction.
890 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
891 * disassembler these will look like an access to sel 0 or 1.
892 */
893 #define read_r10k_perf_cntr(counter) \
894 ({ \
895 unsigned int __res; \
896 __asm__ __volatile__( \
897 "mfpc\t%0, %1" \
898 : "=r" (__res) \
899 : "i" (counter)); \
900 \
901 __res; \
902 })
903
904 #define write_r10k_perf_cntr(counter,val) \
905 do { \
906 __asm__ __volatile__( \
907 "mtpc\t%0, %1" \
908 : \
909 : "r" (val), "i" (counter)); \
910 } while (0)
911
912 #define read_r10k_perf_event(counter) \
913 ({ \
914 unsigned int __res; \
915 __asm__ __volatile__( \
916 "mfps\t%0, %1" \
917 : "=r" (__res) \
918 : "i" (counter)); \
919 \
920 __res; \
921 })
922
923 #define write_r10k_perf_cntl(counter,val) \
924 do { \
925 __asm__ __volatile__( \
926 "mtps\t%0, %1" \
927 : \
928 : "r" (val), "i" (counter)); \
929 } while (0)
930
931
932 /*
933 * Macros to access the system control coprocessor
934 */
935
936 #define __read_32bit_c0_register(source, sel) \
937 ({ unsigned int __res; \
938 if (sel == 0) \
939 __asm__ __volatile__( \
940 "mfc0\t%0, " #source "\n\t" \
941 : "=r" (__res)); \
942 else \
943 __asm__ __volatile__( \
944 ".set\tmips32\n\t" \
945 "mfc0\t%0, " #source ", " #sel "\n\t" \
946 ".set\tmips0\n\t" \
947 : "=r" (__res)); \
948 __res; \
949 })
950
951 #define __read_64bit_c0_register(source, sel) \
952 ({ unsigned long long __res; \
953 if (sizeof(unsigned long) == 4) \
954 __res = __read_64bit_c0_split(source, sel); \
955 else if (sel == 0) \
956 __asm__ __volatile__( \
957 ".set\tmips3\n\t" \
958 "dmfc0\t%0, " #source "\n\t" \
959 ".set\tmips0" \
960 : "=r" (__res)); \
961 else \
962 __asm__ __volatile__( \
963 ".set\tmips64\n\t" \
964 "dmfc0\t%0, " #source ", " #sel "\n\t" \
965 ".set\tmips0" \
966 : "=r" (__res)); \
967 __res; \
968 })
969
970 #define __write_32bit_c0_register(register, sel, value) \
971 do { \
972 if (sel == 0) \
973 __asm__ __volatile__( \
974 "mtc0\t%z0, " #register "\n\t" \
975 : : "Jr" ((unsigned int)(value))); \
976 else \
977 __asm__ __volatile__( \
978 ".set\tmips32\n\t" \
979 "mtc0\t%z0, " #register ", " #sel "\n\t" \
980 ".set\tmips0" \
981 : : "Jr" ((unsigned int)(value))); \
982 } while (0)
983
984 #define __write_64bit_c0_register(register, sel, value) \
985 do { \
986 if (sizeof(unsigned long) == 4) \
987 __write_64bit_c0_split(register, sel, value); \
988 else if (sel == 0) \
989 __asm__ __volatile__( \
990 ".set\tmips3\n\t" \
991 "dmtc0\t%z0, " #register "\n\t" \
992 ".set\tmips0" \
993 : : "Jr" (value)); \
994 else \
995 __asm__ __volatile__( \
996 ".set\tmips64\n\t" \
997 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
998 ".set\tmips0" \
999 : : "Jr" (value)); \
1000 } while (0)
1001
1002 #define __read_ulong_c0_register(reg, sel) \
1003 ((sizeof(unsigned long) == 4) ? \
1004 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1005 (unsigned long) __read_64bit_c0_register(reg, sel))
1006
1007 #define __write_ulong_c0_register(reg, sel, val) \
1008 do { \
1009 if (sizeof(unsigned long) == 4) \
1010 __write_32bit_c0_register(reg, sel, val); \
1011 else \
1012 __write_64bit_c0_register(reg, sel, val); \
1013 } while (0)
1014
1015 /*
1016 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1017 */
1018 #define __read_32bit_c0_ctrl_register(source) \
1019 ({ unsigned int __res; \
1020 __asm__ __volatile__( \
1021 "cfc0\t%0, " #source "\n\t" \
1022 : "=r" (__res)); \
1023 __res; \
1024 })
1025
1026 #define __write_32bit_c0_ctrl_register(register, value) \
1027 do { \
1028 __asm__ __volatile__( \
1029 "ctc0\t%z0, " #register "\n\t" \
1030 : : "Jr" ((unsigned int)(value))); \
1031 } while (0)
1032
1033 /*
1034 * These versions are only needed for systems with more than 38 bits of
1035 * physical address space running the 32-bit kernel. That's none atm :-)
1036 */
1037 #define __read_64bit_c0_split(source, sel) \
1038 ({ \
1039 unsigned long long __val; \
1040 unsigned long __flags; \
1041 \
1042 local_irq_save(__flags); \
1043 if (sel == 0) \
1044 __asm__ __volatile__( \
1045 ".set\tmips64\n\t" \
1046 "dmfc0\t%M0, " #source "\n\t" \
1047 "dsll\t%L0, %M0, 32\n\t" \
1048 "dsra\t%M0, %M0, 32\n\t" \
1049 "dsra\t%L0, %L0, 32\n\t" \
1050 ".set\tmips0" \
1051 : "=r" (__val)); \
1052 else \
1053 __asm__ __volatile__( \
1054 ".set\tmips64\n\t" \
1055 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1056 "dsll\t%L0, %M0, 32\n\t" \
1057 "dsra\t%M0, %M0, 32\n\t" \
1058 "dsra\t%L0, %L0, 32\n\t" \
1059 ".set\tmips0" \
1060 : "=r" (__val)); \
1061 local_irq_restore(__flags); \
1062 \
1063 __val; \
1064 })
1065
1066 #define __write_64bit_c0_split(source, sel, val) \
1067 do { \
1068 unsigned long __flags; \
1069 \
1070 local_irq_save(__flags); \
1071 if (sel == 0) \
1072 __asm__ __volatile__( \
1073 ".set\tmips64\n\t" \
1074 "dsll\t%L0, %L0, 32\n\t" \
1075 "dsrl\t%L0, %L0, 32\n\t" \
1076 "dsll\t%M0, %M0, 32\n\t" \
1077 "or\t%L0, %L0, %M0\n\t" \
1078 "dmtc0\t%L0, " #source "\n\t" \
1079 ".set\tmips0" \
1080 : : "r" (val)); \
1081 else \
1082 __asm__ __volatile__( \
1083 ".set\tmips64\n\t" \
1084 "dsll\t%L0, %L0, 32\n\t" \
1085 "dsrl\t%L0, %L0, 32\n\t" \
1086 "dsll\t%M0, %M0, 32\n\t" \
1087 "or\t%L0, %L0, %M0\n\t" \
1088 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1089 ".set\tmips0" \
1090 : : "r" (val)); \
1091 local_irq_restore(__flags); \
1092 } while (0)
1093
1094 #define __readx_32bit_c0_register(source) \
1095 ({ \
1096 unsigned int __res; \
1097 \
1098 __asm__ __volatile__( \
1099 " .set push \n" \
1100 " .set noat \n" \
1101 " .set mips32r2 \n" \
1102 " .insn \n" \
1103 " # mfhc0 $1, %1 \n" \
1104 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1105 " move %0, $1 \n" \
1106 " .set pop \n" \
1107 : "=r" (__res) \
1108 : "i" (source)); \
1109 __res; \
1110 })
1111
1112 #define __writex_32bit_c0_register(register, value) \
1113 do { \
1114 __asm__ __volatile__( \
1115 " .set push \n" \
1116 " .set noat \n" \
1117 " .set mips32r2 \n" \
1118 " move $1, %0 \n" \
1119 " # mthc0 $1, %1 \n" \
1120 " .insn \n" \
1121 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1122 " .set pop \n" \
1123 : \
1124 : "r" (value), "i" (register)); \
1125 } while (0)
1126
1127 #define read_c0_index() __read_32bit_c0_register($0, 0)
1128 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1129
1130 #define read_c0_random() __read_32bit_c0_register($1, 0)
1131 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1132
1133 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1134 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1135
1136 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1137 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1138
1139 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1140 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1141
1142 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1143 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1144
1145 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1146 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1147
1148 #define read_c0_context() __read_ulong_c0_register($4, 0)
1149 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1150
1151 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1152 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1153
1154 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1155 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1156
1157 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1158 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1159
1160 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1161 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1162
1163 #define read_c0_info() __read_32bit_c0_register($7, 0)
1164
1165 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1166 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1167
1168 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1169 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1170
1171 #define read_c0_count() __read_32bit_c0_register($9, 0)
1172 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1173
1174 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1175 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1176
1177 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1178 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1179
1180 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1181 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1182
1183 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1184 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1185
1186 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1187 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1188
1189 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1190 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1191
1192 #define read_c0_status() __read_32bit_c0_register($12, 0)
1193
1194 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1195
1196 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1197 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1198
1199 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1200 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1201
1202 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1203
1204 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1205
1206 #define read_c0_config() __read_32bit_c0_register($16, 0)
1207 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1208 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1209 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1210 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1211 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1212 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1213 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1214 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1215 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1216 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1217 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1218 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1219 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1220 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1221 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1222
1223 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1224 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1225 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1226 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1227 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1228 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1229
1230 /*
1231 * The WatchLo register. There may be up to 8 of them.
1232 */
1233 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1234 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1235 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1236 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1237 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1238 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1239 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1240 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1241 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1242 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1243 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1244 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1245 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1246 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1247 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1248 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1249
1250 /*
1251 * The WatchHi register. There may be up to 8 of them.
1252 */
1253 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1254 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1255 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1256 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1257 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1258 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1259 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1260 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1261
1262 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1263 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1264 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1265 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1266 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1267 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1268 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1269 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1270
1271 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1272 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1273
1274 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1275 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1276
1277 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1278 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1279
1280 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1281 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1282
1283 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1284 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1285 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1286
1287 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1288 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1289
1290 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1291 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1292
1293 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1294 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1295
1296 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1297 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1298
1299 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1300 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1301
1302 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1303 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1304
1305 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1306 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1307
1308 /*
1309 * MIPS32 / MIPS64 performance counters
1310 */
1311 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1312 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1313 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1314 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1315 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1316 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1317 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1318 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1319 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1320 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1321 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1322 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1323 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1324 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1325 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1326 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1327 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1328 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1329 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1330 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1331 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1332 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1333 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1334 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1335
1336 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1337 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1338
1339 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1340 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1341
1342 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1343
1344 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1345 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1346
1347 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1348 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1349
1350 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1351 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1352
1353 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1354 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1355
1356 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1357 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1358
1359 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1360 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1361
1362 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1363 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1364
1365 /* MIPSR2 */
1366 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1367 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1368
1369 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1370 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1371
1372 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1373 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1374
1375 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1376 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1377
1378 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1379 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1380
1381 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1382 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1383
1384 /* MIPSR3 */
1385 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1386 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1387
1388 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1389 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1390
1391 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1392 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1393
1394 /* Hardware Page Table Walker */
1395 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1396 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1397
1398 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1399 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1400
1401 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1402 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1403
1404 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1405 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1406
1407 /* Cavium OCTEON (cnMIPS) */
1408 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1409 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1410
1411 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1412 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1413
1414 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1415 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1416 /*
1417 * The cacheerr registers are not standardized. On OCTEON, they are
1418 * 64 bits wide.
1419 */
1420 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1421 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1422
1423 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1424 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1425
1426 /* BMIPS3300 */
1427 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1428 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1429
1430 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1431 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1432
1433 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1434 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1435
1436 /* BMIPS43xx */
1437 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1438 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1439
1440 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1441 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1442
1443 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1444 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1445
1446 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1447 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1448
1449 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1450 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1451
1452 /* BMIPS5000 */
1453 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1454 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1455
1456 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1457 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1458
1459 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1460 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1461
1462 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1463 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1464
1465 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1466 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1467
1468 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1469 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1470
1471 /*
1472 * Macros to access the floating point coprocessor control registers
1473 */
1474 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1475 ({ \
1476 unsigned int __res; \
1477 \
1478 __asm__ __volatile__( \
1479 " .set push \n" \
1480 " .set reorder \n" \
1481 " # gas fails to assemble cfc1 for some archs, \n" \
1482 " # like Octeon. \n" \
1483 " .set mips1 \n" \
1484 " "STR(gas_hardfloat)" \n" \
1485 " cfc1 %0,"STR(source)" \n" \
1486 " .set pop \n" \
1487 : "=r" (__res)); \
1488 __res; \
1489 })
1490
1491 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1492 do { \
1493 __asm__ __volatile__( \
1494 " .set push \n" \
1495 " .set reorder \n" \
1496 " "STR(gas_hardfloat)" \n" \
1497 " ctc1 %0,"STR(dest)" \n" \
1498 " .set pop \n" \
1499 : : "r" (val)); \
1500 } while (0)
1501
1502 #ifdef GAS_HAS_SET_HARDFLOAT
1503 #define read_32bit_cp1_register(source) \
1504 _read_32bit_cp1_register(source, .set hardfloat)
1505 #define write_32bit_cp1_register(dest, val) \
1506 _write_32bit_cp1_register(dest, val, .set hardfloat)
1507 #else
1508 #define read_32bit_cp1_register(source) \
1509 _read_32bit_cp1_register(source, )
1510 #define write_32bit_cp1_register(dest, val) \
1511 _write_32bit_cp1_register(dest, val, )
1512 #endif
1513
1514 #ifdef HAVE_AS_DSP
1515 #define rddsp(mask) \
1516 ({ \
1517 unsigned int __dspctl; \
1518 \
1519 __asm__ __volatile__( \
1520 " .set push \n" \
1521 " .set dsp \n" \
1522 " rddsp %0, %x1 \n" \
1523 " .set pop \n" \
1524 : "=r" (__dspctl) \
1525 : "i" (mask)); \
1526 __dspctl; \
1527 })
1528
1529 #define wrdsp(val, mask) \
1530 do { \
1531 __asm__ __volatile__( \
1532 " .set push \n" \
1533 " .set dsp \n" \
1534 " wrdsp %0, %x1 \n" \
1535 " .set pop \n" \
1536 : \
1537 : "r" (val), "i" (mask)); \
1538 } while (0)
1539
1540 #define mflo0() \
1541 ({ \
1542 long mflo0; \
1543 __asm__( \
1544 " .set push \n" \
1545 " .set dsp \n" \
1546 " mflo %0, $ac0 \n" \
1547 " .set pop \n" \
1548 : "=r" (mflo0)); \
1549 mflo0; \
1550 })
1551
1552 #define mflo1() \
1553 ({ \
1554 long mflo1; \
1555 __asm__( \
1556 " .set push \n" \
1557 " .set dsp \n" \
1558 " mflo %0, $ac1 \n" \
1559 " .set pop \n" \
1560 : "=r" (mflo1)); \
1561 mflo1; \
1562 })
1563
1564 #define mflo2() \
1565 ({ \
1566 long mflo2; \
1567 __asm__( \
1568 " .set push \n" \
1569 " .set dsp \n" \
1570 " mflo %0, $ac2 \n" \
1571 " .set pop \n" \
1572 : "=r" (mflo2)); \
1573 mflo2; \
1574 })
1575
1576 #define mflo3() \
1577 ({ \
1578 long mflo3; \
1579 __asm__( \
1580 " .set push \n" \
1581 " .set dsp \n" \
1582 " mflo %0, $ac3 \n" \
1583 " .set pop \n" \
1584 : "=r" (mflo3)); \
1585 mflo3; \
1586 })
1587
1588 #define mfhi0() \
1589 ({ \
1590 long mfhi0; \
1591 __asm__( \
1592 " .set push \n" \
1593 " .set dsp \n" \
1594 " mfhi %0, $ac0 \n" \
1595 " .set pop \n" \
1596 : "=r" (mfhi0)); \
1597 mfhi0; \
1598 })
1599
1600 #define mfhi1() \
1601 ({ \
1602 long mfhi1; \
1603 __asm__( \
1604 " .set push \n" \
1605 " .set dsp \n" \
1606 " mfhi %0, $ac1 \n" \
1607 " .set pop \n" \
1608 : "=r" (mfhi1)); \
1609 mfhi1; \
1610 })
1611
1612 #define mfhi2() \
1613 ({ \
1614 long mfhi2; \
1615 __asm__( \
1616 " .set push \n" \
1617 " .set dsp \n" \
1618 " mfhi %0, $ac2 \n" \
1619 " .set pop \n" \
1620 : "=r" (mfhi2)); \
1621 mfhi2; \
1622 })
1623
1624 #define mfhi3() \
1625 ({ \
1626 long mfhi3; \
1627 __asm__( \
1628 " .set push \n" \
1629 " .set dsp \n" \
1630 " mfhi %0, $ac3 \n" \
1631 " .set pop \n" \
1632 : "=r" (mfhi3)); \
1633 mfhi3; \
1634 })
1635
1636
1637 #define mtlo0(x) \
1638 ({ \
1639 __asm__( \
1640 " .set push \n" \
1641 " .set dsp \n" \
1642 " mtlo %0, $ac0 \n" \
1643 " .set pop \n" \
1644 : \
1645 : "r" (x)); \
1646 })
1647
1648 #define mtlo1(x) \
1649 ({ \
1650 __asm__( \
1651 " .set push \n" \
1652 " .set dsp \n" \
1653 " mtlo %0, $ac1 \n" \
1654 " .set pop \n" \
1655 : \
1656 : "r" (x)); \
1657 })
1658
1659 #define mtlo2(x) \
1660 ({ \
1661 __asm__( \
1662 " .set push \n" \
1663 " .set dsp \n" \
1664 " mtlo %0, $ac2 \n" \
1665 " .set pop \n" \
1666 : \
1667 : "r" (x)); \
1668 })
1669
1670 #define mtlo3(x) \
1671 ({ \
1672 __asm__( \
1673 " .set push \n" \
1674 " .set dsp \n" \
1675 " mtlo %0, $ac3 \n" \
1676 " .set pop \n" \
1677 : \
1678 : "r" (x)); \
1679 })
1680
1681 #define mthi0(x) \
1682 ({ \
1683 __asm__( \
1684 " .set push \n" \
1685 " .set dsp \n" \
1686 " mthi %0, $ac0 \n" \
1687 " .set pop \n" \
1688 : \
1689 : "r" (x)); \
1690 })
1691
1692 #define mthi1(x) \
1693 ({ \
1694 __asm__( \
1695 " .set push \n" \
1696 " .set dsp \n" \
1697 " mthi %0, $ac1 \n" \
1698 " .set pop \n" \
1699 : \
1700 : "r" (x)); \
1701 })
1702
1703 #define mthi2(x) \
1704 ({ \
1705 __asm__( \
1706 " .set push \n" \
1707 " .set dsp \n" \
1708 " mthi %0, $ac2 \n" \
1709 " .set pop \n" \
1710 : \
1711 : "r" (x)); \
1712 })
1713
1714 #define mthi3(x) \
1715 ({ \
1716 __asm__( \
1717 " .set push \n" \
1718 " .set dsp \n" \
1719 " mthi %0, $ac3 \n" \
1720 " .set pop \n" \
1721 : \
1722 : "r" (x)); \
1723 })
1724
1725 #else
1726
1727 #ifdef CONFIG_CPU_MICROMIPS
1728 #define rddsp(mask) \
1729 ({ \
1730 unsigned int __res; \
1731 \
1732 __asm__ __volatile__( \
1733 " .set push \n" \
1734 " .set noat \n" \
1735 " # rddsp $1, %x1 \n" \
1736 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1737 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1738 " move %0, $1 \n" \
1739 " .set pop \n" \
1740 : "=r" (__res) \
1741 : "i" (mask)); \
1742 __res; \
1743 })
1744
1745 #define wrdsp(val, mask) \
1746 do { \
1747 __asm__ __volatile__( \
1748 " .set push \n" \
1749 " .set noat \n" \
1750 " move $1, %0 \n" \
1751 " # wrdsp $1, %x1 \n" \
1752 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1753 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1754 " .set pop \n" \
1755 : \
1756 : "r" (val), "i" (mask)); \
1757 } while (0)
1758
1759 #define _umips_dsp_mfxxx(ins) \
1760 ({ \
1761 unsigned long __treg; \
1762 \
1763 __asm__ __volatile__( \
1764 " .set push \n" \
1765 " .set noat \n" \
1766 " .hword 0x0001 \n" \
1767 " .hword %x1 \n" \
1768 " move %0, $1 \n" \
1769 " .set pop \n" \
1770 : "=r" (__treg) \
1771 : "i" (ins)); \
1772 __treg; \
1773 })
1774
1775 #define _umips_dsp_mtxxx(val, ins) \
1776 do { \
1777 __asm__ __volatile__( \
1778 " .set push \n" \
1779 " .set noat \n" \
1780 " move $1, %0 \n" \
1781 " .hword 0x0001 \n" \
1782 " .hword %x1 \n" \
1783 " .set pop \n" \
1784 : \
1785 : "r" (val), "i" (ins)); \
1786 } while (0)
1787
1788 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1789 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1790
1791 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1792 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1793
1794 #define mflo0() _umips_dsp_mflo(0)
1795 #define mflo1() _umips_dsp_mflo(1)
1796 #define mflo2() _umips_dsp_mflo(2)
1797 #define mflo3() _umips_dsp_mflo(3)
1798
1799 #define mfhi0() _umips_dsp_mfhi(0)
1800 #define mfhi1() _umips_dsp_mfhi(1)
1801 #define mfhi2() _umips_dsp_mfhi(2)
1802 #define mfhi3() _umips_dsp_mfhi(3)
1803
1804 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1805 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1806 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1807 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1808
1809 #define mthi0(x) _umips_dsp_mthi(x, 0)
1810 #define mthi1(x) _umips_dsp_mthi(x, 1)
1811 #define mthi2(x) _umips_dsp_mthi(x, 2)
1812 #define mthi3(x) _umips_dsp_mthi(x, 3)
1813
1814 #else /* !CONFIG_CPU_MICROMIPS */
1815 #define rddsp(mask) \
1816 ({ \
1817 unsigned int __res; \
1818 \
1819 __asm__ __volatile__( \
1820 " .set push \n" \
1821 " .set noat \n" \
1822 " # rddsp $1, %x1 \n" \
1823 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1824 " move %0, $1 \n" \
1825 " .set pop \n" \
1826 : "=r" (__res) \
1827 : "i" (mask)); \
1828 __res; \
1829 })
1830
1831 #define wrdsp(val, mask) \
1832 do { \
1833 __asm__ __volatile__( \
1834 " .set push \n" \
1835 " .set noat \n" \
1836 " move $1, %0 \n" \
1837 " # wrdsp $1, %x1 \n" \
1838 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1839 " .set pop \n" \
1840 : \
1841 : "r" (val), "i" (mask)); \
1842 } while (0)
1843
1844 #define _dsp_mfxxx(ins) \
1845 ({ \
1846 unsigned long __treg; \
1847 \
1848 __asm__ __volatile__( \
1849 " .set push \n" \
1850 " .set noat \n" \
1851 " .word (0x00000810 | %1) \n" \
1852 " move %0, $1 \n" \
1853 " .set pop \n" \
1854 : "=r" (__treg) \
1855 : "i" (ins)); \
1856 __treg; \
1857 })
1858
1859 #define _dsp_mtxxx(val, ins) \
1860 do { \
1861 __asm__ __volatile__( \
1862 " .set push \n" \
1863 " .set noat \n" \
1864 " move $1, %0 \n" \
1865 " .word (0x00200011 | %1) \n" \
1866 " .set pop \n" \
1867 : \
1868 : "r" (val), "i" (ins)); \
1869 } while (0)
1870
1871 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1872 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1873
1874 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1875 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1876
1877 #define mflo0() _dsp_mflo(0)
1878 #define mflo1() _dsp_mflo(1)
1879 #define mflo2() _dsp_mflo(2)
1880 #define mflo3() _dsp_mflo(3)
1881
1882 #define mfhi0() _dsp_mfhi(0)
1883 #define mfhi1() _dsp_mfhi(1)
1884 #define mfhi2() _dsp_mfhi(2)
1885 #define mfhi3() _dsp_mfhi(3)
1886
1887 #define mtlo0(x) _dsp_mtlo(x, 0)
1888 #define mtlo1(x) _dsp_mtlo(x, 1)
1889 #define mtlo2(x) _dsp_mtlo(x, 2)
1890 #define mtlo3(x) _dsp_mtlo(x, 3)
1891
1892 #define mthi0(x) _dsp_mthi(x, 0)
1893 #define mthi1(x) _dsp_mthi(x, 1)
1894 #define mthi2(x) _dsp_mthi(x, 2)
1895 #define mthi3(x) _dsp_mthi(x, 3)
1896
1897 #endif /* CONFIG_CPU_MICROMIPS */
1898 #endif
1899
1900 /*
1901 * TLB operations.
1902 *
1903 * It is responsibility of the caller to take care of any TLB hazards.
1904 */
tlb_probe(void)1905 static inline void tlb_probe(void)
1906 {
1907 __asm__ __volatile__(
1908 ".set noreorder\n\t"
1909 "tlbp\n\t"
1910 ".set reorder");
1911 }
1912
tlb_read(void)1913 static inline void tlb_read(void)
1914 {
1915 #if MIPS34K_MISSED_ITLB_WAR
1916 int res = 0;
1917
1918 __asm__ __volatile__(
1919 " .set push \n"
1920 " .set noreorder \n"
1921 " .set noat \n"
1922 " .set mips32r2 \n"
1923 " .word 0x41610001 # dvpe $1 \n"
1924 " move %0, $1 \n"
1925 " ehb \n"
1926 " .set pop \n"
1927 : "=r" (res));
1928
1929 instruction_hazard();
1930 #endif
1931
1932 __asm__ __volatile__(
1933 ".set noreorder\n\t"
1934 "tlbr\n\t"
1935 ".set reorder");
1936
1937 #if MIPS34K_MISSED_ITLB_WAR
1938 if ((res & _ULCAST_(1)))
1939 __asm__ __volatile__(
1940 " .set push \n"
1941 " .set noreorder \n"
1942 " .set noat \n"
1943 " .set mips32r2 \n"
1944 " .word 0x41600021 # evpe \n"
1945 " ehb \n"
1946 " .set pop \n");
1947 #endif
1948 }
1949
tlb_write_indexed(void)1950 static inline void tlb_write_indexed(void)
1951 {
1952 __asm__ __volatile__(
1953 ".set noreorder\n\t"
1954 "tlbwi\n\t"
1955 ".set reorder");
1956 }
1957
tlb_write_random(void)1958 static inline void tlb_write_random(void)
1959 {
1960 __asm__ __volatile__(
1961 ".set noreorder\n\t"
1962 "tlbwr\n\t"
1963 ".set reorder");
1964 }
1965
1966 /*
1967 * Manipulate bits in a c0 register.
1968 */
1969 #define __BUILD_SET_C0(name) \
1970 static inline unsigned int \
1971 set_c0_##name(unsigned int set) \
1972 { \
1973 unsigned int res, new; \
1974 \
1975 res = read_c0_##name(); \
1976 new = res | set; \
1977 write_c0_##name(new); \
1978 \
1979 return res; \
1980 } \
1981 \
1982 static inline unsigned int \
1983 clear_c0_##name(unsigned int clear) \
1984 { \
1985 unsigned int res, new; \
1986 \
1987 res = read_c0_##name(); \
1988 new = res & ~clear; \
1989 write_c0_##name(new); \
1990 \
1991 return res; \
1992 } \
1993 \
1994 static inline unsigned int \
1995 change_c0_##name(unsigned int change, unsigned int val) \
1996 { \
1997 unsigned int res, new; \
1998 \
1999 res = read_c0_##name(); \
2000 new = res & ~change; \
2001 new |= (val & change); \
2002 write_c0_##name(new); \
2003 \
2004 return res; \
2005 }
2006
2007 __BUILD_SET_C0(status)
__BUILD_SET_C0(cause)2008 __BUILD_SET_C0(cause)
2009 __BUILD_SET_C0(config)
2010 __BUILD_SET_C0(config5)
2011 __BUILD_SET_C0(intcontrol)
2012 __BUILD_SET_C0(intctl)
2013 __BUILD_SET_C0(srsmap)
2014 __BUILD_SET_C0(pagegrain)
2015 __BUILD_SET_C0(brcm_config_0)
2016 __BUILD_SET_C0(brcm_bus_pll)
2017 __BUILD_SET_C0(brcm_reset)
2018 __BUILD_SET_C0(brcm_cmt_intr)
2019 __BUILD_SET_C0(brcm_cmt_ctrl)
2020 __BUILD_SET_C0(brcm_config)
2021 __BUILD_SET_C0(brcm_mode)
2022
2023 /*
2024 * Return low 10 bits of ebase.
2025 * Note that under KVM (MIPSVZ) this returns vcpu id.
2026 */
2027 static inline unsigned int get_ebase_cpunum(void)
2028 {
2029 return read_c0_ebase() & 0x3ff;
2030 }
2031
2032 #endif /* !__ASSEMBLY__ */
2033
2034 #endif /* _ASM_MIPSREGS_H */
2035