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1  /*
2   * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
3   *
4   * May be copied or modified under the terms of the GNU General Public
5   * License.  See linux/COPYING for more information.
6   *
7   * Definitions for the SH5 PCI hardware.
8   */
9  #ifndef __PCI_SH5_H
10  #define __PCI_SH5_H
11  
12  /* Product ID */
13  #define PCISH5_PID		0x350d
14  
15  /* vendor ID */
16  #define PCISH5_VID		0x1054
17  
18  /* Configuration types */
19  #define ST_TYPE0                0x00    /* Configuration cycle type 0 */
20  #define ST_TYPE1                0x01    /* Configuration cycle type 1 */
21  
22  /* VCR data */
23  #define PCISH5_VCR_STATUS      0x00
24  #define PCISH5_VCR_VERSION     0x08
25  
26  /*
27  ** ICR register offsets and bits
28  */
29  #define PCISH5_ICR_CR          0x100   /* PCI control register values */
30  #define CR_PBAM                 (1<<12)
31  #define CR_PFCS                 (1<<11)
32  #define CR_FTO                  (1<<10)
33  #define CR_PFE                  (1<<9)
34  #define CR_TBS                  (1<<8)
35  #define CR_SPUE                 (1<<7)
36  #define CR_BMAM                 (1<<6)
37  #define CR_HOST                 (1<<5)
38  #define CR_CLKEN                (1<<4)
39  #define CR_SOCS                 (1<<3)
40  #define CR_IOCS                 (1<<2)
41  #define CR_RSTCTL               (1<<1)
42  #define CR_CFINT                (1<<0)
43  #define CR_LOCK_MASK            0xa5000000
44  
45  #define PCISH5_ICR_INT         0x114   /* Interrupt registert values     */
46  #define INT_MADIM               (1<<2)
47  
48  #define PCISH5_ICR_LSR0        0X104   /* Local space register values    */
49  #define PCISH5_ICR_LSR1        0X108   /* Local space register values    */
50  #define PCISH5_ICR_LAR0        0x10c   /* Local address register values  */
51  #define PCISH5_ICR_LAR1        0x110   /* Local address register values  */
52  #define PCISH5_ICR_INTM        0x118   /* Interrupt mask register values                         */
53  #define PCISH5_ICR_AIR         0x11c   /* Interrupt error address information register values    */
54  #define PCISH5_ICR_CIR         0x120   /* Interrupt error command information register values    */
55  #define PCISH5_ICR_AINT        0x130   /* Interrupt error arbiter interrupt register values      */
56  #define PCISH5_ICR_AINTM       0x134   /* Interrupt error arbiter interrupt mask register values */
57  #define PCISH5_ICR_BMIR        0x138   /* Interrupt error info register of bus master values     */
58  #define PCISH5_ICR_PAR         0x1c0   /* Pio address register values                            */
59  #define PCISH5_ICR_MBR         0x1c4   /* Memory space bank register values                      */
60  #define PCISH5_ICR_IOBR        0x1c8   /* I/O space bank register values                         */
61  #define PCISH5_ICR_PINT        0x1cc   /* power management interrupt register values             */
62  #define PCISH5_ICR_PINTM       0x1d0   /* power management interrupt mask register values        */
63  #define PCISH5_ICR_MBMR        0x1d8   /* memory space bank mask register values                 */
64  #define PCISH5_ICR_IOBMR       0x1dc   /* I/O space bank mask register values                    */
65  #define PCISH5_ICR_CSCR0       0x210   /* PCI cache snoop control register 0                     */
66  #define PCISH5_ICR_CSCR1       0x214   /* PCI cache snoop control register 1                     */
67  #define PCISH5_ICR_PDR         0x220   /* Pio data register values                               */
68  
69  /* These are configs space registers */
70  #define PCISH5_ICR_CSR_VID     0x000	/* Vendor id                           */
71  #define PCISH5_ICR_CSR_DID     0x002   /* Device id                           */
72  #define PCISH5_ICR_CSR_CMD     0x004   /* Command register                    */
73  #define PCISH5_ICR_CSR_STATUS  0x006   /* Stautus                             */
74  #define PCISH5_ICR_CSR_IBAR0   0x010   /* I/O base address register           */
75  #define PCISH5_ICR_CSR_MBAR0   0x014   /* First  Memory base address register */
76  #define PCISH5_ICR_CSR_MBAR1   0x018   /* Second Memory base address register */
77  
78  /* Base address of registers */
79  #define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000)
80  #define SH5PCI_IO_BASE  (PHYS_PCI_BLOCK + 0x00800000)
81  /* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG)    */
82  
83  extern unsigned long pcicr_virt;
84  /* Register selection macro */
85  #define PCISH5_ICR_REG(x)                ( pcicr_virt + (PCISH5_ICR_##x))
86  /* #define PCISH5_VCR_REG(x)                ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
87  
88  /* Write I/O functions */
89  #define SH5PCI_WRITE(reg,val)        __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
90  #define SH5PCI_WRITE_SHORT(reg,val)  __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
91  #define SH5PCI_WRITE_BYTE(reg,val)   __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
92  
93  /* Read I/O functions */
94  #define SH5PCI_READ(reg)             __raw_readl(PCISH5_ICR_REG(reg))
95  #define SH5PCI_READ_SHORT(reg)       __raw_readw(PCISH5_ICR_REG(reg))
96  #define SH5PCI_READ_BYTE(reg)        __raw_readb(PCISH5_ICR_REG(reg))
97  
98  /* Set PCI config bits */
99  #define SET_CONFIG_BITS(bus,devfn,where)  ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
100  
101  /* Set PCI command register */
102  #define CONFIG_CMD(bus, devfn, where)            SET_CONFIG_BITS(bus->number,devfn,where)
103  
104  /* Size converters */
105  #define PCISH5_MEM_SIZCONV(x)		  (((x / 0x40000) - 1) << 18)
106  #define PCISH5_IO_SIZCONV(x)		  (((x / 0x40000) - 1) << 18)
107  
108  extern struct pci_ops sh5_pci_ops;
109  
110  #endif /* __PCI_SH5_H */
111