1 #ifndef _ASM_X86_MCE_H
2 #define _ASM_X86_MCE_H
3
4 #include <uapi/asm/mce.h>
5
6 /*
7 * Machine Check support for x86
8 */
9
10 /* MCG_CAP register defines */
11 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
14 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
15 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16 #define MCG_EXT_CNT_SHIFT 16
17 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
19 #define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
20
21 /* MCG_STATUS register defines */
22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
25
26 /* MCi_STATUS register defines */
27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
36
37 /* AMD-specific bits */
38 #define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
39 #define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
40
41 /*
42 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
43 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
44 * errors to indicate that errors are being filtered by hardware.
45 * We should mask out bit 12 when looking for specific signatures
46 * of uncorrected errors - so the F bit is deliberately skipped
47 * in this #define.
48 */
49 #define MCACOD 0xefff /* MCA Error Code */
50
51 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
52 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
53 #define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
54 #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
55 #define MCACOD_DATA 0x0134 /* Data Load */
56 #define MCACOD_INSTR 0x0150 /* Instruction Fetch */
57
58 /* MCi_MISC register defines */
59 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
60 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
61 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
62 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
63 #define MCI_MISC_ADDR_PHYS 2 /* physical address */
64 #define MCI_MISC_ADDR_MEM 3 /* memory address */
65 #define MCI_MISC_ADDR_GENERIC 7 /* generic */
66
67 /* CTL2 register defines */
68 #define MCI_CTL2_CMCI_EN (1ULL << 30)
69 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
70
71 #define MCJ_CTX_MASK 3
72 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
73 #define MCJ_CTX_RANDOM 0 /* inject context: random */
74 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
75 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
76 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
77 #define MCJ_EXCEPTION 0x8 /* raise as exception */
78 #define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
79
80 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
81
82 /* Software defined banks */
83 #define MCE_EXTENDED_BANK 128
84 #define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
85 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
86
87 #define MCE_LOG_LEN 32
88 #define MCE_LOG_SIGNATURE "MACHINECHECK"
89
90 /*
91 * This structure contains all data related to the MCE log. Also
92 * carries a signature to make it easier to find from external
93 * debugging tools. Each entry is only valid when its finished flag
94 * is set.
95 */
96 struct mce_log {
97 char signature[12]; /* "MACHINECHECK" */
98 unsigned len; /* = MCE_LOG_LEN */
99 unsigned next;
100 unsigned flags;
101 unsigned recordlen; /* length of struct mce */
102 struct mce entry[MCE_LOG_LEN];
103 };
104
105 struct mca_config {
106 bool dont_log_ce;
107 bool cmci_disabled;
108 bool ignore_ce;
109 bool disabled;
110 bool ser;
111 bool bios_cmci_threshold;
112 u8 banks;
113 s8 bootlog;
114 int tolerant;
115 int monarch_timeout;
116 int panic_timeout;
117 u32 rip_msr;
118 };
119
120 extern struct mca_config mca_cfg;
121 extern void mce_register_decode_chain(struct notifier_block *nb);
122 extern void mce_unregister_decode_chain(struct notifier_block *nb);
123
124 #include <linux/percpu.h>
125 #include <linux/atomic.h>
126
127 extern int mce_p5_enabled;
128
129 #ifdef CONFIG_X86_MCE
130 int mcheck_init(void);
131 void mcheck_cpu_init(struct cpuinfo_x86 *c);
132 #else
mcheck_init(void)133 static inline int mcheck_init(void) { return 0; }
mcheck_cpu_init(struct cpuinfo_x86 * c)134 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
135 #endif
136
137 #ifdef CONFIG_X86_ANCIENT_MCE
138 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
139 void winchip_mcheck_init(struct cpuinfo_x86 *c);
enable_p5_mce(void)140 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
141 #else
intel_p5_mcheck_init(struct cpuinfo_x86 * c)142 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
winchip_mcheck_init(struct cpuinfo_x86 * c)143 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
enable_p5_mce(void)144 static inline void enable_p5_mce(void) {}
145 #endif
146
147 void mce_setup(struct mce *m);
148 void mce_log(struct mce *m);
149 DECLARE_PER_CPU(struct device *, mce_device);
150
151 /*
152 * Maximum banks number.
153 * This is the limit of the current register layout on
154 * Intel CPUs.
155 */
156 #define MAX_NR_BANKS 32
157
158 #ifdef CONFIG_X86_MCE_INTEL
159 void mce_intel_feature_init(struct cpuinfo_x86 *c);
160 void cmci_clear(void);
161 void cmci_reenable(void);
162 void cmci_rediscover(void);
163 void cmci_recheck(void);
164 #else
mce_intel_feature_init(struct cpuinfo_x86 * c)165 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
cmci_clear(void)166 static inline void cmci_clear(void) {}
cmci_reenable(void)167 static inline void cmci_reenable(void) {}
cmci_rediscover(void)168 static inline void cmci_rediscover(void) {}
cmci_recheck(void)169 static inline void cmci_recheck(void) {}
170 #endif
171
172 #ifdef CONFIG_X86_MCE_AMD
173 void mce_amd_feature_init(struct cpuinfo_x86 *c);
174 #else
mce_amd_feature_init(struct cpuinfo_x86 * c)175 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
176 #endif
177
178 int mce_available(struct cpuinfo_x86 *c);
179
180 DECLARE_PER_CPU(unsigned, mce_exception_count);
181 DECLARE_PER_CPU(unsigned, mce_poll_count);
182
183 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
184 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
185
186 enum mcp_flags {
187 MCP_TIMESTAMP = (1 << 0), /* log time stamp */
188 MCP_UC = (1 << 1), /* log uncorrected errors */
189 MCP_DONTLOG = (1 << 2), /* only clear, don't log */
190 };
191 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
192
193 int mce_notify_irq(void);
194 void mce_notify_process(void);
195
196 DECLARE_PER_CPU(struct mce, injectm);
197
198 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
199 const char __user *ubuf,
200 size_t usize, loff_t *off));
201
202 /* Disable CMCI/polling for MCA bank claimed by firmware */
203 extern void mce_disable_bank(int bank);
204
205 /*
206 * Exception handler
207 */
208
209 /* Call the installed machine check handler for this CPU setup. */
210 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
211 void do_machine_check(struct pt_regs *, long);
212
213 /*
214 * Threshold handler
215 */
216
217 extern void (*mce_threshold_vector)(void);
218 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
219
220 /*
221 * Thermal handler
222 */
223
224 void intel_init_thermal(struct cpuinfo_x86 *c);
225
226 void mce_log_therm_throt_event(__u64 status);
227
228 /* Interrupt Handler for core thermal thresholds */
229 extern int (*platform_thermal_notify)(__u64 msr_val);
230
231 /* Interrupt Handler for package thermal thresholds */
232 extern int (*platform_thermal_package_notify)(__u64 msr_val);
233
234 /* Callback support of rate control, return true, if
235 * callback has rate control */
236 extern bool (*platform_thermal_package_rate_control)(void);
237
238 #ifdef CONFIG_X86_THERMAL_VECTOR
239 extern void mcheck_intel_therm_init(void);
240 #else
mcheck_intel_therm_init(void)241 static inline void mcheck_intel_therm_init(void) { }
242 #endif
243
244 /*
245 * Used by APEI to report memory error via /dev/mcelog
246 */
247
248 struct cper_sec_mem_err;
249 extern void apei_mce_report_mem_error(int corrected,
250 struct cper_sec_mem_err *mem_err);
251
252 #endif /* _ASM_X86_MCE_H */
253