1 /*************************************************************************************** 2 * 3 * Copyright (c) Beceem Communications Inc. 4 * 5 * Module Name: 6 * NVM.h 7 * 8 * Abstract: 9 * This file has the prototypes,preprocessors and definitions various NVM libraries. 10 * 11 * 12 * Revision History: 13 * Who When What 14 * -------- -------- ---------------------------------------------- 15 * Name Date Created/reviewed/modified 16 * 17 * Notes: 18 * 19 ****************************************************************************************/ 20 21 #ifndef _NVM_H_ 22 #define _NVM_H_ 23 24 struct bcm_flash_cs_info { 25 u32 MagicNumber; 26 /* let the magic number be 0xBECE-F1A5 - F1A5 for "flas-h" */ 27 u32 FlashLayoutVersion; 28 u32 ISOImageVersion; 29 u32 SCSIFirmwareVersion; 30 u32 OffsetFromZeroForPart1ISOImage; 31 u32 OffsetFromZeroForScsiFirmware; 32 u32 SizeOfScsiFirmware; 33 u32 OffsetFromZeroForPart2ISOImage; 34 u32 OffsetFromZeroForCalibrationStart; 35 u32 OffsetFromZeroForCalibrationEnd; 36 u32 OffsetFromZeroForVSAStart; 37 u32 OffsetFromZeroForVSAEnd; 38 u32 OffsetFromZeroForControlSectionStart; 39 u32 OffsetFromZeroForControlSectionData; 40 u32 CDLessInactivityTimeout; 41 u32 NewImageSignature; 42 u32 FlashSectorSizeSig; 43 u32 FlashSectorSize; 44 u32 FlashWriteSupportSize; 45 u32 TotalFlashSize; 46 u32 FlashBaseAddr; 47 u32 FlashPartMaxSize; 48 u32 IsCDLessDeviceBootSig; 49 /* MSC Timeout after reset to switch from MSC to NW Mode */ 50 u32 MassStorageTimeout; 51 }; 52 53 #define FLASH2X_TOTAL_SIZE (64 * 1024 * 1024) 54 #define DEFAULT_SECTOR_SIZE (64 * 1024) 55 56 struct bcm_flash2x_cs_info { 57 /* magic number as 0xBECE-F1A5 - F1A5 for "flas-h" */ 58 u32 MagicNumber; 59 u32 FlashLayoutVersion; 60 u32 ISOImageVersion; 61 u32 SCSIFirmwareVersion; 62 u32 OffsetFromZeroForPart1ISOImage; 63 u32 OffsetFromZeroForScsiFirmware; 64 u32 SizeOfScsiFirmware; 65 u32 OffsetFromZeroForPart2ISOImage; 66 u32 OffsetFromZeroForDSDStart; 67 u32 OffsetFromZeroForDSDEnd; 68 u32 OffsetFromZeroForVSAStart; 69 u32 OffsetFromZeroForVSAEnd; 70 u32 OffsetFromZeroForControlSectionStart; 71 u32 OffsetFromZeroForControlSectionData; 72 /* NO Data Activity timeout to switch from MSC to NW Mode */ 73 u32 CDLessInactivityTimeout; 74 u32 NewImageSignature; 75 u32 FlashSectorSizeSig; 76 u32 FlashSectorSize; 77 u32 FlashWriteSupportSize; 78 u32 TotalFlashSize; 79 u32 FlashBaseAddr; 80 u32 FlashPartMaxSize; 81 u32 IsCDLessDeviceBootSig; 82 /* MSC Timeout after reset to switch from MSC to NW Mode */ 83 u32 MassStorageTimeout; 84 /* Flash Map 2.0 Field */ 85 u32 OffsetISOImage1Part1Start; 86 u32 OffsetISOImage1Part1End; 87 u32 OffsetISOImage1Part2Start; 88 u32 OffsetISOImage1Part2End; 89 u32 OffsetISOImage1Part3Start; 90 u32 OffsetISOImage1Part3End; 91 u32 OffsetISOImage2Part1Start; 92 u32 OffsetISOImage2Part1End; 93 u32 OffsetISOImage2Part2Start; 94 u32 OffsetISOImage2Part2End; 95 u32 OffsetISOImage2Part3Start; 96 u32 OffsetISOImage2Part3End; 97 /* DSD Header offset from start of DSD */ 98 u32 OffsetFromDSDStartForDSDHeader; 99 u32 OffsetFromZeroForDSD1Start; 100 u32 OffsetFromZeroForDSD1End; 101 u32 OffsetFromZeroForDSD2Start; 102 u32 OffsetFromZeroForDSD2End; 103 u32 OffsetFromZeroForVSA1Start; 104 u32 OffsetFromZeroForVSA1End; 105 u32 OffsetFromZeroForVSA2Start; 106 u32 OffsetFromZeroForVSA2End; 107 /* 108 * ACCESS_BITS_PER_SECTOR 2 109 * ACCESS_RW 0 110 * ACCESS_RO 1 111 * ACCESS_RESVD 2 112 * ACCESS_RESVD 3 113 */ 114 u32 SectorAccessBitMap[FLASH2X_TOTAL_SIZE / (DEFAULT_SECTOR_SIZE * 16)]; 115 /* All expansions to the control data structure should add here */ 116 }; 117 118 struct bcm_vendor_section_info { 119 u32 OffsetFromZeroForSectionStart; 120 u32 OffsetFromZeroForSectionEnd; 121 u32 AccessFlags; 122 u32 Reserved[16]; 123 }; 124 125 struct bcm_flash2x_vendor_info { 126 struct bcm_vendor_section_info VendorSection[TOTAL_SECTIONS]; 127 u32 Reserved[16]; 128 }; 129 130 struct bcm_dsd_header { 131 u32 DSDImageSize; 132 u32 DSDImageCRC; 133 u32 DSDImagePriority; 134 /* We should not consider right now. Reading reserve is worthless. */ 135 u32 Reserved[252]; /* Resvd for DSD Header */ 136 u32 DSDImageMagicNumber; 137 }; 138 139 struct bcm_iso_header { 140 u32 ISOImageMagicNumber; 141 u32 ISOImageSize; 142 u32 ISOImageCRC; 143 u32 ISOImagePriority; 144 /* We should not consider right now. Reading reserve is worthless. */ 145 u32 Reserved[60]; /* Resvd for ISO Header extension */ 146 }; 147 148 #define EEPROM_BEGIN_CIS (0) 149 #define EEPROM_BEGIN_NON_CIS (0x200) 150 #define EEPROM_END (0x2000) 151 #define INIT_PARAMS_SIGNATURE (0x95a7a597) 152 #define MAX_INIT_PARAMS_LENGTH (2048) 153 #define MAC_ADDRESS_OFFSET 0x200 154 155 #define INIT_PARAMS_1_SIGNATURE_ADDRESS EEPROM_BEGIN_NON_CIS 156 #define INIT_PARAMS_1_DATA_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+16) 157 #define INIT_PARAMS_1_MACADDRESS_ADDRESS (MAC_ADDRESS_OFFSET) 158 #define INIT_PARAMS_1_LENGTH_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+4) 159 160 #define INIT_PARAMS_2_SIGNATURE_ADDRESS (EEPROM_BEGIN_NON_CIS + 2048 + 16) 161 #define INIT_PARAMS_2_DATA_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 16) 162 #define INIT_PARAMS_2_MACADDRESS_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 8) 163 #define INIT_PARAMS_2_LENGTH_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS + 4) 164 165 #define EEPROM_SPI_DEV_CONFIG_REG 0x0F003000 166 #define EEPROM_SPI_Q_STATUS1_REG 0x0F003004 167 #define EEPROM_SPI_Q_STATUS1_MASK_REG 0x0F00300C 168 169 #define EEPROM_SPI_Q_STATUS_REG 0x0F003008 170 #define EEPROM_CMDQ_SPI_REG 0x0F003018 171 #define EEPROM_WRITE_DATAQ_REG 0x0F00301C 172 #define EEPROM_READ_DATAQ_REG 0x0F003020 173 #define SPI_FLUSH_REG 0x0F00304C 174 175 #define EEPROM_WRITE_ENABLE 0x06000000 176 #define EEPROM_READ_STATUS_REGISTER 0x05000000 177 #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000 178 #define EEPROM_WRITE_QUEUE_EMPTY 0x00001000 179 #define EEPROM_WRITE_QUEUE_AVAIL 0x00002000 180 #define EEPROM_WRITE_QUEUE_FULL 0x00004000 181 #define EEPROM_16_BYTE_PAGE_READ 0xFB000000 182 #define EEPROM_4_BYTE_PAGE_READ 0x3B000000 183 184 #define EEPROM_CMD_QUEUE_FLUSH 0x00000001 185 #define EEPROM_WRITE_QUEUE_FLUSH 0x00000002 186 #define EEPROM_READ_QUEUE_FLUSH 0x00000004 187 #define EEPROM_ETH_QUEUE_FLUSH 0x00000008 188 #define EEPROM_ALL_QUEUE_FLUSH 0x0000000f 189 #define EEPROM_READ_ENABLE 0x06000000 190 #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000 191 #define EEPROM_READ_DATA_FULL 0x00000010 192 #define EEPROM_READ_DATA_AVAIL 0x00000020 193 #define EEPROM_READ_QUEUE_EMPTY 0x00000002 194 #define EEPROM_CMD_QUEUE_EMPTY 0x00000100 195 #define EEPROM_CMD_QUEUE_AVAIL 0x00000200 196 #define EEPROM_CMD_QUEUE_FULL 0x00000400 197 198 /* Most EEPROM status register bit 0 indicates if the EEPROM is busy 199 * with a write if set 1. See the details of the EEPROM Status Register 200 * in the EEPROM data sheet. 201 */ 202 #define EEPROM_STATUS_REG_WRITE_BUSY 0x00000001 203 204 /* We will have 1 mSec for every RETRIES_PER_DELAY count and have a max attempts of MAX_EEPROM_RETRIES 205 * This will give us 80 mSec minimum of delay = 80mSecs 206 */ 207 #define MAX_EEPROM_RETRIES 80 208 #define RETRIES_PER_DELAY 64 209 #define MAX_RW_SIZE 0x10 210 #define MAX_READ_SIZE 0x10 211 #define MAX_SECTOR_SIZE (512 * 1024) 212 #define MIN_SECTOR_SIZE (1024) 213 #define FLASH_SECTOR_SIZE_OFFSET 0xEFFFC 214 #define FLASH_SECTOR_SIZE_SIG_OFFSET 0xEFFF8 215 #define FLASH_SECTOR_SIZE_SIG 0xCAFEBABE 216 #define FLASH_CS_INFO_START_ADDR 0xFF0000 217 #define FLASH_CONTROL_STRUCT_SIGNATURE 0xBECEF1A5 218 #define SCSI_FIRMWARE_MAJOR_VERSION 0x1 219 #define SCSI_FIRMWARE_MINOR_VERSION 0x5 220 #define BYTE_WRITE_SUPPORT 0x1 221 #define FLASH_AUTO_INIT_BASE_ADDR 0xF00000 222 #define FLASH_CONTIGIOUS_START_ADDR_AFTER_INIT 0x1C000000 223 #define FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT 0x1F000000 224 #define FLASH_CONTIGIOUS_START_ADDR_BCS350 0x08000000 225 #define FLASH_CONTIGIOUS_END_ADDR_BCS350 0x08FFFFFF 226 #define FLASH_SIZE_ADDR 0xFFFFEC 227 #define FLASH_SPI_CMDQ_REG 0xAF003040 228 #define FLASH_SPI_WRITEQ_REG 0xAF003044 229 #define FLASH_SPI_READQ_REG 0xAF003048 230 #define FLASH_CONFIG_REG 0xAF003050 231 #define FLASH_GPIO_CONFIG_REG 0xAF000030 232 #define FLASH_CMD_WRITE_ENABLE 0x06 233 #define FLASH_CMD_READ_ENABLE 0x03 234 #define FLASH_CMD_RESET_WRITE_ENABLE 0x04 235 #define FLASH_CMD_STATUS_REG_READ 0x05 236 #define FLASH_CMD_STATUS_REG_WRITE 0x01 237 #define FLASH_CMD_READ_ID 0x9F 238 #define PAD_SELECT_REGISTER 0xAF000410 239 #define FLASH_PART_SST25VF080B 0xBF258E 240 #define EEPROM_CAL_DATA_INTERNAL_LOC 0xbFB00008 241 #define EEPROM_CALPARAM_START 0x200 242 #define EEPROM_SIZE_OFFSET 524 243 244 /* As Read/Write time vaires from 1.5 to 3.0 ms. 245 * so After Ignoring the rdm/wrm time(that is dependent on many factor like interface etc.), 246 * here time calculated meets the worst case delay, 3.0 ms 247 */ 248 #define MAX_FLASH_RETRIES 4 249 #define FLASH_PER_RETRIES_DELAY 16 250 #define EEPROM_MAX_CAL_AREA_SIZE 0xF0000 251 #define BECM ntohl(0x4245434d) 252 #define FLASH_2X_MAJOR_NUMBER 0x2 253 #define DSD_IMAGE_MAGIC_NUMBER 0xBECE0D5D 254 #define ISO_IMAGE_MAGIC_NUMBER 0xBECE0150 255 #define NON_CDLESS_DEVICE_BOOT_SIG 0xBECEB007 256 257 #define MINOR_VERSION(x) ((x >> 16) & 0xFFFF) 258 #define MAJOR_VERSION(x) (x & 0xFFFF) 259 260 #define CORRUPTED_PATTERN 0x0 261 #define UNINIT_PTR_IN_CS 0xBBBBDDDD 262 #define VENDOR_PTR_IN_CS 0xAAAACCCC 263 #define FLASH2X_SECTION_PRESENT (1 << 0) 264 #define FLASH2X_SECTION_VALID (1 << 1) 265 #define FLASH2X_SECTION_RO (1 << 2) 266 #define FLASH2X_SECTION_ACT (1 << 3) 267 #define SECTOR_IS_NOT_WRITABLE STATUS_FAILURE 268 #define INVALID_OFFSET STATUS_FAILURE 269 #define INVALID_SECTION STATUS_FAILURE 270 #define SECTOR_1K 1024 271 #define SECTOR_64K (64 * SECTOR_1K) 272 #define SECTOR_128K (2 * SECTOR_64K) 273 #define SECTOR_256k (2 * SECTOR_128K) 274 #define SECTOR_512K (2 * SECTOR_256k) 275 #define FLASH_PART_SIZE (16 * 1024 * 1024) 276 #define RESET_CHIP_SELECT -1 277 #define CHIP_SELECT_BIT12 12 278 #define SECTOR_READWRITE_PERMISSION 0 279 #define SECTOR_READONLY 1 280 #define SIGNATURE_SIZE 4 281 #define DEFAULT_BUFF_SIZE 0x10000 282 283 #define FIELD_OFFSET_IN_HEADER(HeaderPointer, Field) ((u8 *)&((HeaderPointer)(NULL))->Field - (u8 *)(NULL)) 284 285 #endif 286 287