1 /* 2 * rcar_du_regs.h -- R-Car Display Unit Registers Definitions 3 * 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * 6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 */ 12 13 #ifndef __RCAR_DU_REGS_H__ 14 #define __RCAR_DU_REGS_H__ 15 16 #define DU0_REG_OFFSET 0x00000 17 #define DU1_REG_OFFSET 0x30000 18 #define DU2_REG_OFFSET 0x40000 19 20 /* ----------------------------------------------------------------------------- 21 * Display Control Registers 22 */ 23 24 #define DSYSR 0x00000 /* display 1 */ 25 #define DSYSR_ILTS (1 << 29) 26 #define DSYSR_DSEC (1 << 20) 27 #define DSYSR_IUPD (1 << 16) 28 #define DSYSR_DRES (1 << 9) 29 #define DSYSR_DEN (1 << 8) 30 #define DSYSR_TVM_MASTER (0 << 6) 31 #define DSYSR_TVM_SWITCH (1 << 6) 32 #define DSYSR_TVM_TVSYNC (2 << 6) 33 #define DSYSR_TVM_MASK (3 << 6) 34 #define DSYSR_SCM_INT_NONE (0 << 4) 35 #define DSYSR_SCM_INT_SYNC (2 << 4) 36 #define DSYSR_SCM_INT_VIDEO (3 << 4) 37 38 #define DSMR 0x00004 39 #define DSMR_VSPM (1 << 28) 40 #define DSMR_ODPM (1 << 27) 41 #define DSMR_DIPM_DISP (0 << 25) 42 #define DSMR_DIPM_CSYNC (1 << 25) 43 #define DSMR_DIPM_DE (3 << 25) 44 #define DSMR_DIPM_MASK (3 << 25) 45 #define DSMR_CSPM (1 << 24) 46 #define DSMR_DIL (1 << 19) 47 #define DSMR_VSL (1 << 18) 48 #define DSMR_HSL (1 << 17) 49 #define DSMR_DDIS (1 << 16) 50 #define DSMR_CDEL (1 << 15) 51 #define DSMR_CDEM_CDE (0 << 13) 52 #define DSMR_CDEM_LOW (2 << 13) 53 #define DSMR_CDEM_HIGH (3 << 13) 54 #define DSMR_CDEM_MASK (3 << 13) 55 #define DSMR_CDED (1 << 12) 56 #define DSMR_ODEV (1 << 8) 57 #define DSMR_CSY_VH_OR (0 << 6) 58 #define DSMR_CSY_333 (2 << 6) 59 #define DSMR_CSY_222 (3 << 6) 60 #define DSMR_CSY_MASK (3 << 6) 61 62 #define DSSR 0x00008 63 #define DSSR_VC1FB_DSA0 (0 << 30) 64 #define DSSR_VC1FB_DSA1 (1 << 30) 65 #define DSSR_VC1FB_DSA2 (2 << 30) 66 #define DSSR_VC1FB_INIT (3 << 30) 67 #define DSSR_VC1FB_MASK (3 << 30) 68 #define DSSR_VC0FB_DSA0 (0 << 28) 69 #define DSSR_VC0FB_DSA1 (1 << 28) 70 #define DSSR_VC0FB_DSA2 (2 << 28) 71 #define DSSR_VC0FB_INIT (3 << 28) 72 #define DSSR_VC0FB_MASK (3 << 28) 73 #define DSSR_DFB(n) (1 << ((n)+15)) 74 #define DSSR_TVR (1 << 15) 75 #define DSSR_FRM (1 << 14) 76 #define DSSR_VBK (1 << 11) 77 #define DSSR_RINT (1 << 9) 78 #define DSSR_HBK (1 << 8) 79 #define DSSR_ADC(n) (1 << ((n)-1)) 80 81 #define DSRCR 0x0000c 82 #define DSRCR_TVCL (1 << 15) 83 #define DSRCR_FRCL (1 << 14) 84 #define DSRCR_VBCL (1 << 11) 85 #define DSRCR_RICL (1 << 9) 86 #define DSRCR_HBCL (1 << 8) 87 #define DSRCR_ADCL(n) (1 << ((n)-1)) 88 #define DSRCR_MASK 0x0000cbff 89 90 #define DIER 0x00010 91 #define DIER_TVE (1 << 15) 92 #define DIER_FRE (1 << 14) 93 #define DIER_VBE (1 << 11) 94 #define DIER_RIE (1 << 9) 95 #define DIER_HBE (1 << 8) 96 #define DIER_ADCE(n) (1 << ((n)-1)) 97 98 #define CPCR 0x00014 99 #define CPCR_CP4CE (1 << 19) 100 #define CPCR_CP3CE (1 << 18) 101 #define CPCR_CP2CE (1 << 17) 102 #define CPCR_CP1CE (1 << 16) 103 104 #define DPPR 0x00018 105 #define DPPR_DPE(n) (1 << ((n)*4-1)) 106 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) 107 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) 108 #define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ 109 #define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) 110 #define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) 111 #define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ 112 113 #define DEFR 0x00020 114 #define DEFR_CODE (0x7773 << 16) 115 #define DEFR_EXSL (1 << 12) 116 #define DEFR_EXVL (1 << 11) 117 #define DEFR_EXUP (1 << 5) 118 #define DEFR_VCUP (1 << 4) 119 #define DEFR_DEFE (1 << 0) 120 121 #define DAPCR 0x00024 122 #define DAPCR_CODE (0x7773 << 16) 123 #define DAPCR_AP2E (1 << 4) 124 #define DAPCR_AP1E (1 << 0) 125 126 #define DCPCR 0x00028 127 #define DCPCR_CODE (0x7773 << 16) 128 #define DCPCR_CA2B (1 << 13) 129 #define DCPCR_CD2F (1 << 12) 130 #define DCPCR_DC2E (1 << 8) 131 #define DCPCR_CAB (1 << 5) 132 #define DCPCR_CDF (1 << 4) 133 #define DCPCR_DCE (1 << 0) 134 135 #define DEFR2 0x00034 136 #define DEFR2_CODE (0x7775 << 16) 137 #define DEFR2_DEFE2G (1 << 0) 138 139 #define DEFR3 0x00038 140 #define DEFR3_CODE (0x7776 << 16) 141 #define DEFR3_EVDA (1 << 14) 142 #define DEFR3_EVDM_1 (1 << 12) 143 #define DEFR3_EVDM_2 (2 << 12) 144 #define DEFR3_EVDM_3 (3 << 12) 145 #define DEFR3_VMSM2_EMA (1 << 6) 146 #define DEFR3_VMSM1_ENA (1 << 4) 147 #define DEFR3_DEFE3 (1 << 0) 148 149 #define DEFR4 0x0003c 150 #define DEFR4_CODE (0x7777 << 16) 151 #define DEFR4_LRUO (1 << 5) 152 #define DEFR4_SPCE (1 << 4) 153 154 #define DVCSR 0x000d0 155 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) 156 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) 157 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) 158 #define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) 159 #define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) 160 #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) 161 #define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) 162 #define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) 163 #define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) 164 #define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) 165 166 #define DEFR5 0x000e0 167 #define DEFR5_CODE (0x66 << 24) 168 #define DEFR5_YCRGB2_DIS (0 << 14) 169 #define DEFR5_YCRGB2_PRI1 (1 << 14) 170 #define DEFR5_YCRGB2_PRI2 (2 << 14) 171 #define DEFR5_YCRGB2_PRI3 (3 << 14) 172 #define DEFR5_YCRGB2_MASK (3 << 14) 173 #define DEFR5_YCRGB1_DIS (0 << 12) 174 #define DEFR5_YCRGB1_PRI1 (1 << 12) 175 #define DEFR5_YCRGB1_PRI2 (2 << 12) 176 #define DEFR5_YCRGB1_PRI3 (3 << 12) 177 #define DEFR5_YCRGB1_MASK (3 << 12) 178 #define DEFR5_DEFE5 (1 << 0) 179 180 #define DDLTR 0x000e4 181 #define DDLTR_CODE (0x7766 << 16) 182 #define DDLTR_DLAR2 (1 << 6) 183 #define DDLTR_DLAY2 (1 << 5) 184 #define DDLTR_DLAY1 (1 << 1) 185 186 #define DEFR6 0x000e8 187 #define DEFR6_CODE (0x7778 << 16) 188 #define DEFR6_ODPM22_D2SMR (0 << 10) 189 #define DEFR6_ODPM22_DISP (2 << 10) 190 #define DEFR6_ODPM22_CDE (3 << 10) 191 #define DEFR6_ODPM22_MASK (3 << 10) 192 #define DEFR6_ODPM12_DSMR (0 << 8) 193 #define DEFR6_ODPM12_DISP (2 << 8) 194 #define DEFR6_ODPM12_CDE (3 << 8) 195 #define DEFR6_ODPM12_MASK (3 << 8) 196 #define DEFR6_TCNE2 (1 << 6) 197 #define DEFR6_MLOS1 (1 << 2) 198 #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE2) 199 200 /* ----------------------------------------------------------------------------- 201 * R8A7790-only Control Registers 202 */ 203 204 #define DD1SSR 0x20008 205 #define DD1SSR_TVR (1 << 15) 206 #define DD1SSR_FRM (1 << 14) 207 #define DD1SSR_BUF (1 << 12) 208 #define DD1SSR_VBK (1 << 11) 209 #define DD1SSR_RINT (1 << 9) 210 #define DD1SSR_HBK (1 << 8) 211 #define DD1SSR_ADC(n) (1 << ((n)-1)) 212 213 #define DD1SRCR 0x2000c 214 #define DD1SRCR_TVR (1 << 15) 215 #define DD1SRCR_FRM (1 << 14) 216 #define DD1SRCR_BUF (1 << 12) 217 #define DD1SRCR_VBK (1 << 11) 218 #define DD1SRCR_RINT (1 << 9) 219 #define DD1SRCR_HBK (1 << 8) 220 #define DD1SRCR_ADC(n) (1 << ((n)-1)) 221 222 #define DD1IER 0x20010 223 #define DD1IER_TVR (1 << 15) 224 #define DD1IER_FRM (1 << 14) 225 #define DD1IER_BUF (1 << 12) 226 #define DD1IER_VBK (1 << 11) 227 #define DD1IER_RINT (1 << 9) 228 #define DD1IER_HBK (1 << 8) 229 #define DD1IER_ADC(n) (1 << ((n)-1)) 230 231 #define DEFR8 0x20020 232 #define DEFR8_CODE (0x7790 << 16) 233 #define DEFR8_VSCS (1 << 6) 234 #define DEFR8_DRGBS_DU(n) ((n) << 4) 235 #define DEFR8_DRGBS_MASK (3 << 4) 236 #define DEFR8_DEFE8 (1 << 0) 237 238 #define DOFLR 0x20024 239 #define DOFLR_CODE (0x7790 << 16) 240 #define DOFLR_HSYCFL1 (1 << 13) 241 #define DOFLR_VSYCFL1 (1 << 12) 242 #define DOFLR_ODDFL1 (1 << 11) 243 #define DOFLR_DISPFL1 (1 << 10) 244 #define DOFLR_CDEFL1 (1 << 9) 245 #define DOFLR_RGBFL1 (1 << 8) 246 #define DOFLR_HSYCFL0 (1 << 5) 247 #define DOFLR_VSYCFL0 (1 << 4) 248 #define DOFLR_ODDFL0 (1 << 3) 249 #define DOFLR_DISPFL0 (1 << 2) 250 #define DOFLR_CDEFL0 (1 << 1) 251 #define DOFLR_RGBFL0 (1 << 0) 252 253 #define DIDSR 0x20028 254 #define DIDSR_CODE (0x7790 << 16) 255 #define DIDSR_LCDS_DCLKIN(n) (0 << (8 + (n) * 2)) 256 #define DIDSR_LCDS_LVDS0(n) (2 << (8 + (n) * 2)) 257 #define DIDSR_LCDS_LVDS1(n) (3 << (8 + (n) * 2)) 258 #define DIDSR_LCDS_MASK(n) (3 << (8 + (n) * 2)) 259 #define DIDSR_PCDS_CLK(n, clk) (clk << ((n) * 2)) 260 #define DIDSR_PCDS_MASK(n) (3 << ((n) * 2)) 261 262 /* ----------------------------------------------------------------------------- 263 * Display Timing Generation Registers 264 */ 265 266 #define HDSR 0x00040 267 #define HDER 0x00044 268 #define VDSR 0x00048 269 #define VDER 0x0004c 270 #define HCR 0x00050 271 #define HSWR 0x00054 272 #define VCR 0x00058 273 #define VSPR 0x0005c 274 #define EQWR 0x00060 275 #define SPWR 0x00064 276 #define CLAMPSR 0x00070 277 #define CLAMPWR 0x00074 278 #define DESR 0x00078 279 #define DEWR 0x0007c 280 281 /* ----------------------------------------------------------------------------- 282 * Display Attribute Registers 283 */ 284 285 #define CP1TR 0x00080 286 #define CP2TR 0x00084 287 #define CP3TR 0x00088 288 #define CP4TR 0x0008c 289 290 #define DOOR 0x00090 291 #define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 292 #define CDER 0x00094 293 #define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 294 #define BPOR 0x00098 295 #define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 296 297 #define RINTOFSR 0x0009c 298 299 #define DSHPR 0x000c8 300 #define DSHPR_CODE (0x7776 << 16) 301 #define DSHPR_PRIH (0xa << 4) 302 #define DSHPR_PRIL_BPP16 (0x8 << 0) 303 #define DSHPR_PRIL_BPP32 (0x9 << 0) 304 305 /* ----------------------------------------------------------------------------- 306 * Display Plane Registers 307 */ 308 309 #define PLANE_OFF 0x00100 310 311 #define PnMR 0x00100 /* plane 1 */ 312 #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ 313 #define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ 314 #define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ 315 #define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ 316 #define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ 317 #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ 318 #define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ 319 #define PnMR_WAE (1 << 16) /* Wrap around Enable */ 320 #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ 321 #define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ 322 #define PnMR_SPIM_EOR (2 << 12) /* EOR */ 323 #define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ 324 #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ 325 #define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ 326 #define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ 327 #define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ 328 #define PnMR_DC (1 << 7) /* Display Area Change */ 329 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 330 #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ 331 #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 332 #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ 333 #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ 334 #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ 335 #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ 336 #define PnMR_DDDF_YC (3 << 0) /* YC */ 337 #define PnMR_DDDF_MASK (3 << 0) 338 339 #define PnMWR 0x00104 340 341 #define PnALPHAR 0x00108 342 #define PnALPHAR_ABIT_1 (0 << 12) 343 #define PnALPHAR_ABIT_0 (1 << 12) 344 #define PnALPHAR_ABIT_X (2 << 12) 345 346 #define PnDSXR 0x00110 347 #define PnDSYR 0x00114 348 #define PnDPXR 0x00118 349 #define PnDPYR 0x0011c 350 351 #define PnDSA0R 0x00120 352 #define PnDSA1R 0x00124 353 #define PnDSA2R 0x00128 354 #define PnDSA_MASK 0xfffffff0 355 356 #define PnSPXR 0x00130 357 #define PnSPYR 0x00134 358 #define PnWASPR 0x00138 359 #define PnWAMWR 0x0013c 360 361 #define PnBTR 0x00140 362 363 #define PnTC1R 0x00144 364 #define PnTC2R 0x00148 365 #define PnTC3R 0x0014c 366 #define PnTC3R_CODE (0x66 << 24) 367 368 #define PnMLR 0x00150 369 370 #define PnSWAPR 0x00180 371 #define PnSWAPR_DIGN (1 << 4) 372 #define PnSWAPR_SPQW (1 << 3) 373 #define PnSWAPR_SPLW (1 << 2) 374 #define PnSWAPR_SPWD (1 << 1) 375 #define PnSWAPR_SPBY (1 << 0) 376 377 #define PnDDCR 0x00184 378 #define PnDDCR_CODE (0x7775 << 16) 379 #define PnDDCR_LRGB1 (1 << 11) 380 #define PnDDCR_LRGB0 (1 << 10) 381 382 #define PnDDCR2 0x00188 383 #define PnDDCR2_CODE (0x7776 << 16) 384 #define PnDDCR2_NV21 (1 << 5) 385 #define PnDDCR2_Y420 (1 << 4) 386 #define PnDDCR2_DIVU (1 << 1) 387 #define PnDDCR2_DIVY (1 << 0) 388 389 #define PnDDCR4 0x00190 390 #define PnDDCR4_CODE (0x7766 << 16) 391 #define PnDDCR4_SDFS_RGB (0 << 4) 392 #define PnDDCR4_SDFS_YC (5 << 4) 393 #define PnDDCR4_SDFS_MASK (7 << 4) 394 #define PnDDCR4_EDF_NONE (0 << 0) 395 #define PnDDCR4_EDF_ARGB8888 (1 << 0) 396 #define PnDDCR4_EDF_RGB888 (2 << 0) 397 #define PnDDCR4_EDF_RGB666 (3 << 0) 398 #define PnDDCR4_EDF_MASK (7 << 0) 399 400 #define APnMR 0x0a100 401 #define APnMR_WAE (1 << 16) /* Wrap around Enable */ 402 #define APnMR_DC (1 << 7) /* Display Area Change */ 403 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 404 #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 405 406 #define APnMWR 0x0a104 407 408 #define APnDSXR 0x0a110 409 #define APnDSYR 0x0a114 410 #define APnDPXR 0x0a118 411 #define APnDPYR 0x0a11c 412 413 #define APnDSA0R 0x0a120 414 #define APnDSA1R 0x0a124 415 #define APnDSA2R 0x0a128 416 417 #define APnSPXR 0x0a130 418 #define APnSPYR 0x0a134 419 #define APnWASPR 0x0a138 420 #define APnWAMWR 0x0a13c 421 422 #define APnBTR 0x0a140 423 424 #define APnMLR 0x0a150 425 #define APnSWAPR 0x0a180 426 427 /* ----------------------------------------------------------------------------- 428 * Display Capture Registers 429 */ 430 431 #define DCMR 0x0c100 432 #define DCMWR 0x0c104 433 #define DCSAR 0x0c120 434 #define DCMLR 0x0c150 435 436 /* ----------------------------------------------------------------------------- 437 * Color Palette Registers 438 */ 439 440 #define CP1_000R 0x01000 441 #define CP1_255R 0x013fc 442 #define CP2_000R 0x02000 443 #define CP2_255R 0x023fc 444 #define CP3_000R 0x03000 445 #define CP3_255R 0x033fc 446 #define CP4_000R 0x04000 447 #define CP4_255R 0x043fc 448 449 /* ----------------------------------------------------------------------------- 450 * External Synchronization Control Registers 451 */ 452 453 #define ESCR 0x10000 454 #define ESCR2 0x31000 455 #define ESCR_DCLKOINV (1 << 25) 456 #define ESCR_DCLKSEL_DCLKIN (0 << 20) 457 #define ESCR_DCLKSEL_CLKS (1 << 20) 458 #define ESCR_DCLKSEL_MASK (1 << 20) 459 #define ESCR_DCLKDIS (1 << 16) 460 #define ESCR_SYNCSEL_OFF (0 << 8) 461 #define ESCR_SYNCSEL_EXVSYNC (2 << 8) 462 #define ESCR_SYNCSEL_EXHSYNC (3 << 8) 463 #define ESCR_FRQSEL_MASK (0x3f << 0) 464 465 #define OTAR 0x10004 466 #define OTAR2 0x31004 467 468 /* ----------------------------------------------------------------------------- 469 * Dual Display Output Control Registers 470 */ 471 472 #define DORCR 0x11000 473 #define DORCR_PG2T (1 << 30) 474 #define DORCR_DK2S (1 << 28) 475 #define DORCR_PG2D_DS1 (0 << 24) 476 #define DORCR_PG2D_DS2 (1 << 24) 477 #define DORCR_PG2D_FIX0 (2 << 24) 478 #define DORCR_PG2D_DOOR (3 << 24) 479 #define DORCR_PG2D_MASK (3 << 24) 480 #define DORCR_DR1D (1 << 21) 481 #define DORCR_PG1D_DS1 (0 << 16) 482 #define DORCR_PG1D_DS2 (1 << 16) 483 #define DORCR_PG1D_FIX0 (2 << 16) 484 #define DORCR_PG1D_DOOR (3 << 16) 485 #define DORCR_PG1D_MASK (3 << 16) 486 #define DORCR_RGPV (1 << 4) 487 #define DORCR_DPRS (1 << 0) 488 489 #define DPTSR 0x11004 490 #define DPTSR_PnDK(n) (1 << ((n) + 16)) 491 #define DPTSR_PnTS(n) (1 << (n)) 492 493 #define DAPTSR 0x11008 494 #define DAPTSR_APnDK(n) (1 << ((n) + 16)) 495 #define DAPTSR_APnTS(n) (1 << (n)) 496 497 #define DS1PR 0x11020 498 #define DS2PR 0x11024 499 500 /* ----------------------------------------------------------------------------- 501 * YC-RGB Conversion Coefficient Registers 502 */ 503 504 #define YNCR 0x11080 505 #define YNOR 0x11084 506 #define CRNOR 0x11088 507 #define CBNOR 0x1108c 508 #define RCRCR 0x11090 509 #define GCRCR 0x11094 510 #define GCBCR 0x11098 511 #define BCBCR 0x1109c 512 513 #endif /* __RCAR_DU_REGS_H__ */ 514