1 /*********************************************************************** 2 ;* File Name : TMSCSIM.H * 3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter * 4 ;* Device Driver * 5 ;***********************************************************************/ 6 /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */ 7 8 #ifndef _TMSCSIM_H 9 #define _TMSCSIM_H 10 11 #include <linux/types.h> 12 13 #define SCSI_IRQ_NONE 255 14 15 #define MAX_ADAPTER_NUM 4 16 #define MAX_SG_LIST_BUF 16 /* Not used */ 17 #define MAX_SCSI_ID 8 18 #define MAX_SRB_CNT 50 /* Max number of started commands */ 19 20 #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ 21 22 /* 23 ;----------------------------------------------------------------------- 24 ; SCSI Request Block 25 ;----------------------------------------------------------------------- 26 */ 27 struct dc390_srb 28 { 29 //u8 CmdBlock[12]; 30 31 struct dc390_srb *pNextSRB; 32 struct dc390_dcb *pSRBDCB; 33 struct scsi_cmnd *pcmd; 34 struct scatterlist *pSegmentList; 35 36 struct scatterlist Segmentx; /* make a one entry of S/G list table */ 37 38 unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A 39 in CPU endianness. We're only getting 32-bit bus 40 addresses by default */ 41 unsigned long SGToBeXferLen; /*; to be xfer length */ 42 unsigned long TotalXferredLen; 43 unsigned long SavedTotXLen; 44 unsigned long Saved_Ptr; 45 u32 SRBState; 46 47 u8 SRBStatus; 48 u8 SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ 49 /*; b4-settimeout,b5-Residual valid */ 50 u8 AdaptStatus; 51 u8 TargetStatus; 52 53 u8 ScsiPhase; 54 s8 TagNumber; 55 u8 SGIndex; 56 u8 SGcount; 57 58 u8 MsgCnt; 59 u8 EndMessage; 60 61 u8 MsgInBuf[6]; 62 u8 MsgOutBuf[6]; 63 64 //u8 IORBFlag; /*;81h-Reset, 2-retry */ 65 }; 66 67 68 /* 69 ;----------------------------------------------------------------------- 70 ; Device Control Block 71 ;----------------------------------------------------------------------- 72 */ 73 struct dc390_dcb 74 { 75 struct dc390_dcb *pNextDCB; 76 struct dc390_acb *pDCBACB; 77 78 /* Queued SRBs */ 79 struct dc390_srb *pGoingSRB; 80 struct dc390_srb *pGoingLast; 81 struct dc390_srb *pActiveSRB; 82 u8 GoingSRBCnt; 83 84 u32 TagMask; 85 86 u8 TargetID; /*; SCSI Target ID (SCSI Only) */ 87 u8 TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 88 u8 DevMode; 89 u8 DCBFlag; 90 91 u8 CtrlR1; 92 u8 CtrlR3; 93 u8 CtrlR4; 94 95 u8 SyncMode; /*; 0:async mode */ 96 u8 NegoPeriod; /*;for nego. */ 97 u8 SyncPeriod; /*;for reg. */ 98 u8 SyncOffset; /*;for reg. and nego.(low nibble) */ 99 }; 100 101 102 /* 103 ;----------------------------------------------------------------------- 104 ; Adapter Control Block 105 ;----------------------------------------------------------------------- 106 */ 107 struct dc390_acb 108 { 109 struct Scsi_Host *pScsiHost; 110 u16 IOPortBase; 111 u8 IRQLevel; 112 u8 status; 113 114 u8 SRBCount; 115 u8 AdapterIndex; /*; nth Adapter this driver */ 116 u8 DCBCnt; 117 118 u8 TagMaxNum; 119 u8 ACBFlag; 120 u8 Gmode2; 121 u8 scan_devices; 122 123 struct dc390_dcb *pLinkDCB; 124 struct dc390_dcb *pLastDCB; 125 struct dc390_dcb *pDCBRunRobin; 126 127 struct dc390_dcb *pActiveDCB; 128 struct dc390_srb *pFreeSRB; 129 struct dc390_srb *pTmpSRB; 130 131 u8 msgin123[4]; 132 u8 Connected; 133 u8 pad; 134 135 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0) 136 spinlock_t lock; 137 #endif 138 u8 sel_timeout; 139 u8 glitch_cfg; 140 141 u8 MsgLen; 142 u8 Ignore_IRQ; /* Not used */ 143 144 struct pci_dev *pdev; 145 146 unsigned long last_reset; 147 unsigned long Cmds; 148 u32 SelLost; 149 u32 SelConn; 150 u32 CmdInQ; 151 u32 CmdOutOfSRB; 152 153 struct dc390_srb TmpSRB; 154 struct dc390_srb SRB_array[MAX_SRB_CNT]; /* 50 SRBs */ 155 }; 156 157 158 /*;-----------------------------------------------------------------------*/ 159 160 161 #define BIT31 0x80000000 162 #define BIT30 0x40000000 163 #define BIT29 0x20000000 164 #define BIT28 0x10000000 165 #define BIT27 0x08000000 166 #define BIT26 0x04000000 167 #define BIT25 0x02000000 168 #define BIT24 0x01000000 169 #define BIT23 0x00800000 170 #define BIT22 0x00400000 171 #define BIT21 0x00200000 172 #define BIT20 0x00100000 173 #define BIT19 0x00080000 174 #define BIT18 0x00040000 175 #define BIT17 0x00020000 176 #define BIT16 0x00010000 177 #define BIT15 0x00008000 178 #define BIT14 0x00004000 179 #define BIT13 0x00002000 180 #define BIT12 0x00001000 181 #define BIT11 0x00000800 182 #define BIT10 0x00000400 183 #define BIT9 0x00000200 184 #define BIT8 0x00000100 185 #define BIT7 0x00000080 186 #define BIT6 0x00000040 187 #define BIT5 0x00000020 188 #define BIT4 0x00000010 189 #define BIT3 0x00000008 190 #define BIT2 0x00000004 191 #define BIT1 0x00000002 192 #define BIT0 0x00000001 193 194 /*;---UnitCtrlFlag */ 195 #define UNIT_ALLOCATED BIT0 196 #define UNIT_INFO_CHANGED BIT1 197 #define FORMATING_MEDIA BIT2 198 #define UNIT_RETRY BIT3 199 200 /*;---UnitFlags */ 201 #define DASD_SUPPORT BIT0 202 #define SCSI_SUPPORT BIT1 203 #define ASPI_SUPPORT BIT2 204 205 /*;----SRBState machine definition */ 206 #define SRB_FREE 0 207 #define SRB_WAIT BIT0 208 #define SRB_READY BIT1 209 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/ 210 #define SRB_MSGIN BIT3 211 #define SRB_MSGIN_MULTI BIT4 212 #define SRB_COMMAND BIT5 213 #define SRB_START_ BIT6 /*;arbitration+msg_out+command_out*/ 214 #define SRB_DISCONNECT BIT7 215 #define SRB_DATA_XFER BIT8 216 #define SRB_XFERPAD BIT9 217 #define SRB_STATUS BIT10 218 #define SRB_COMPLETED BIT11 219 #define SRB_ABORT_SENT BIT12 220 #define DO_SYNC_NEGO BIT13 221 #define SRB_UNEXPECT_RESEL BIT14 222 223 /*;---SRBstatus */ 224 #define SRB_OK BIT0 225 #define ABORTION BIT1 226 #define OVER_RUN BIT2 227 #define UNDER_RUN BIT3 228 #define PARITY_ERROR BIT4 229 #define SRB_ERROR BIT5 230 231 /*;---ACBFlag */ 232 #define RESET_DEV BIT0 233 #define RESET_DETECT BIT1 234 #define RESET_DONE BIT2 235 236 /*;---DCBFlag */ 237 #define ABORT_DEV_ BIT0 238 239 /*;---SRBFlag */ 240 #define DATAOUT BIT7 241 #define DATAIN BIT6 242 #define RESIDUAL_VALID BIT5 243 #define ENABLE_TIMER BIT4 244 #define RESET_DEV0 BIT2 245 #define ABORT_DEV BIT1 246 #define AUTO_REQSENSE BIT0 247 248 /*;---Adapter status */ 249 #define H_STATUS_GOOD 0 250 #define H_SEL_TIMEOUT 0x11 251 #define H_OVER_UNDER_RUN 0x12 252 #define H_UNEXP_BUS_FREE 0x13 253 #define H_TARGET_PHASE_F 0x14 254 #define H_INVALID_CCB_OP 0x16 255 #define H_LINK_CCB_BAD 0x17 256 #define H_BAD_TARGET_DIR 0x18 257 #define H_DUPLICATE_CCB 0x19 258 #define H_BAD_CCB_OR_SG 0x1A 259 #define H_ABORT 0x0FF 260 261 /* cmd->result */ 262 #define RES_TARGET 0x000000FF /* Target State */ 263 #define RES_TARGET_LNX STATUS_MASK /* Only official ... */ 264 #define RES_ENDMSG 0x0000FF00 /* End Message */ 265 #define RES_DID 0x00FF0000 /* DID_ codes */ 266 #define RES_DRV 0xFF000000 /* DRIVER_ codes */ 267 268 #define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)) 269 #define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)) 270 271 #define SET_RES_TARGET(who, tgt) do { who &= ~RES_TARGET; who |= (int)(tgt); } while (0) 272 #define SET_RES_TARGET_LNX(who, tgt) do { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } while (0) 273 #define SET_RES_MSG(who, msg) do { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } while (0) 274 #define SET_RES_DID(who, did) do { who &= ~RES_DID; who |= (int)(did) << 16; } while (0) 275 #define SET_RES_DRV(who, drv) do { who &= ~RES_DRV; who |= (int)(drv) << 24; } while (0) 276 277 /*;---Sync_Mode */ 278 #define SYNC_DISABLE 0 279 #define SYNC_ENABLE BIT0 280 #define SYNC_NEGO_DONE BIT1 281 #define WIDE_ENABLE BIT2 /* Not used ;-) */ 282 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ 283 #define EN_TAG_QUEUEING BIT4 284 #define EN_ATN_STOP BIT5 285 286 #define SYNC_NEGO_OFFSET 15 287 288 /*;---SCSI bus phase*/ 289 #define SCSI_DATA_OUT 0 290 #define SCSI_DATA_IN 1 291 #define SCSI_COMMAND 2 292 #define SCSI_STATUS_ 3 293 #define SCSI_NOP0 4 294 #define SCSI_NOP1 5 295 #define SCSI_MSG_OUT 6 296 #define SCSI_MSG_IN 7 297 298 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */ 299 #define ABORT_TAG 0x0d 300 301 /* 302 * SISC query queue 303 */ 304 typedef struct { 305 dma_addr_t saved_dma_handle; 306 } dc390_cmd_scp_t; 307 308 /* 309 ;========================================================== 310 ; EEPROM byte offset 311 ;========================================================== 312 */ 313 typedef struct _EEprom 314 { 315 u8 EE_MODE1; 316 u8 EE_SPEED; 317 u8 xx1; 318 u8 xx2; 319 } EEprom, *PEEprom; 320 321 #define REAL_EE_ADAPT_SCSI_ID 64 322 #define REAL_EE_MODE2 65 323 #define REAL_EE_DELAY 66 324 #define REAL_EE_TAG_CMD_NUM 67 325 326 #define EE_ADAPT_SCSI_ID 32 327 #define EE_MODE2 33 328 #define EE_DELAY 34 329 #define EE_TAG_CMD_NUM 35 330 331 #define EE_LEN 40 332 333 /*; EE_MODE1 bits definition*/ 334 #define PARITY_CHK_ BIT0 335 #define SYNC_NEGO_ BIT1 336 #define EN_DISCONNECT_ BIT2 337 #define SEND_START_ BIT3 338 #define TAG_QUEUEING_ BIT4 339 340 /*; EE_MODE2 bits definition*/ 341 #define MORE2_DRV BIT0 342 #define GREATER_1G BIT1 343 #define RST_SCSI_BUS BIT2 344 #define ACTIVE_NEGATION BIT3 345 #define NO_SEEK BIT4 346 #define LUN_CHECK BIT5 347 348 #define ENABLE_CE 1 349 #define DISABLE_CE 0 350 #define EEPROM_READ 0x80 351 352 /* 353 ;========================================================== 354 ; AMD 53C974 Registers bit Definition 355 ;========================================================== 356 */ 357 /* 358 ;==================== 359 ; SCSI Register 360 ;==================== 361 */ 362 363 /*; Command Reg.(+0CH) (rw) */ 364 #define DMA_COMMAND BIT7 365 #define NOP_CMD 0 366 #define CLEAR_FIFO_CMD 1 367 #define RST_DEVICE_CMD 2 368 #define RST_SCSI_BUS_CMD 3 369 370 #define INFO_XFER_CMD 0x10 371 #define INITIATOR_CMD_CMPLTE 0x11 372 #define MSG_ACCEPTED_CMD 0x12 373 #define XFER_PAD_BYTE 0x18 374 #define SET_ATN_CMD 0x1A 375 #define RESET_ATN_CMD 0x1B 376 377 #define SEL_WO_ATN 0x41 /* currently not used */ 378 #define SEL_W_ATN 0x42 379 #define SEL_W_ATN_STOP 0x43 380 #define SEL_W_ATN3 0x46 381 #define EN_SEL_RESEL 0x44 382 #define DIS_SEL_RESEL 0x45 /* currently not used */ 383 #define RESEL 0x40 /* " */ 384 #define RESEL_ATN3 0x47 /* " */ 385 386 #define DATA_XFER_CMD INFO_XFER_CMD 387 388 389 /*; SCSI Status Reg.(+10H) (r) */ 390 #define INTERRUPT BIT7 391 #define ILLEGAL_OP_ERR BIT6 392 #define PARITY_ERR BIT5 393 #define COUNT_2_ZERO BIT4 394 #define GROUP_CODE_VALID BIT3 395 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0) 396 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */ 397 398 /*; Interrupt Status Reg.(+14H) (r) */ 399 #define SCSI_RESET BIT7 400 #define INVALID_CMD BIT6 401 #define DISCONNECTED BIT5 402 #define SERVICE_REQUEST BIT4 403 #define SUCCESSFUL_OP BIT3 404 #define RESELECTED BIT2 405 #define SEL_ATTENTION BIT1 406 #define SELECTED BIT0 407 408 /*; Internal State Reg.(+18H) (r) */ 409 #define SYNC_OFFSET_FLAG BIT3 410 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0) 411 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */ 412 413 /*; Clock Factor Reg.(+24H) (w) */ 414 #define CLK_FREQ_40MHZ 0 415 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0) 416 #define CLK_FREQ_30MHZ (BIT2+BIT1) 417 #define CLK_FREQ_25MHZ (BIT2+BIT0) 418 #define CLK_FREQ_20MHZ BIT2 419 #define CLK_FREQ_15MHZ (BIT1+BIT0) 420 #define CLK_FREQ_10MHZ BIT1 421 422 /*; Control Reg. 1(+20H) (rw) */ 423 #define EXTENDED_TIMING BIT7 424 #define DIS_INT_ON_SCSI_RST BIT6 425 #define PARITY_ERR_REPO BIT4 426 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */ 427 428 /*; Control Reg. 2(+2CH) (rw) */ 429 #define EN_FEATURE BIT6 430 #define EN_SCSI2_CMD BIT3 431 432 /*; Control Reg. 3(+30H) (rw) */ 433 #define ID_MSG_CHECK BIT7 434 #define EN_QTAG_MSG BIT6 435 #define EN_GRP2_CMD BIT5 436 #define FAST_SCSI BIT4 /* ;10MB/SEC */ 437 #define FAST_CLK BIT3 /* ;25 - 40 MHZ */ 438 439 /*; Control Reg. 4(+34H) (rw) */ 440 #define EATER_12NS 0 441 #define EATER_25NS BIT7 442 #define EATER_35NS BIT6 443 #define EATER_0NS (BIT7+BIT6) 444 #define REDUCED_POWER BIT5 445 #define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */ 446 #define NEGATE_REQACKDATA BIT2 447 #define NEGATE_REQACK BIT3 448 449 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2))) 450 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0) 451 452 /* 453 ;==================== 454 ; DMA Register 455 ;==================== 456 */ 457 /*; DMA Command Reg.(+40H) (rw) */ 458 #define READ_DIRECTION BIT7 459 #define WRITE_DIRECTION 0 460 #define EN_DMA_INT BIT6 461 #define EN_PAGE_INT BIT5 /* page transfer interrupt enable */ 462 #define MAP_TO_MDL BIT4 463 #define DIAGNOSTIC BIT2 464 #define DMA_IDLE_CMD 0 465 #define DMA_BLAST_CMD BIT0 466 #define DMA_ABORT_CMD BIT1 467 #define DMA_START_CMD (BIT1+BIT0) 468 469 /*; DMA Status Reg.(+54H) (r) */ 470 #define PCI_MS_ABORT BIT6 471 #define BLAST_COMPLETE BIT5 472 #define SCSI_INTERRUPT BIT4 473 #define DMA_XFER_DONE BIT3 474 #define DMA_XFER_ABORT BIT2 475 #define DMA_XFER_ERROR BIT1 476 #define POWER_DOWN BIT0 477 478 /*; DMA SCSI Bus and Ctrl.(+70H) */ 479 #define EN_INT_ON_PCI_ABORT BIT25 480 #define WRT_ERASE_DMA_STAT BIT24 481 #define PW_DOWN_CTRL BIT21 482 #define SCSI_BUSY BIT20 483 #define SCLK BIT19 484 #define SCAM BIT18 485 #define SCSI_LINES 0x0003ffff 486 487 /* 488 ;========================================================== 489 ; SCSI Chip register address offset 490 ;========================================================== 491 ;Registers are rw unless declared otherwise 492 */ 493 #define CtcReg_Low 0x00 /* r curr. transfer count */ 494 #define CtcReg_Mid 0x04 /* r */ 495 #define CtcReg_High 0x38 /* r */ 496 #define ScsiFifo 0x08 497 #define ScsiCmd 0x0C 498 #define Scsi_Status 0x10 /* r */ 499 #define INT_Status 0x14 /* r */ 500 #define Sync_Period 0x18 /* w */ 501 #define Sync_Offset 0x1C /* w */ 502 #define Clk_Factor 0x24 /* w */ 503 #define CtrlReg1 0x20 504 #define CtrlReg2 0x2C 505 #define CtrlReg3 0x30 506 #define CtrlReg4 0x34 507 #define DMA_Cmd 0x40 508 #define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */ 509 #define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */ 510 #define DMA_Wk_ByteCntr 0x4C /* r working byte counter */ 511 #define DMA_Wk_AddrCntr 0x50 /* r working address counter */ 512 #define DMA_Status 0x54 /* r */ 513 #define DMA_MDL_Addr 0x58 /* rw starting MDL address */ 514 #define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */ 515 #define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */ 516 517 #define StcReg_Low CtcReg_Low /* w start transfer count */ 518 #define StcReg_Mid CtcReg_Mid /* w */ 519 #define StcReg_High CtcReg_High /* w */ 520 #define Scsi_Dest_ID Scsi_Status /* w */ 521 #define Scsi_TimeOut INT_Status /* w */ 522 #define Intern_State Sync_Period /* r */ 523 #define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */ 524 525 526 #define DC390_read8(address) \ 527 (inb (pACB->IOPortBase + (address))) 528 529 #define DC390_read8_(address, base) \ 530 (inb ((u16)(base) + (address))) 531 532 #define DC390_read16(address) \ 533 (inw (pACB->IOPortBase + (address))) 534 535 #define DC390_read32(address) \ 536 (inl (pACB->IOPortBase + (address))) 537 538 #define DC390_write8(address,value) \ 539 outb ((value), pACB->IOPortBase + (address)) 540 541 #define DC390_write8_(address,value,base) \ 542 outb ((value), (u16)(base) + (address)) 543 544 #define DC390_write16(address,value) \ 545 outw ((value), pACB->IOPortBase + (address)) 546 547 #define DC390_write32(address,value) \ 548 outl ((value), pACB->IOPortBase + (address)) 549 550 551 #endif /* _TMSCSIM_H */ 552