1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
2 #define _ASM_POWERPC_MMU_HASH64_H_
3 /*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15 #include <asm/asm-compat.h>
16 #include <asm/page.h>
17
18 /*
19 * This is necessary to get the definition of PGTABLE_RANGE which we
20 * need for various slices related matters. Note that this isn't the
21 * complete pgtable.h but only a portion of it.
22 */
23 #include <asm/pgtable-ppc64.h>
24 #include <asm/bug.h>
25 #include <asm/processor.h>
26
27 /*
28 * SLB
29 */
30
31 #define SLB_NUM_BOLTED 3
32 #define SLB_CACHE_ENTRIES 8
33 #define SLB_MIN_SIZE 32
34
35 /* Bits in the SLB ESID word */
36 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
37
38 /* Bits in the SLB VSID word */
39 #define SLB_VSID_SHIFT 12
40 #define SLB_VSID_SHIFT_1T 24
41 #define SLB_VSID_SSIZE_SHIFT 62
42 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
43 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
44 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
45 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
46 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
47 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
48 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
49 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
50 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
51 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
52 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
53 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
54 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
55 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
56
57 #define SLB_VSID_KERNEL (SLB_VSID_KP)
58 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
59
60 #define SLBIE_C (0x08000000)
61 #define SLBIE_SSIZE_SHIFT 25
62
63 /*
64 * Hash table
65 */
66
67 #define HPTES_PER_GROUP 8
68
69 #define HPTE_V_SSIZE_SHIFT 62
70 #define HPTE_V_AVPN_SHIFT 7
71 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
72 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
73 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
74 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
75 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
76 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
77 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
78 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
79
80 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
81 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
82 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
83 #define HPTE_R_RPN_SHIFT 12
84 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
85 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
86 #define HPTE_R_N ASM_CONST(0x0000000000000004)
87 #define HPTE_R_G ASM_CONST(0x0000000000000008)
88 #define HPTE_R_M ASM_CONST(0x0000000000000010)
89 #define HPTE_R_I ASM_CONST(0x0000000000000020)
90 #define HPTE_R_W ASM_CONST(0x0000000000000040)
91 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
92 #define HPTE_R_C ASM_CONST(0x0000000000000080)
93 #define HPTE_R_R ASM_CONST(0x0000000000000100)
94 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
95
96 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
97 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
98
99 /* Values for PP (assumes Ks=0, Kp=1) */
100 #define PP_RWXX 0 /* Supervisor read/write, User none */
101 #define PP_RWRX 1 /* Supervisor read/write, User read */
102 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
103 #define PP_RXRX 3 /* Supervisor read, User read */
104 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
105
106 /* Fields for tlbiel instruction in architecture 2.06 */
107 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
108 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
109 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
110 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
111 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
112 #define TLBIEL_INVAL_SET_SHIFT 12
113
114 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
115
116 #ifndef __ASSEMBLY__
117
118 struct hash_pte {
119 __be64 v;
120 __be64 r;
121 };
122
123 extern struct hash_pte *htab_address;
124 extern unsigned long htab_size_bytes;
125 extern unsigned long htab_hash_mask;
126
127 /*
128 * Page size definition
129 *
130 * shift : is the "PAGE_SHIFT" value for that page size
131 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
132 * directly to a slbmte "vsid" value
133 * penc : is the HPTE encoding mask for the "LP" field:
134 *
135 */
136 struct mmu_psize_def
137 {
138 unsigned int shift; /* number of bits */
139 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
140 unsigned int tlbiel; /* tlbiel supported for that page size */
141 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
142 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
143 };
144 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
145
shift_to_mmu_psize(unsigned int shift)146 static inline int shift_to_mmu_psize(unsigned int shift)
147 {
148 int psize;
149
150 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
151 if (mmu_psize_defs[psize].shift == shift)
152 return psize;
153 return -1;
154 }
155
mmu_psize_to_shift(unsigned int mmu_psize)156 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
157 {
158 if (mmu_psize_defs[mmu_psize].shift)
159 return mmu_psize_defs[mmu_psize].shift;
160 BUG();
161 }
162
163 #endif /* __ASSEMBLY__ */
164
165 /*
166 * Segment sizes.
167 * These are the values used by hardware in the B field of
168 * SLB entries and the first dword of MMU hashtable entries.
169 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
170 */
171 #define MMU_SEGSIZE_256M 0
172 #define MMU_SEGSIZE_1T 1
173
174 /*
175 * encode page number shift.
176 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
177 * 12 bits. This enable us to address upto 76 bit va.
178 * For hpt hash from a va we can ignore the page size bits of va and for
179 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
180 * we work in all cases including 4k page size.
181 */
182 #define VPN_SHIFT 12
183
184 /*
185 * HPTE Large Page (LP) details
186 */
187 #define LP_SHIFT 12
188 #define LP_BITS 8
189 #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
190
191 #ifndef __ASSEMBLY__
192
slb_vsid_shift(int ssize)193 static inline int slb_vsid_shift(int ssize)
194 {
195 if (ssize == MMU_SEGSIZE_256M)
196 return SLB_VSID_SHIFT;
197 return SLB_VSID_SHIFT_1T;
198 }
199
segment_shift(int ssize)200 static inline int segment_shift(int ssize)
201 {
202 if (ssize == MMU_SEGSIZE_256M)
203 return SID_SHIFT;
204 return SID_SHIFT_1T;
205 }
206
207 /*
208 * The current system page and segment sizes
209 */
210 extern int mmu_linear_psize;
211 extern int mmu_virtual_psize;
212 extern int mmu_vmalloc_psize;
213 extern int mmu_vmemmap_psize;
214 extern int mmu_io_psize;
215 extern int mmu_kernel_ssize;
216 extern int mmu_highuser_ssize;
217 extern u16 mmu_slb_size;
218 extern unsigned long tce_alloc_start, tce_alloc_end;
219
220 /*
221 * If the processor supports 64k normal pages but not 64k cache
222 * inhibited pages, we have to be prepared to switch processes
223 * to use 4k pages when they create cache-inhibited mappings.
224 * If this is the case, mmu_ci_restrictions will be set to 1.
225 */
226 extern int mmu_ci_restrictions;
227
228 /*
229 * This computes the AVPN and B fields of the first dword of a HPTE,
230 * for use when we want to match an existing PTE. The bottom 7 bits
231 * of the returned value are zero.
232 */
hpte_encode_avpn(unsigned long vpn,int psize,int ssize)233 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
234 int ssize)
235 {
236 unsigned long v;
237 /*
238 * The AVA field omits the low-order 23 bits of the 78 bits VA.
239 * These bits are not needed in the PTE, because the
240 * low-order b of these bits are part of the byte offset
241 * into the virtual page and, if b < 23, the high-order
242 * 23-b of these bits are always used in selecting the
243 * PTEGs to be searched
244 */
245 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
246 v <<= HPTE_V_AVPN_SHIFT;
247 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
248 return v;
249 }
250
251 /*
252 * This function sets the AVPN and L fields of the HPTE appropriately
253 * using the base page size and actual page size.
254 */
hpte_encode_v(unsigned long vpn,int base_psize,int actual_psize,int ssize)255 static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
256 int actual_psize, int ssize)
257 {
258 unsigned long v;
259 v = hpte_encode_avpn(vpn, base_psize, ssize);
260 if (actual_psize != MMU_PAGE_4K)
261 v |= HPTE_V_LARGE;
262 return v;
263 }
264
265 /*
266 * This function sets the ARPN, and LP fields of the HPTE appropriately
267 * for the page size. We assume the pa is already "clean" that is properly
268 * aligned for the requested page size
269 */
hpte_encode_r(unsigned long pa,int base_psize,int actual_psize)270 static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
271 int actual_psize)
272 {
273 /* A 4K page needs no special encoding */
274 if (actual_psize == MMU_PAGE_4K)
275 return pa & HPTE_R_RPN;
276 else {
277 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
278 unsigned int shift = mmu_psize_defs[actual_psize].shift;
279 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
280 }
281 }
282
283 /*
284 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
285 */
hpt_vpn(unsigned long ea,unsigned long vsid,int ssize)286 static inline unsigned long hpt_vpn(unsigned long ea,
287 unsigned long vsid, int ssize)
288 {
289 unsigned long mask;
290 int s_shift = segment_shift(ssize);
291
292 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
293 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
294 }
295
296 /*
297 * This hashes a virtual address
298 */
hpt_hash(unsigned long vpn,unsigned int shift,int ssize)299 static inline unsigned long hpt_hash(unsigned long vpn,
300 unsigned int shift, int ssize)
301 {
302 int mask;
303 unsigned long hash, vsid;
304
305 /* VPN_SHIFT can be atmost 12 */
306 if (ssize == MMU_SEGSIZE_256M) {
307 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
308 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
309 ((vpn & mask) >> (shift - VPN_SHIFT));
310 } else {
311 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
312 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
313 hash = vsid ^ (vsid << 25) ^
314 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
315 }
316 return hash & 0x7fffffffffUL;
317 }
318
319 extern int __hash_page_4K(unsigned long ea, unsigned long access,
320 unsigned long vsid, pte_t *ptep, unsigned long trap,
321 unsigned int local, int ssize, int subpage_prot);
322 extern int __hash_page_64K(unsigned long ea, unsigned long access,
323 unsigned long vsid, pte_t *ptep, unsigned long trap,
324 unsigned int local, int ssize);
325 struct mm_struct;
326 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
327 extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, unsigned long access, unsigned long trap);
328 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
329 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
330 pte_t *ptep, unsigned long trap, int local, int ssize,
331 unsigned int shift, unsigned int mmu_psize);
332 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
333 extern int __hash_page_thp(unsigned long ea, unsigned long access,
334 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
335 int local, int ssize, unsigned int psize);
336 #else
__hash_page_thp(unsigned long ea,unsigned long access,unsigned long vsid,pmd_t * pmdp,unsigned long trap,int local,int ssize,unsigned int psize)337 static inline int __hash_page_thp(unsigned long ea, unsigned long access,
338 unsigned long vsid, pmd_t *pmdp,
339 unsigned long trap, int local,
340 int ssize, unsigned int psize)
341 {
342 BUG();
343 return -1;
344 }
345 #endif
346 extern void hash_failure_debug(unsigned long ea, unsigned long access,
347 unsigned long vsid, unsigned long trap,
348 int ssize, int psize, int lpsize,
349 unsigned long pte);
350 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
351 unsigned long pstart, unsigned long prot,
352 int psize, int ssize);
353 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
354 int psize, int ssize);
355 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
356 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
357
358 extern void hpte_init_native(void);
359 extern void hpte_init_lpar(void);
360 extern void hpte_init_beat(void);
361 extern void hpte_init_beat_v3(void);
362
363 extern void slb_initialize(void);
364 extern void slb_flush_and_rebolt(void);
365
366 extern void slb_vmalloc_update(void);
367 extern void slb_set_size(u16 size);
368 #endif /* __ASSEMBLY__ */
369
370 /*
371 * VSID allocation (256MB segment)
372 *
373 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
374 * from mmu context id and effective segment id of the address.
375 *
376 * For user processes max context id is limited to ((1ul << 19) - 5)
377 * for kernel space, we use the top 4 context ids to map address as below
378 * NOTE: each context only support 64TB now.
379 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
380 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
381 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
382 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
383 *
384 * The proto-VSIDs are then scrambled into real VSIDs with the
385 * multiplicative hash:
386 *
387 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
388 *
389 * VSID_MULTIPLIER is prime, so in particular it is
390 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
391 * Because the modulus is 2^n-1 we can compute it efficiently without
392 * a divide or extra multiply (see below). The scramble function gives
393 * robust scattering in the hash table (at least based on some initial
394 * results).
395 *
396 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
397 * bad address. This enables us to consolidate bad address handling in
398 * hash_page.
399 *
400 * We also need to avoid the last segment of the last context, because that
401 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
402 * because of the modulo operation in vsid scramble. But the vmemmap
403 * (which is what uses region 0xf) will never be close to 64TB in size
404 * (it's 56 bytes per page of system memory).
405 */
406
407 #define CONTEXT_BITS 19
408 #define ESID_BITS 18
409 #define ESID_BITS_1T 6
410
411 /*
412 * 256MB segment
413 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
414 * available for user + kernel mapping. The top 4 contexts are used for
415 * kernel mapping. Each segment contains 2^28 bytes. Each
416 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
417 * (19 == 37 + 28 - 46).
418 */
419 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
420
421 /*
422 * This should be computed such that protovosid * vsid_mulitplier
423 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
424 */
425 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
426 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
427 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
428
429 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
430 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
431 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
432
433
434 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
435
436 /*
437 * This macro generates asm code to compute the VSID scramble
438 * function. Used in slb_allocate() and do_stab_bolted. The function
439 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
440 *
441 * rt = register continaing the proto-VSID and into which the
442 * VSID will be stored
443 * rx = scratch register (clobbered)
444 *
445 * - rt and rx must be different registers
446 * - The answer will end up in the low VSID_BITS bits of rt. The higher
447 * bits may contain other garbage, so you may need to mask the
448 * result.
449 */
450 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
451 lis rx,VSID_MULTIPLIER_##size@h; \
452 ori rx,rx,VSID_MULTIPLIER_##size@l; \
453 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
454 \
455 srdi rx,rt,VSID_BITS_##size; \
456 clrldi rt,rt,(64-VSID_BITS_##size); \
457 add rt,rt,rx; /* add high and low bits */ \
458 /* NOTE: explanation based on VSID_BITS_##size = 36 \
459 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
460 * 2^36-1+2^28-1. That in particular means that if r3 >= \
461 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
462 * the bit clear, r3 already has the answer we want, if it \
463 * doesn't, the answer is the low 36 bits of r3+1. So in all \
464 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
465 addi rx,rt,1; \
466 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
467 add rt,rt,rx
468
469 /* 4 bits per slice and we have one slice per 1TB */
470 #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
471
472 #ifndef __ASSEMBLY__
473
474 #ifdef CONFIG_PPC_SUBPAGE_PROT
475 /*
476 * For the sub-page protection option, we extend the PGD with one of
477 * these. Basically we have a 3-level tree, with the top level being
478 * the protptrs array. To optimize speed and memory consumption when
479 * only addresses < 4GB are being protected, pointers to the first
480 * four pages of sub-page protection words are stored in the low_prot
481 * array.
482 * Each page of sub-page protection words protects 1GB (4 bytes
483 * protects 64k). For the 3-level tree, each page of pointers then
484 * protects 8TB.
485 */
486 struct subpage_prot_table {
487 unsigned long maxaddr; /* only addresses < this are protected */
488 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
489 unsigned int *low_prot[4];
490 };
491
492 #define SBP_L1_BITS (PAGE_SHIFT - 2)
493 #define SBP_L2_BITS (PAGE_SHIFT - 3)
494 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
495 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
496 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
497 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
498
499 extern void subpage_prot_free(struct mm_struct *mm);
500 extern void subpage_prot_init_new_context(struct mm_struct *mm);
501 #else
subpage_prot_free(struct mm_struct * mm)502 static inline void subpage_prot_free(struct mm_struct *mm) {}
subpage_prot_init_new_context(struct mm_struct * mm)503 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
504 #endif /* CONFIG_PPC_SUBPAGE_PROT */
505
506 typedef unsigned long mm_context_id_t;
507 struct spinlock;
508
509 typedef struct {
510 mm_context_id_t id;
511 u16 user_psize; /* page size index */
512
513 #ifdef CONFIG_PPC_MM_SLICES
514 u64 low_slices_psize; /* SLB page size encodings */
515 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
516 #else
517 u16 sllp; /* SLB page size encoding */
518 #endif
519 unsigned long vdso_base;
520 #ifdef CONFIG_PPC_SUBPAGE_PROT
521 struct subpage_prot_table spt;
522 #endif /* CONFIG_PPC_SUBPAGE_PROT */
523 #ifdef CONFIG_PPC_ICSWX
524 struct spinlock *cop_lockp; /* guard acop and cop_pid */
525 unsigned long acop; /* mask of enabled coprocessor types */
526 unsigned int cop_pid; /* pid value used with coprocessors */
527 #endif /* CONFIG_PPC_ICSWX */
528 #ifdef CONFIG_PPC_64K_PAGES
529 /* for 4K PTE fragment support */
530 void *pte_frag;
531 #endif
532 } mm_context_t;
533
534
535 #if 0
536 /*
537 * The code below is equivalent to this function for arguments
538 * < 2^VSID_BITS, which is all this should ever be called
539 * with. However gcc is not clever enough to compute the
540 * modulus (2^n-1) without a second multiply.
541 */
542 #define vsid_scramble(protovsid, size) \
543 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
544
545 #else /* 1 */
546 #define vsid_scramble(protovsid, size) \
547 ({ \
548 unsigned long x; \
549 x = (protovsid) * VSID_MULTIPLIER_##size; \
550 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
551 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
552 })
553 #endif /* 1 */
554
555 /* Returns the segment size indicator for a user address */
user_segment_size(unsigned long addr)556 static inline int user_segment_size(unsigned long addr)
557 {
558 /* Use 1T segments if possible for addresses >= 1T */
559 if (addr >= (1UL << SID_SHIFT_1T))
560 return mmu_highuser_ssize;
561 return MMU_SEGSIZE_256M;
562 }
563
get_vsid(unsigned long context,unsigned long ea,int ssize)564 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
565 int ssize)
566 {
567 /*
568 * Bad address. We return VSID 0 for that
569 */
570 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
571 return 0;
572
573 if (ssize == MMU_SEGSIZE_256M)
574 return vsid_scramble((context << ESID_BITS)
575 | (ea >> SID_SHIFT), 256M);
576 return vsid_scramble((context << ESID_BITS_1T)
577 | (ea >> SID_SHIFT_1T), 1T);
578 }
579
580 /*
581 * This is only valid for addresses >= PAGE_OFFSET
582 *
583 * For kernel space, we use the top 4 context ids to map address as below
584 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
585 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
586 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
587 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
588 */
get_kernel_vsid(unsigned long ea,int ssize)589 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
590 {
591 unsigned long context;
592
593 /*
594 * kernel take the top 4 context from the available range
595 */
596 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
597 return get_vsid(context, ea, ssize);
598 }
599 #endif /* __ASSEMBLY__ */
600
601 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */
602