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1 /*
2  * ipr.h -- driver for IBM Power Linux RAID adapters
3  *
4  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5  *
6  * Copyright (C) 2003, 2004 IBM Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  *
22  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23  *				that broke 64bit platforms.
24  */
25 
26 #ifndef _IPR_H
27 #define _IPR_H
28 
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/blk-iopoll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
38 
39 /*
40  * Literals
41  */
42 #define IPR_DRIVER_VERSION "2.6.0"
43 #define IPR_DRIVER_DATE "(November 16, 2012)"
44 
45 /*
46  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47  *	ops per device for devices not running tagged command queuing.
48  *	This can be adjusted at runtime through sysfs device attributes.
49  */
50 #define IPR_MAX_CMD_PER_LUN				6
51 #define IPR_MAX_CMD_PER_ATA_LUN			1
52 
53 /*
54  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55  *	ops the mid-layer can send to the adapter.
56  */
57 #define IPR_NUM_BASE_CMD_BLKS			(ioa_cfg->max_cmds)
58 
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E	0x0339
60 
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE             0x034A
63 
64 #define IPR_SUBS_DEV_ID_2780	0x0264
65 #define IPR_SUBS_DEV_ID_5702	0x0266
66 #define IPR_SUBS_DEV_ID_5703	0x0278
67 #define IPR_SUBS_DEV_ID_572E	0x028D
68 #define IPR_SUBS_DEV_ID_573E	0x02D3
69 #define IPR_SUBS_DEV_ID_573D	0x02D4
70 #define IPR_SUBS_DEV_ID_571A	0x02C0
71 #define IPR_SUBS_DEV_ID_571B	0x02BE
72 #define IPR_SUBS_DEV_ID_571E	0x02BF
73 #define IPR_SUBS_DEV_ID_571F	0x02D5
74 #define IPR_SUBS_DEV_ID_572A	0x02C1
75 #define IPR_SUBS_DEV_ID_572B	0x02C2
76 #define IPR_SUBS_DEV_ID_572F	0x02C3
77 #define IPR_SUBS_DEV_ID_574E	0x030A
78 #define IPR_SUBS_DEV_ID_575B	0x030D
79 #define IPR_SUBS_DEV_ID_575C	0x0338
80 #define IPR_SUBS_DEV_ID_57B3	0x033A
81 #define IPR_SUBS_DEV_ID_57B7	0x0360
82 #define IPR_SUBS_DEV_ID_57B8	0x02C2
83 
84 #define IPR_SUBS_DEV_ID_57B4    0x033B
85 #define IPR_SUBS_DEV_ID_57B2    0x035F
86 #define IPR_SUBS_DEV_ID_57C0    0x0352
87 #define IPR_SUBS_DEV_ID_57C3    0x0353
88 #define IPR_SUBS_DEV_ID_57C4    0x0354
89 #define IPR_SUBS_DEV_ID_57C6    0x0357
90 #define IPR_SUBS_DEV_ID_57CC    0x035C
91 
92 #define IPR_SUBS_DEV_ID_57B5    0x033C
93 #define IPR_SUBS_DEV_ID_57CE    0x035E
94 #define IPR_SUBS_DEV_ID_57B1    0x0355
95 
96 #define IPR_SUBS_DEV_ID_574D    0x0356
97 #define IPR_SUBS_DEV_ID_57C8    0x035D
98 
99 #define IPR_SUBS_DEV_ID_57D5    0x03FB
100 #define IPR_SUBS_DEV_ID_57D6    0x03FC
101 #define IPR_SUBS_DEV_ID_57D7    0x03FF
102 #define IPR_SUBS_DEV_ID_57D8    0x03FE
103 #define IPR_SUBS_DEV_ID_57D9    0x046D
104 #define IPR_SUBS_DEV_ID_57DA    0x04CA
105 #define IPR_SUBS_DEV_ID_57EB    0x0474
106 #define IPR_SUBS_DEV_ID_57EC    0x0475
107 #define IPR_SUBS_DEV_ID_57ED    0x0499
108 #define IPR_SUBS_DEV_ID_57EE    0x049A
109 #define IPR_SUBS_DEV_ID_57EF    0x049B
110 #define IPR_SUBS_DEV_ID_57F0    0x049C
111 #define IPR_SUBS_DEV_ID_2CCA	0x04C7
112 #define IPR_SUBS_DEV_ID_2CD2	0x04C8
113 #define IPR_SUBS_DEV_ID_2CCD	0x04C9
114 #define IPR_NAME				"ipr"
115 
116 /*
117  * Return codes
118  */
119 #define IPR_RC_JOB_CONTINUE		1
120 #define IPR_RC_JOB_RETURN		2
121 
122 /*
123  * IOASCs
124  */
125 #define IPR_IOASC_NR_INIT_CMD_REQUIRED		0x02040200
126 #define IPR_IOASC_NR_IOA_RESET_REQUIRED		0x02048000
127 #define IPR_IOASC_SYNC_REQUIRED			0x023f0000
128 #define IPR_IOASC_MED_DO_NOT_REALLOC		0x03110C00
129 #define IPR_IOASC_HW_SEL_TIMEOUT			0x04050000
130 #define IPR_IOASC_HW_DEV_BUS_STATUS			0x04448500
131 #define	IPR_IOASC_IOASC_MASK			0xFFFFFF00
132 #define	IPR_IOASC_SCSI_STATUS_MASK		0x000000FF
133 #define IPR_IOASC_HW_CMD_FAILED			0x046E0000
134 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT	0x05240000
135 #define IPR_IOASC_IR_RESOURCE_HANDLE		0x05250000
136 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA		0x05258100
137 #define IPR_IOASA_IR_DUAL_IOA_DISABLED		0x052C8000
138 #define IPR_IOASC_BUS_WAS_RESET			0x06290000
139 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER		0x06298000
140 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST	0x0B5A0000
141 
142 #define IPR_FIRST_DRIVER_IOASC			0x10000000
143 #define IPR_IOASC_IOA_WAS_RESET			0x10000001
144 #define IPR_IOASC_PCI_ACCESS_ERROR			0x10000002
145 
146 /* Driver data flags */
147 #define IPR_USE_LONG_TRANSOP_TIMEOUT		0x00000001
148 #define IPR_USE_PCI_WARM_RESET			0x00000002
149 
150 #define IPR_DEFAULT_MAX_ERROR_DUMP			984
151 #define IPR_NUM_LOG_HCAMS				2
152 #define IPR_NUM_CFG_CHG_HCAMS				2
153 #define IPR_NUM_HCAMS	(IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
154 
155 #define IPR_MAX_SIS64_TARGETS_PER_BUS			1024
156 #define IPR_MAX_SIS64_LUNS_PER_TARGET			0xffffffff
157 
158 #define IPR_MAX_NUM_TARGETS_PER_BUS			256
159 #define IPR_MAX_NUM_LUNS_PER_TARGET			256
160 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET	8
161 #define IPR_VSET_BUS					0xff
162 #define IPR_IOA_BUS						0xff
163 #define IPR_IOA_TARGET					0xff
164 #define IPR_IOA_LUN						0xff
165 #define IPR_MAX_NUM_BUSES				16
166 #define IPR_MAX_BUS_TO_SCAN				IPR_MAX_NUM_BUSES
167 
168 #define IPR_NUM_RESET_RELOAD_RETRIES		3
169 
170 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
171 #define IPR_NUM_INTERNAL_CMD_BLKS	(IPR_NUM_HCAMS + \
172                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
173 
174 #define IPR_MAX_COMMANDS		100
175 #define IPR_NUM_CMD_BLKS		(IPR_NUM_BASE_CMD_BLKS + \
176 						IPR_NUM_INTERNAL_CMD_BLKS)
177 
178 #define IPR_MAX_PHYSICAL_DEVS				192
179 #define IPR_DEFAULT_SIS64_DEVS				1024
180 #define IPR_MAX_SIS64_DEVS				4096
181 
182 #define IPR_MAX_SGLIST					64
183 #define IPR_IOA_MAX_SECTORS				32767
184 #define IPR_VSET_MAX_SECTORS				512
185 #define IPR_MAX_CDB_LEN					16
186 #define IPR_MAX_HRRQ_RETRIES				3
187 
188 #define IPR_DEFAULT_BUS_WIDTH				16
189 #define IPR_80MBs_SCSI_RATE		((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
190 #define IPR_U160_SCSI_RATE	((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
191 #define IPR_U320_SCSI_RATE	((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
192 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
193 
194 #define IPR_IOA_RES_HANDLE				0xffffffff
195 #define IPR_INVALID_RES_HANDLE			0
196 #define IPR_IOA_RES_ADDR				0x00ffffff
197 
198 /*
199  * Adapter Commands
200  */
201 #define IPR_QUERY_RSRC_STATE				0xC2
202 #define IPR_RESET_DEVICE				0xC3
203 #define	IPR_RESET_TYPE_SELECT				0x80
204 #define	IPR_LUN_RESET					0x40
205 #define	IPR_TARGET_RESET					0x20
206 #define	IPR_BUS_RESET					0x10
207 #define	IPR_ATA_PHY_RESET					0x80
208 #define IPR_ID_HOST_RR_Q				0xC4
209 #define IPR_QUERY_IOA_CONFIG				0xC5
210 #define IPR_CANCEL_ALL_REQUESTS			0xCE
211 #define IPR_HOST_CONTROLLED_ASYNC			0xCF
212 #define	IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE	0x01
213 #define	IPR_HCAM_CDB_OP_CODE_LOG_DATA		0x02
214 #define IPR_SET_SUPPORTED_DEVICES			0xFB
215 #define IPR_SET_ALL_SUPPORTED_DEVICES			0x80
216 #define IPR_IOA_SHUTDOWN				0xF7
217 #define	IPR_WR_BUF_DOWNLOAD_AND_SAVE			0x05
218 
219 /*
220  * Timeouts
221  */
222 #define IPR_SHUTDOWN_TIMEOUT			(ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
223 #define IPR_VSET_RW_TIMEOUT			(ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
224 #define IPR_ABBREV_SHUTDOWN_TIMEOUT		(10 * HZ)
225 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO	(2 * 60 * HZ)
226 #define IPR_DEVICE_RESET_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
227 #define IPR_CANCEL_ALL_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
228 #define IPR_ABORT_TASK_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
229 #define IPR_INTERNAL_TIMEOUT			(ipr_fastfail ? 10 * HZ : 30 * HZ)
230 #define IPR_WRITE_BUFFER_TIMEOUT		(30 * 60 * HZ)
231 #define IPR_SET_SUP_DEVICE_TIMEOUT		(2 * 60 * HZ)
232 #define IPR_REQUEST_SENSE_TIMEOUT		(10 * HZ)
233 #define IPR_OPERATIONAL_TIMEOUT		(5 * 60)
234 #define IPR_LONG_OPERATIONAL_TIMEOUT	(12 * 60)
235 #define IPR_WAIT_FOR_RESET_TIMEOUT		(2 * HZ)
236 #define IPR_CHECK_FOR_RESET_TIMEOUT		(HZ / 10)
237 #define IPR_WAIT_FOR_BIST_TIMEOUT		(2 * HZ)
238 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT	(120 * HZ)
239 #define IPR_PCI_RESET_TIMEOUT			(HZ / 2)
240 #define IPR_SIS32_DUMP_TIMEOUT			(15 * HZ)
241 #define IPR_SIS64_DUMP_TIMEOUT			(40 * HZ)
242 #define IPR_DUMP_DELAY_SECONDS			4
243 #define IPR_DUMP_DELAY_TIMEOUT			(IPR_DUMP_DELAY_SECONDS * HZ)
244 
245 /*
246  * SCSI Literals
247  */
248 #define IPR_VENDOR_ID_LEN			8
249 #define IPR_PROD_ID_LEN				16
250 #define IPR_SERIAL_NUM_LEN			8
251 
252 /*
253  * Hardware literals
254  */
255 #define IPR_FMT2_MBX_ADDR_MASK				0x0fffffff
256 #define IPR_FMT2_MBX_BAR_SEL_MASK			0xf0000000
257 #define IPR_FMT2_MKR_BAR_SEL_SHIFT			28
258 #define IPR_GET_FMT2_BAR_SEL(mbx) \
259 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
260 #define IPR_SDT_FMT2_BAR0_SEL				0x0
261 #define IPR_SDT_FMT2_BAR1_SEL				0x1
262 #define IPR_SDT_FMT2_BAR2_SEL				0x2
263 #define IPR_SDT_FMT2_BAR3_SEL				0x3
264 #define IPR_SDT_FMT2_BAR4_SEL				0x4
265 #define IPR_SDT_FMT2_BAR5_SEL				0x5
266 #define IPR_SDT_FMT2_EXP_ROM_SEL			0x8
267 #define IPR_FMT2_SDT_READY_TO_USE			0xC4D4E3F2
268 #define IPR_FMT3_SDT_READY_TO_USE			0xC4D4E3F3
269 #define IPR_DOORBELL					0x82800000
270 #define IPR_RUNTIME_RESET				0x40000000
271 
272 #define IPR_IPL_INIT_MIN_STAGE_TIME			5
273 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 30
274 #define IPR_IPL_INIT_STAGE_UNKNOWN			0x0
275 #define IPR_IPL_INIT_STAGE_TRANSOP			0xB0000000
276 #define IPR_IPL_INIT_STAGE_MASK				0xff000000
277 #define IPR_IPL_INIT_STAGE_TIME_MASK			0x0000ffff
278 #define IPR_PCII_IPL_STAGE_CHANGE			(0x80000000 >> 0)
279 
280 #define IPR_PCII_IOA_TRANS_TO_OPER			(0x80000000 >> 0)
281 #define IPR_PCII_IOARCB_XFER_FAILED			(0x80000000 >> 3)
282 #define IPR_PCII_IOA_UNIT_CHECKED			(0x80000000 >> 4)
283 #define IPR_PCII_NO_HOST_RRQ				(0x80000000 >> 5)
284 #define IPR_PCII_CRITICAL_OPERATION			(0x80000000 >> 6)
285 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE		(0x80000000 >> 7)
286 #define IPR_PCII_IOARRIN_LOST				(0x80000000 >> 27)
287 #define IPR_PCII_MMIO_ERROR				(0x80000000 >> 28)
288 #define IPR_PCII_PROC_ERR_STATE			(0x80000000 >> 29)
289 #define IPR_PCII_HRRQ_UPDATED				(0x80000000 >> 30)
290 #define IPR_PCII_CORE_ISSUED_RST_REQ		(0x80000000 >> 31)
291 
292 #define IPR_PCII_ERROR_INTERRUPTS \
293 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
294 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
295 
296 #define IPR_PCII_OPER_INTERRUPTS \
297 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
298 
299 #define IPR_UPROCI_RESET_ALERT			(0x80000000 >> 7)
300 #define IPR_UPROCI_IO_DEBUG_ALERT			(0x80000000 >> 9)
301 #define IPR_UPROCI_SIS64_START_BIST			(0x80000000 >> 23)
302 
303 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC		200000	/* 200 ms */
304 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC		200000	/* 200 ms */
305 
306 /*
307  * Dump literals
308  */
309 #define IPR_FMT2_MAX_IOA_DUMP_SIZE			(4 * 1024 * 1024)
310 #define IPR_FMT3_MAX_IOA_DUMP_SIZE			(80 * 1024 * 1024)
311 #define IPR_FMT2_NUM_SDT_ENTRIES			511
312 #define IPR_FMT3_NUM_SDT_ENTRIES			0xFFF
313 #define IPR_FMT2_MAX_NUM_DUMP_PAGES	((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
314 #define IPR_FMT3_MAX_NUM_DUMP_PAGES	((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
315 
316 /*
317  * Misc literals
318  */
319 #define IPR_NUM_IOADL_ENTRIES			IPR_MAX_SGLIST
320 #define IPR_MAX_MSIX_VECTORS		0x10
321 #define IPR_MAX_HRRQ_NUM		0x10
322 #define IPR_INIT_HRRQ			0x0
323 
324 /*
325  * Adapter interface types
326  */
327 
328 struct ipr_res_addr {
329 	u8 reserved;
330 	u8 bus;
331 	u8 target;
332 	u8 lun;
333 #define IPR_GET_PHYS_LOC(res_addr) \
334 	(((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
335 }__attribute__((packed, aligned (4)));
336 
337 struct ipr_std_inq_vpids {
338 	u8 vendor_id[IPR_VENDOR_ID_LEN];
339 	u8 product_id[IPR_PROD_ID_LEN];
340 }__attribute__((packed));
341 
342 struct ipr_vpd {
343 	struct ipr_std_inq_vpids vpids;
344 	u8 sn[IPR_SERIAL_NUM_LEN];
345 }__attribute__((packed));
346 
347 struct ipr_ext_vpd {
348 	struct ipr_vpd vpd;
349 	__be32 wwid[2];
350 }__attribute__((packed));
351 
352 struct ipr_ext_vpd64 {
353 	struct ipr_vpd vpd;
354 	__be32 wwid[4];
355 }__attribute__((packed));
356 
357 struct ipr_std_inq_data {
358 	u8 peri_qual_dev_type;
359 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
360 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
361 
362 	u8 removeable_medium_rsvd;
363 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
364 
365 #define IPR_IS_DASD_DEVICE(std_inq) \
366 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
367 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
368 
369 #define IPR_IS_SES_DEVICE(std_inq) \
370 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
371 
372 	u8 version;
373 	u8 aen_naca_fmt;
374 	u8 additional_len;
375 	u8 sccs_rsvd;
376 	u8 bq_enc_multi;
377 	u8 sync_cmdq_flags;
378 
379 	struct ipr_std_inq_vpids vpids;
380 
381 	u8 ros_rsvd_ram_rsvd[4];
382 
383 	u8 serial_num[IPR_SERIAL_NUM_LEN];
384 }__attribute__ ((packed));
385 
386 #define IPR_RES_TYPE_AF_DASD		0x00
387 #define IPR_RES_TYPE_GENERIC_SCSI	0x01
388 #define IPR_RES_TYPE_VOLUME_SET		0x02
389 #define IPR_RES_TYPE_REMOTE_AF_DASD	0x03
390 #define IPR_RES_TYPE_GENERIC_ATA	0x04
391 #define IPR_RES_TYPE_ARRAY		0x05
392 #define IPR_RES_TYPE_IOAFP		0xff
393 
394 struct ipr_config_table_entry {
395 	u8 proto;
396 #define IPR_PROTO_SATA			0x02
397 #define IPR_PROTO_SATA_ATAPI		0x03
398 #define IPR_PROTO_SAS_STP		0x06
399 #define IPR_PROTO_SAS_STP_ATAPI		0x07
400 	u8 array_id;
401 	u8 flags;
402 #define IPR_IS_IOA_RESOURCE		0x80
403 	u8 rsvd_subtype;
404 
405 #define IPR_QUEUEING_MODEL(res)	((((res)->flags) & 0x70) >> 4)
406 #define IPR_QUEUE_FROZEN_MODEL		0
407 #define IPR_QUEUE_NACA_MODEL		1
408 
409 	struct ipr_res_addr res_addr;
410 	__be32 res_handle;
411 	__be32 lun_wwn[2];
412 	struct ipr_std_inq_data std_inq_data;
413 }__attribute__ ((packed, aligned (4)));
414 
415 struct ipr_config_table_entry64 {
416 	u8 res_type;
417 	u8 proto;
418 	u8 vset_num;
419 	u8 array_id;
420 	__be16 flags;
421 	__be16 res_flags;
422 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
423 	__be32 res_handle;
424 	u8 dev_id_type;
425 	u8 reserved[3];
426 	__be64 dev_id;
427 	__be64 lun;
428 	__be64 lun_wwn[2];
429 #define IPR_MAX_RES_PATH_LENGTH		48
430 	__be64 res_path;
431 	struct ipr_std_inq_data std_inq_data;
432 	u8 reserved2[4];
433 	__be64 reserved3[2];
434 	u8 reserved4[8];
435 }__attribute__ ((packed, aligned (8)));
436 
437 struct ipr_config_table_hdr {
438 	u8 num_entries;
439 	u8 flags;
440 #define IPR_UCODE_DOWNLOAD_REQ	0x10
441 	__be16 reserved;
442 }__attribute__((packed, aligned (4)));
443 
444 struct ipr_config_table_hdr64 {
445 	__be16 num_entries;
446 	__be16 reserved;
447 	u8 flags;
448 	u8 reserved2[11];
449 }__attribute__((packed, aligned (4)));
450 
451 struct ipr_config_table {
452 	struct ipr_config_table_hdr hdr;
453 	struct ipr_config_table_entry dev[0];
454 }__attribute__((packed, aligned (4)));
455 
456 struct ipr_config_table64 {
457 	struct ipr_config_table_hdr64 hdr64;
458 	struct ipr_config_table_entry64 dev[0];
459 }__attribute__((packed, aligned (8)));
460 
461 struct ipr_config_table_entry_wrapper {
462 	union {
463 		struct ipr_config_table_entry *cfgte;
464 		struct ipr_config_table_entry64 *cfgte64;
465 	} u;
466 };
467 
468 struct ipr_hostrcb_cfg_ch_not {
469 	union {
470 		struct ipr_config_table_entry cfgte;
471 		struct ipr_config_table_entry64 cfgte64;
472 	} u;
473 	u8 reserved[936];
474 }__attribute__((packed, aligned (4)));
475 
476 struct ipr_supported_device {
477 	__be16 data_length;
478 	u8 reserved;
479 	u8 num_records;
480 	struct ipr_std_inq_vpids vpids;
481 	u8 reserved2[16];
482 }__attribute__((packed, aligned (4)));
483 
484 struct ipr_hrr_queue {
485 	struct ipr_ioa_cfg *ioa_cfg;
486 	__be32 *host_rrq;
487 	dma_addr_t host_rrq_dma;
488 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK	0xfffffffc
489 #define IPR_HRRQ_RESP_BIT_SET		0x00000002
490 #define IPR_HRRQ_TOGGLE_BIT		0x00000001
491 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT	2
492 #define IPR_ID_HRRQ_SELE_ENABLE		0x02
493 	volatile __be32 *hrrq_start;
494 	volatile __be32 *hrrq_end;
495 	volatile __be32 *hrrq_curr;
496 
497 	struct list_head hrrq_free_q;
498 	struct list_head hrrq_pending_q;
499 	spinlock_t _lock;
500 	spinlock_t *lock;
501 
502 	volatile u32 toggle_bit;
503 	u32 size;
504 	u32 min_cmd_id;
505 	u32 max_cmd_id;
506 	u8 allow_interrupts:1;
507 	u8 ioa_is_dead:1;
508 	u8 allow_cmds:1;
509 	u8 removing_ioa:1;
510 
511 	struct blk_iopoll iopoll;
512 };
513 
514 /* Command packet structure */
515 struct ipr_cmd_pkt {
516 	u8 reserved;		/* Reserved by IOA */
517 	u8 hrrq_id;
518 	u8 request_type;
519 #define IPR_RQTYPE_SCSICDB		0x00
520 #define IPR_RQTYPE_IOACMD		0x01
521 #define IPR_RQTYPE_HCAM			0x02
522 #define IPR_RQTYPE_ATA_PASSTHRU	0x04
523 
524 	u8 reserved2;
525 
526 	u8 flags_hi;
527 #define IPR_FLAGS_HI_WRITE_NOT_READ		0x80
528 #define IPR_FLAGS_HI_NO_ULEN_CHK		0x20
529 #define IPR_FLAGS_HI_SYNC_OVERRIDE		0x10
530 #define IPR_FLAGS_HI_SYNC_COMPLETE		0x08
531 #define IPR_FLAGS_HI_NO_LINK_DESC		0x04
532 
533 	u8 flags_lo;
534 #define IPR_FLAGS_LO_ALIGNED_BFR		0x20
535 #define IPR_FLAGS_LO_DELAY_AFTER_RST		0x10
536 #define IPR_FLAGS_LO_UNTAGGED_TASK		0x00
537 #define IPR_FLAGS_LO_SIMPLE_TASK		0x02
538 #define IPR_FLAGS_LO_ORDERED_TASK		0x04
539 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK		0x06
540 #define IPR_FLAGS_LO_ACA_TASK			0x08
541 
542 	u8 cdb[16];
543 	__be16 timeout;
544 }__attribute__ ((packed, aligned(4)));
545 
546 struct ipr_ioarcb_ata_regs {	/* 22 bytes */
547 	u8 flags;
548 #define IPR_ATA_FLAG_PACKET_CMD			0x80
549 #define IPR_ATA_FLAG_XFER_TYPE_DMA			0x40
550 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION	0x20
551 	u8 reserved[3];
552 
553 	__be16 data;
554 	u8 feature;
555 	u8 nsect;
556 	u8 lbal;
557 	u8 lbam;
558 	u8 lbah;
559 	u8 device;
560 	u8 command;
561 	u8 reserved2[3];
562 	u8 hob_feature;
563 	u8 hob_nsect;
564 	u8 hob_lbal;
565 	u8 hob_lbam;
566 	u8 hob_lbah;
567 	u8 ctl;
568 }__attribute__ ((packed, aligned(2)));
569 
570 struct ipr_ioadl_desc {
571 	__be32 flags_and_data_len;
572 #define IPR_IOADL_FLAGS_MASK		0xff000000
573 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
574 #define IPR_IOADL_DATA_LEN_MASK		0x00ffffff
575 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
576 #define IPR_IOADL_FLAGS_READ		0x48000000
577 #define IPR_IOADL_FLAGS_READ_LAST	0x49000000
578 #define IPR_IOADL_FLAGS_WRITE		0x68000000
579 #define IPR_IOADL_FLAGS_WRITE_LAST	0x69000000
580 #define IPR_IOADL_FLAGS_LAST		0x01000000
581 
582 	__be32 address;
583 }__attribute__((packed, aligned (8)));
584 
585 struct ipr_ioadl64_desc {
586 	__be32 flags;
587 	__be32 data_len;
588 	__be64 address;
589 }__attribute__((packed, aligned (16)));
590 
591 struct ipr_ata64_ioadl {
592 	struct ipr_ioarcb_ata_regs regs;
593 	u16 reserved[5];
594 	struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
595 }__attribute__((packed, aligned (16)));
596 
597 struct ipr_ioarcb_add_data {
598 	union {
599 		struct ipr_ioarcb_ata_regs regs;
600 		struct ipr_ioadl_desc ioadl[5];
601 		__be32 add_cmd_parms[10];
602 	} u;
603 }__attribute__ ((packed, aligned (4)));
604 
605 struct ipr_ioarcb_sis64_add_addr_ecb {
606 	__be64 ioasa_host_pci_addr;
607 	__be64 data_ioadl_addr;
608 	__be64 reserved;
609 	__be32 ext_control_buf[4];
610 }__attribute__((packed, aligned (8)));
611 
612 /* IOA Request Control Block    128 bytes  */
613 struct ipr_ioarcb {
614 	union {
615 		__be32 ioarcb_host_pci_addr;
616 		__be64 ioarcb_host_pci_addr64;
617 	} a;
618 	__be32 res_handle;
619 	__be32 host_response_handle;
620 	__be32 reserved1;
621 	__be32 reserved2;
622 	__be32 reserved3;
623 
624 	__be32 data_transfer_length;
625 	__be32 read_data_transfer_length;
626 	__be32 write_ioadl_addr;
627 	__be32 ioadl_len;
628 	__be32 read_ioadl_addr;
629 	__be32 read_ioadl_len;
630 
631 	__be32 ioasa_host_pci_addr;
632 	__be16 ioasa_len;
633 	__be16 reserved4;
634 
635 	struct ipr_cmd_pkt cmd_pkt;
636 
637 	__be16 add_cmd_parms_offset;
638 	__be16 add_cmd_parms_len;
639 
640 	union {
641 		struct ipr_ioarcb_add_data add_data;
642 		struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
643 	} u;
644 
645 }__attribute__((packed, aligned (4)));
646 
647 struct ipr_ioasa_vset {
648 	__be32 failing_lba_hi;
649 	__be32 failing_lba_lo;
650 	__be32 reserved;
651 }__attribute__((packed, aligned (4)));
652 
653 struct ipr_ioasa_af_dasd {
654 	__be32 failing_lba;
655 	__be32 reserved[2];
656 }__attribute__((packed, aligned (4)));
657 
658 struct ipr_ioasa_gpdd {
659 	u8 end_state;
660 	u8 bus_phase;
661 	__be16 reserved;
662 	__be32 ioa_data[2];
663 }__attribute__((packed, aligned (4)));
664 
665 struct ipr_ioasa_gata {
666 	u8 error;
667 	u8 nsect;		/* Interrupt reason */
668 	u8 lbal;
669 	u8 lbam;
670 	u8 lbah;
671 	u8 device;
672 	u8 status;
673 	u8 alt_status;	/* ATA CTL */
674 	u8 hob_nsect;
675 	u8 hob_lbal;
676 	u8 hob_lbam;
677 	u8 hob_lbah;
678 }__attribute__((packed, aligned (4)));
679 
680 struct ipr_auto_sense {
681 	__be16 auto_sense_len;
682 	__be16 ioa_data_len;
683 	__be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
684 };
685 
686 struct ipr_ioasa_hdr {
687 	__be32 ioasc;
688 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
689 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
690 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
691 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
692 
693 	__be16 ret_stat_len;	/* Length of the returned IOASA */
694 
695 	__be16 avail_stat_len;	/* Total Length of status available. */
696 
697 	__be32 residual_data_len;	/* number of bytes in the host data */
698 	/* buffers that were not used by the IOARCB command. */
699 
700 	__be32 ilid;
701 #define IPR_NO_ILID			0
702 #define IPR_DRIVER_ILID		0xffffffff
703 
704 	__be32 fd_ioasc;
705 
706 	__be32 fd_phys_locator;
707 
708 	__be32 fd_res_handle;
709 
710 	__be32 ioasc_specific;	/* status code specific field */
711 #define IPR_ADDITIONAL_STATUS_FMT		0x80000000
712 #define IPR_AUTOSENSE_VALID			0x40000000
713 #define IPR_ATA_DEVICE_WAS_RESET		0x20000000
714 #define IPR_IOASC_SPECIFIC_MASK		0x00ffffff
715 #define IPR_FIELD_POINTER_VALID		(0x80000000 >> 8)
716 #define IPR_FIELD_POINTER_MASK		0x0000ffff
717 
718 }__attribute__((packed, aligned (4)));
719 
720 struct ipr_ioasa {
721 	struct ipr_ioasa_hdr hdr;
722 
723 	union {
724 		struct ipr_ioasa_vset vset;
725 		struct ipr_ioasa_af_dasd dasd;
726 		struct ipr_ioasa_gpdd gpdd;
727 		struct ipr_ioasa_gata gata;
728 	} u;
729 
730 	struct ipr_auto_sense auto_sense;
731 }__attribute__((packed, aligned (4)));
732 
733 struct ipr_ioasa64 {
734 	struct ipr_ioasa_hdr hdr;
735 	u8 fd_res_path[8];
736 
737 	union {
738 		struct ipr_ioasa_vset vset;
739 		struct ipr_ioasa_af_dasd dasd;
740 		struct ipr_ioasa_gpdd gpdd;
741 		struct ipr_ioasa_gata gata;
742 	} u;
743 
744 	struct ipr_auto_sense auto_sense;
745 }__attribute__((packed, aligned (4)));
746 
747 struct ipr_mode_parm_hdr {
748 	u8 length;
749 	u8 medium_type;
750 	u8 device_spec_parms;
751 	u8 block_desc_len;
752 }__attribute__((packed));
753 
754 struct ipr_mode_pages {
755 	struct ipr_mode_parm_hdr hdr;
756 	u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
757 }__attribute__((packed));
758 
759 struct ipr_mode_page_hdr {
760 	u8 ps_page_code;
761 #define IPR_MODE_PAGE_PS	0x80
762 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
763 	u8 page_length;
764 }__attribute__ ((packed));
765 
766 struct ipr_dev_bus_entry {
767 	struct ipr_res_addr res_addr;
768 	u8 flags;
769 #define IPR_SCSI_ATTR_ENABLE_QAS			0x80
770 #define IPR_SCSI_ATTR_DISABLE_QAS			0x40
771 #define IPR_SCSI_ATTR_QAS_MASK				0xC0
772 #define IPR_SCSI_ATTR_ENABLE_TM				0x20
773 #define IPR_SCSI_ATTR_NO_TERM_PWR			0x10
774 #define IPR_SCSI_ATTR_TM_SUPPORTED			0x08
775 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED	0x04
776 
777 	u8 scsi_id;
778 	u8 bus_width;
779 	u8 extended_reset_delay;
780 #define IPR_EXTENDED_RESET_DELAY	7
781 
782 	__be32 max_xfer_rate;
783 
784 	u8 spinup_delay;
785 	u8 reserved3;
786 	__be16 reserved4;
787 }__attribute__((packed, aligned (4)));
788 
789 struct ipr_mode_page28 {
790 	struct ipr_mode_page_hdr hdr;
791 	u8 num_entries;
792 	u8 entry_length;
793 	struct ipr_dev_bus_entry bus[0];
794 }__attribute__((packed));
795 
796 struct ipr_mode_page24 {
797 	struct ipr_mode_page_hdr hdr;
798 	u8 flags;
799 #define IPR_ENABLE_DUAL_IOA_AF 0x80
800 }__attribute__((packed));
801 
802 struct ipr_ioa_vpd {
803 	struct ipr_std_inq_data std_inq_data;
804 	u8 ascii_part_num[12];
805 	u8 reserved[40];
806 	u8 ascii_plant_code[4];
807 }__attribute__((packed));
808 
809 struct ipr_inquiry_page3 {
810 	u8 peri_qual_dev_type;
811 	u8 page_code;
812 	u8 reserved1;
813 	u8 page_length;
814 	u8 ascii_len;
815 	u8 reserved2[3];
816 	u8 load_id[4];
817 	u8 major_release;
818 	u8 card_type;
819 	u8 minor_release[2];
820 	u8 ptf_number[4];
821 	u8 patch_number[4];
822 }__attribute__((packed));
823 
824 struct ipr_inquiry_cap {
825 	u8 peri_qual_dev_type;
826 	u8 page_code;
827 	u8 reserved1;
828 	u8 page_length;
829 	u8 ascii_len;
830 	u8 reserved2;
831 	u8 sis_version[2];
832 	u8 cap;
833 #define IPR_CAP_DUAL_IOA_RAID		0x80
834 	u8 reserved3[15];
835 }__attribute__((packed));
836 
837 #define IPR_INQUIRY_PAGE0_ENTRIES 20
838 struct ipr_inquiry_page0 {
839 	u8 peri_qual_dev_type;
840 	u8 page_code;
841 	u8 reserved1;
842 	u8 len;
843 	u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
844 }__attribute__((packed));
845 
846 struct ipr_hostrcb_device_data_entry {
847 	struct ipr_vpd vpd;
848 	struct ipr_res_addr dev_res_addr;
849 	struct ipr_vpd new_vpd;
850 	struct ipr_vpd ioa_last_with_dev_vpd;
851 	struct ipr_vpd cfc_last_with_dev_vpd;
852 	__be32 ioa_data[5];
853 }__attribute__((packed, aligned (4)));
854 
855 struct ipr_hostrcb_device_data_entry_enhanced {
856 	struct ipr_ext_vpd vpd;
857 	u8 ccin[4];
858 	struct ipr_res_addr dev_res_addr;
859 	struct ipr_ext_vpd new_vpd;
860 	u8 new_ccin[4];
861 	struct ipr_ext_vpd ioa_last_with_dev_vpd;
862 	struct ipr_ext_vpd cfc_last_with_dev_vpd;
863 }__attribute__((packed, aligned (4)));
864 
865 struct ipr_hostrcb64_device_data_entry_enhanced {
866 	struct ipr_ext_vpd vpd;
867 	u8 ccin[4];
868 	u8 res_path[8];
869 	struct ipr_ext_vpd new_vpd;
870 	u8 new_ccin[4];
871 	struct ipr_ext_vpd ioa_last_with_dev_vpd;
872 	struct ipr_ext_vpd cfc_last_with_dev_vpd;
873 }__attribute__((packed, aligned (4)));
874 
875 struct ipr_hostrcb_array_data_entry {
876 	struct ipr_vpd vpd;
877 	struct ipr_res_addr expected_dev_res_addr;
878 	struct ipr_res_addr dev_res_addr;
879 }__attribute__((packed, aligned (4)));
880 
881 struct ipr_hostrcb64_array_data_entry {
882 	struct ipr_ext_vpd vpd;
883 	u8 ccin[4];
884 	u8 expected_res_path[8];
885 	u8 res_path[8];
886 }__attribute__((packed, aligned (4)));
887 
888 struct ipr_hostrcb_array_data_entry_enhanced {
889 	struct ipr_ext_vpd vpd;
890 	u8 ccin[4];
891 	struct ipr_res_addr expected_dev_res_addr;
892 	struct ipr_res_addr dev_res_addr;
893 }__attribute__((packed, aligned (4)));
894 
895 struct ipr_hostrcb_type_ff_error {
896 	__be32 ioa_data[758];
897 }__attribute__((packed, aligned (4)));
898 
899 struct ipr_hostrcb_type_01_error {
900 	__be32 seek_counter;
901 	__be32 read_counter;
902 	u8 sense_data[32];
903 	__be32 ioa_data[236];
904 }__attribute__((packed, aligned (4)));
905 
906 struct ipr_hostrcb_type_21_error {
907 	__be32 wwn[4];
908 	u8 res_path[8];
909 	u8 primary_problem_desc[32];
910 	u8 second_problem_desc[32];
911 	__be32 sense_data[8];
912 	__be32 cdb[4];
913 	__be32 residual_trans_length;
914 	__be32 length_of_error;
915 	__be32 ioa_data[236];
916 }__attribute__((packed, aligned (4)));
917 
918 struct ipr_hostrcb_type_02_error {
919 	struct ipr_vpd ioa_vpd;
920 	struct ipr_vpd cfc_vpd;
921 	struct ipr_vpd ioa_last_attached_to_cfc_vpd;
922 	struct ipr_vpd cfc_last_attached_to_ioa_vpd;
923 	__be32 ioa_data[3];
924 }__attribute__((packed, aligned (4)));
925 
926 struct ipr_hostrcb_type_12_error {
927 	struct ipr_ext_vpd ioa_vpd;
928 	struct ipr_ext_vpd cfc_vpd;
929 	struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
930 	struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
931 	__be32 ioa_data[3];
932 }__attribute__((packed, aligned (4)));
933 
934 struct ipr_hostrcb_type_03_error {
935 	struct ipr_vpd ioa_vpd;
936 	struct ipr_vpd cfc_vpd;
937 	__be32 errors_detected;
938 	__be32 errors_logged;
939 	u8 ioa_data[12];
940 	struct ipr_hostrcb_device_data_entry dev[3];
941 }__attribute__((packed, aligned (4)));
942 
943 struct ipr_hostrcb_type_13_error {
944 	struct ipr_ext_vpd ioa_vpd;
945 	struct ipr_ext_vpd cfc_vpd;
946 	__be32 errors_detected;
947 	__be32 errors_logged;
948 	struct ipr_hostrcb_device_data_entry_enhanced dev[3];
949 }__attribute__((packed, aligned (4)));
950 
951 struct ipr_hostrcb_type_23_error {
952 	struct ipr_ext_vpd ioa_vpd;
953 	struct ipr_ext_vpd cfc_vpd;
954 	__be32 errors_detected;
955 	__be32 errors_logged;
956 	struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
957 }__attribute__((packed, aligned (4)));
958 
959 struct ipr_hostrcb_type_04_error {
960 	struct ipr_vpd ioa_vpd;
961 	struct ipr_vpd cfc_vpd;
962 	u8 ioa_data[12];
963 	struct ipr_hostrcb_array_data_entry array_member[10];
964 	__be32 exposed_mode_adn;
965 	__be32 array_id;
966 	struct ipr_vpd incomp_dev_vpd;
967 	__be32 ioa_data2;
968 	struct ipr_hostrcb_array_data_entry array_member2[8];
969 	struct ipr_res_addr last_func_vset_res_addr;
970 	u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
971 	u8 protection_level[8];
972 }__attribute__((packed, aligned (4)));
973 
974 struct ipr_hostrcb_type_14_error {
975 	struct ipr_ext_vpd ioa_vpd;
976 	struct ipr_ext_vpd cfc_vpd;
977 	__be32 exposed_mode_adn;
978 	__be32 array_id;
979 	struct ipr_res_addr last_func_vset_res_addr;
980 	u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
981 	u8 protection_level[8];
982 	__be32 num_entries;
983 	struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
984 }__attribute__((packed, aligned (4)));
985 
986 struct ipr_hostrcb_type_24_error {
987 	struct ipr_ext_vpd ioa_vpd;
988 	struct ipr_ext_vpd cfc_vpd;
989 	u8 reserved[2];
990 	u8 exposed_mode_adn;
991 #define IPR_INVALID_ARRAY_DEV_NUM		0xff
992 	u8 array_id;
993 	u8 last_res_path[8];
994 	u8 protection_level[8];
995 	struct ipr_ext_vpd64 array_vpd;
996 	u8 description[16];
997 	u8 reserved2[3];
998 	u8 num_entries;
999 	struct ipr_hostrcb64_array_data_entry array_member[32];
1000 }__attribute__((packed, aligned (4)));
1001 
1002 struct ipr_hostrcb_type_07_error {
1003 	u8 failure_reason[64];
1004 	struct ipr_vpd vpd;
1005 	u32 data[222];
1006 }__attribute__((packed, aligned (4)));
1007 
1008 struct ipr_hostrcb_type_17_error {
1009 	u8 failure_reason[64];
1010 	struct ipr_ext_vpd vpd;
1011 	u32 data[476];
1012 }__attribute__((packed, aligned (4)));
1013 
1014 struct ipr_hostrcb_config_element {
1015 	u8 type_status;
1016 #define IPR_PATH_CFG_TYPE_MASK	0xF0
1017 #define IPR_PATH_CFG_NOT_EXIST	0x00
1018 #define IPR_PATH_CFG_IOA_PORT		0x10
1019 #define IPR_PATH_CFG_EXP_PORT		0x20
1020 #define IPR_PATH_CFG_DEVICE_PORT	0x30
1021 #define IPR_PATH_CFG_DEVICE_LUN	0x40
1022 
1023 #define IPR_PATH_CFG_STATUS_MASK	0x0F
1024 #define IPR_PATH_CFG_NO_PROB		0x00
1025 #define IPR_PATH_CFG_DEGRADED		0x01
1026 #define IPR_PATH_CFG_FAILED		0x02
1027 #define IPR_PATH_CFG_SUSPECT		0x03
1028 #define IPR_PATH_NOT_DETECTED		0x04
1029 #define IPR_PATH_INCORRECT_CONN	0x05
1030 
1031 	u8 cascaded_expander;
1032 	u8 phy;
1033 	u8 link_rate;
1034 #define IPR_PHY_LINK_RATE_MASK	0x0F
1035 
1036 	__be32 wwid[2];
1037 }__attribute__((packed, aligned (4)));
1038 
1039 struct ipr_hostrcb64_config_element {
1040 	__be16 length;
1041 	u8 descriptor_id;
1042 #define IPR_DESCRIPTOR_MASK		0xC0
1043 #define IPR_DESCRIPTOR_SIS64		0x00
1044 
1045 	u8 reserved;
1046 	u8 type_status;
1047 
1048 	u8 reserved2[2];
1049 	u8 link_rate;
1050 
1051 	u8 res_path[8];
1052 	__be32 wwid[2];
1053 }__attribute__((packed, aligned (8)));
1054 
1055 struct ipr_hostrcb_fabric_desc {
1056 	__be16 length;
1057 	u8 ioa_port;
1058 	u8 cascaded_expander;
1059 	u8 phy;
1060 	u8 path_state;
1061 #define IPR_PATH_ACTIVE_MASK		0xC0
1062 #define IPR_PATH_NO_INFO		0x00
1063 #define IPR_PATH_ACTIVE			0x40
1064 #define IPR_PATH_NOT_ACTIVE		0x80
1065 
1066 #define IPR_PATH_STATE_MASK		0x0F
1067 #define IPR_PATH_STATE_NO_INFO	0x00
1068 #define IPR_PATH_HEALTHY		0x01
1069 #define IPR_PATH_DEGRADED		0x02
1070 #define IPR_PATH_FAILED			0x03
1071 
1072 	__be16 num_entries;
1073 	struct ipr_hostrcb_config_element elem[1];
1074 }__attribute__((packed, aligned (4)));
1075 
1076 struct ipr_hostrcb64_fabric_desc {
1077 	__be16 length;
1078 	u8 descriptor_id;
1079 
1080 	u8 reserved[2];
1081 	u8 path_state;
1082 
1083 	u8 reserved2[2];
1084 	u8 res_path[8];
1085 	u8 reserved3[6];
1086 	__be16 num_entries;
1087 	struct ipr_hostrcb64_config_element elem[1];
1088 }__attribute__((packed, aligned (8)));
1089 
1090 #define for_each_hrrq(hrrq, ioa_cfg) \
1091 		for (hrrq = (ioa_cfg)->hrrq; \
1092 			hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1093 
1094 #define for_each_fabric_cfg(fabric, cfg) \
1095 		for (cfg = (fabric)->elem; \
1096 			cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1097 			cfg++)
1098 
1099 struct ipr_hostrcb_type_20_error {
1100 	u8 failure_reason[64];
1101 	u8 reserved[3];
1102 	u8 num_entries;
1103 	struct ipr_hostrcb_fabric_desc desc[1];
1104 }__attribute__((packed, aligned (4)));
1105 
1106 struct ipr_hostrcb_type_30_error {
1107 	u8 failure_reason[64];
1108 	u8 reserved[3];
1109 	u8 num_entries;
1110 	struct ipr_hostrcb64_fabric_desc desc[1];
1111 }__attribute__((packed, aligned (4)));
1112 
1113 struct ipr_hostrcb_error {
1114 	__be32 fd_ioasc;
1115 	struct ipr_res_addr fd_res_addr;
1116 	__be32 fd_res_handle;
1117 	__be32 prc;
1118 	union {
1119 		struct ipr_hostrcb_type_ff_error type_ff_error;
1120 		struct ipr_hostrcb_type_01_error type_01_error;
1121 		struct ipr_hostrcb_type_02_error type_02_error;
1122 		struct ipr_hostrcb_type_03_error type_03_error;
1123 		struct ipr_hostrcb_type_04_error type_04_error;
1124 		struct ipr_hostrcb_type_07_error type_07_error;
1125 		struct ipr_hostrcb_type_12_error type_12_error;
1126 		struct ipr_hostrcb_type_13_error type_13_error;
1127 		struct ipr_hostrcb_type_14_error type_14_error;
1128 		struct ipr_hostrcb_type_17_error type_17_error;
1129 		struct ipr_hostrcb_type_20_error type_20_error;
1130 	} u;
1131 }__attribute__((packed, aligned (4)));
1132 
1133 struct ipr_hostrcb64_error {
1134 	__be32 fd_ioasc;
1135 	__be32 ioa_fw_level;
1136 	__be32 fd_res_handle;
1137 	__be32 prc;
1138 	__be64 fd_dev_id;
1139 	__be64 fd_lun;
1140 	u8 fd_res_path[8];
1141 	__be64 time_stamp;
1142 	u8 reserved[16];
1143 	union {
1144 		struct ipr_hostrcb_type_ff_error type_ff_error;
1145 		struct ipr_hostrcb_type_12_error type_12_error;
1146 		struct ipr_hostrcb_type_17_error type_17_error;
1147 		struct ipr_hostrcb_type_21_error type_21_error;
1148 		struct ipr_hostrcb_type_23_error type_23_error;
1149 		struct ipr_hostrcb_type_24_error type_24_error;
1150 		struct ipr_hostrcb_type_30_error type_30_error;
1151 	} u;
1152 }__attribute__((packed, aligned (8)));
1153 
1154 struct ipr_hostrcb_raw {
1155 	__be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1156 }__attribute__((packed, aligned (4)));
1157 
1158 struct ipr_hcam {
1159 	u8 op_code;
1160 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE			0xE1
1161 #define IPR_HOST_RCB_OP_CODE_LOG_DATA				0xE2
1162 
1163 	u8 notify_type;
1164 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED	0x00
1165 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY			0x01
1166 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY			0x02
1167 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY		0x10
1168 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY	0x11
1169 
1170 	u8 notifications_lost;
1171 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST			0
1172 #define IPR_HOST_RCB_NOTIFICATIONS_LOST				0x80
1173 
1174 	u8 flags;
1175 #define IPR_HOSTRCB_INTERNAL_OPER	0x80
1176 #define IPR_HOSTRCB_ERR_RESP_SENT	0x40
1177 
1178 	u8 overlay_id;
1179 #define IPR_HOST_RCB_OVERLAY_ID_1				0x01
1180 #define IPR_HOST_RCB_OVERLAY_ID_2				0x02
1181 #define IPR_HOST_RCB_OVERLAY_ID_3				0x03
1182 #define IPR_HOST_RCB_OVERLAY_ID_4				0x04
1183 #define IPR_HOST_RCB_OVERLAY_ID_6				0x06
1184 #define IPR_HOST_RCB_OVERLAY_ID_7				0x07
1185 #define IPR_HOST_RCB_OVERLAY_ID_12				0x12
1186 #define IPR_HOST_RCB_OVERLAY_ID_13				0x13
1187 #define IPR_HOST_RCB_OVERLAY_ID_14				0x14
1188 #define IPR_HOST_RCB_OVERLAY_ID_16				0x16
1189 #define IPR_HOST_RCB_OVERLAY_ID_17				0x17
1190 #define IPR_HOST_RCB_OVERLAY_ID_20				0x20
1191 #define IPR_HOST_RCB_OVERLAY_ID_21				0x21
1192 #define IPR_HOST_RCB_OVERLAY_ID_23				0x23
1193 #define IPR_HOST_RCB_OVERLAY_ID_24				0x24
1194 #define IPR_HOST_RCB_OVERLAY_ID_26				0x26
1195 #define IPR_HOST_RCB_OVERLAY_ID_30				0x30
1196 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT				0xFF
1197 
1198 	u8 reserved1[3];
1199 	__be32 ilid;
1200 	__be32 time_since_last_ioa_reset;
1201 	__be32 reserved2;
1202 	__be32 length;
1203 
1204 	union {
1205 		struct ipr_hostrcb_error error;
1206 		struct ipr_hostrcb64_error error64;
1207 		struct ipr_hostrcb_cfg_ch_not ccn;
1208 		struct ipr_hostrcb_raw raw;
1209 	} u;
1210 }__attribute__((packed, aligned (4)));
1211 
1212 struct ipr_hostrcb {
1213 	struct ipr_hcam hcam;
1214 	dma_addr_t hostrcb_dma;
1215 	struct list_head queue;
1216 	struct ipr_ioa_cfg *ioa_cfg;
1217 	char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1218 };
1219 
1220 /* IPR smart dump table structures */
1221 struct ipr_sdt_entry {
1222 	__be32 start_token;
1223 	__be32 end_token;
1224 	u8 reserved[4];
1225 
1226 	u8 flags;
1227 #define IPR_SDT_ENDIAN		0x80
1228 #define IPR_SDT_VALID_ENTRY	0x20
1229 
1230 	u8 resv;
1231 	__be16 priority;
1232 }__attribute__((packed, aligned (4)));
1233 
1234 struct ipr_sdt_header {
1235 	__be32 state;
1236 	__be32 num_entries;
1237 	__be32 num_entries_used;
1238 	__be32 dump_size;
1239 }__attribute__((packed, aligned (4)));
1240 
1241 struct ipr_sdt {
1242 	struct ipr_sdt_header hdr;
1243 	struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1244 }__attribute__((packed, aligned (4)));
1245 
1246 struct ipr_uc_sdt {
1247 	struct ipr_sdt_header hdr;
1248 	struct ipr_sdt_entry entry[1];
1249 }__attribute__((packed, aligned (4)));
1250 
1251 /*
1252  * Driver types
1253  */
1254 struct ipr_bus_attributes {
1255 	u8 bus;
1256 	u8 qas_enabled;
1257 	u8 bus_width;
1258 	u8 reserved;
1259 	u32 max_xfer_rate;
1260 };
1261 
1262 struct ipr_sata_port {
1263 	struct ipr_ioa_cfg *ioa_cfg;
1264 	struct ata_port *ap;
1265 	struct ipr_resource_entry *res;
1266 	struct ipr_ioasa_gata ioasa;
1267 };
1268 
1269 struct ipr_resource_entry {
1270 	u8 needs_sync_complete:1;
1271 	u8 in_erp:1;
1272 	u8 add_to_ml:1;
1273 	u8 del_from_ml:1;
1274 	u8 resetting_device:1;
1275 	u8 reset_occurred:1;
1276 
1277 	u32 bus;		/* AKA channel */
1278 	u32 target;		/* AKA id */
1279 	u32 lun;
1280 #define IPR_ARRAY_VIRTUAL_BUS			0x1
1281 #define IPR_VSET_VIRTUAL_BUS			0x2
1282 #define IPR_IOAFP_VIRTUAL_BUS			0x3
1283 
1284 #define IPR_GET_RES_PHYS_LOC(res) \
1285 	(((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1286 
1287 	u8 ata_class;
1288 
1289 	u8 flags;
1290 	__be16 res_flags;
1291 
1292 	u8 type;
1293 
1294 	u8 qmodel;
1295 	struct ipr_std_inq_data std_inq_data;
1296 
1297 	__be32 res_handle;
1298 	__be64 dev_id;
1299 	__be64 lun_wwn;
1300 	struct scsi_lun dev_lun;
1301 	u8 res_path[8];
1302 
1303 	struct ipr_ioa_cfg *ioa_cfg;
1304 	struct scsi_device *sdev;
1305 	struct ipr_sata_port *sata_port;
1306 	struct list_head queue;
1307 }; /* struct ipr_resource_entry */
1308 
1309 struct ipr_resource_hdr {
1310 	u16 num_entries;
1311 	u16 reserved;
1312 };
1313 
1314 struct ipr_misc_cbs {
1315 	struct ipr_ioa_vpd ioa_vpd;
1316 	struct ipr_inquiry_page0 page0_data;
1317 	struct ipr_inquiry_page3 page3_data;
1318 	struct ipr_inquiry_cap cap;
1319 	struct ipr_mode_pages mode_pages;
1320 	struct ipr_supported_device supp_dev;
1321 };
1322 
1323 struct ipr_interrupt_offsets {
1324 	unsigned long set_interrupt_mask_reg;
1325 	unsigned long clr_interrupt_mask_reg;
1326 	unsigned long clr_interrupt_mask_reg32;
1327 	unsigned long sense_interrupt_mask_reg;
1328 	unsigned long sense_interrupt_mask_reg32;
1329 	unsigned long clr_interrupt_reg;
1330 	unsigned long clr_interrupt_reg32;
1331 
1332 	unsigned long sense_interrupt_reg;
1333 	unsigned long sense_interrupt_reg32;
1334 	unsigned long ioarrin_reg;
1335 	unsigned long sense_uproc_interrupt_reg;
1336 	unsigned long sense_uproc_interrupt_reg32;
1337 	unsigned long set_uproc_interrupt_reg;
1338 	unsigned long set_uproc_interrupt_reg32;
1339 	unsigned long clr_uproc_interrupt_reg;
1340 	unsigned long clr_uproc_interrupt_reg32;
1341 
1342 	unsigned long init_feedback_reg;
1343 
1344 	unsigned long dump_addr_reg;
1345 	unsigned long dump_data_reg;
1346 
1347 #define IPR_ENDIAN_SWAP_KEY		0x00080800
1348 	unsigned long endian_swap_reg;
1349 };
1350 
1351 struct ipr_interrupts {
1352 	void __iomem *set_interrupt_mask_reg;
1353 	void __iomem *clr_interrupt_mask_reg;
1354 	void __iomem *clr_interrupt_mask_reg32;
1355 	void __iomem *sense_interrupt_mask_reg;
1356 	void __iomem *sense_interrupt_mask_reg32;
1357 	void __iomem *clr_interrupt_reg;
1358 	void __iomem *clr_interrupt_reg32;
1359 
1360 	void __iomem *sense_interrupt_reg;
1361 	void __iomem *sense_interrupt_reg32;
1362 	void __iomem *ioarrin_reg;
1363 	void __iomem *sense_uproc_interrupt_reg;
1364 	void __iomem *sense_uproc_interrupt_reg32;
1365 	void __iomem *set_uproc_interrupt_reg;
1366 	void __iomem *set_uproc_interrupt_reg32;
1367 	void __iomem *clr_uproc_interrupt_reg;
1368 	void __iomem *clr_uproc_interrupt_reg32;
1369 
1370 	void __iomem *init_feedback_reg;
1371 
1372 	void __iomem *dump_addr_reg;
1373 	void __iomem *dump_data_reg;
1374 
1375 	void __iomem *endian_swap_reg;
1376 };
1377 
1378 struct ipr_chip_cfg_t {
1379 	u32 mailbox;
1380 	u16 max_cmds;
1381 	u8 cache_line_size;
1382 	u8 clear_isr;
1383 	u32 iopoll_weight;
1384 	struct ipr_interrupt_offsets regs;
1385 };
1386 
1387 struct ipr_chip_t {
1388 	u16 vendor;
1389 	u16 device;
1390 	u16 intr_type;
1391 #define IPR_USE_LSI			0x00
1392 #define IPR_USE_MSI			0x01
1393 #define IPR_USE_MSIX			0x02
1394 	u16 sis_type;
1395 #define IPR_SIS32			0x00
1396 #define IPR_SIS64			0x01
1397 	u16 bist_method;
1398 #define IPR_PCI_CFG			0x00
1399 #define IPR_MMIO			0x01
1400 	const struct ipr_chip_cfg_t *cfg;
1401 };
1402 
1403 enum ipr_shutdown_type {
1404 	IPR_SHUTDOWN_NORMAL = 0x00,
1405 	IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1406 	IPR_SHUTDOWN_ABBREV = 0x80,
1407 	IPR_SHUTDOWN_NONE = 0x100
1408 };
1409 
1410 struct ipr_trace_entry {
1411 	u32 time;
1412 
1413 	u8 op_code;
1414 	u8 ata_op_code;
1415 	u8 type;
1416 #define IPR_TRACE_START			0x00
1417 #define IPR_TRACE_FINISH		0xff
1418 	u8 cmd_index;
1419 
1420 	__be32 res_handle;
1421 	union {
1422 		u32 ioasc;
1423 		u32 add_data;
1424 		u32 res_addr;
1425 	} u;
1426 };
1427 
1428 struct ipr_sglist {
1429 	u32 order;
1430 	u32 num_sg;
1431 	u32 num_dma_sg;
1432 	u32 buffer_len;
1433 	struct scatterlist scatterlist[1];
1434 };
1435 
1436 enum ipr_sdt_state {
1437 	INACTIVE,
1438 	WAIT_FOR_DUMP,
1439 	GET_DUMP,
1440 	READ_DUMP,
1441 	ABORT_DUMP,
1442 	DUMP_OBTAINED
1443 };
1444 
1445 /* Per-controller data */
1446 struct ipr_ioa_cfg {
1447 	char eye_catcher[8];
1448 #define IPR_EYECATCHER			"iprcfg"
1449 
1450 	struct list_head queue;
1451 
1452 	u8 in_reset_reload:1;
1453 	u8 in_ioa_bringdown:1;
1454 	u8 ioa_unit_checked:1;
1455 	u8 dump_taken:1;
1456 	u8 allow_ml_add_del:1;
1457 	u8 needs_hard_reset:1;
1458 	u8 dual_raid:1;
1459 	u8 needs_warm_reset:1;
1460 	u8 msi_received:1;
1461 	u8 sis64:1;
1462 	u8 dump_timeout:1;
1463 	u8 cfg_locked:1;
1464 	u8 clear_isr:1;
1465 	u8 probe_done:1;
1466 
1467 	u8 revid;
1468 
1469 	/*
1470 	 * Bitmaps for SIS64 generated target values
1471 	 */
1472 	unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1473 	unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1474 	unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1475 
1476 	u16 type; /* CCIN of the card */
1477 
1478 	u8 log_level;
1479 #define IPR_MAX_LOG_LEVEL			4
1480 #define IPR_DEFAULT_LOG_LEVEL		2
1481 
1482 #define IPR_NUM_TRACE_INDEX_BITS	8
1483 #define IPR_NUM_TRACE_ENTRIES		(1 << IPR_NUM_TRACE_INDEX_BITS)
1484 #define IPR_TRACE_INDEX_MASK		(IPR_NUM_TRACE_ENTRIES - 1)
1485 #define IPR_TRACE_SIZE	(sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1486 	char trace_start[8];
1487 #define IPR_TRACE_START_LABEL			"trace"
1488 	struct ipr_trace_entry *trace;
1489 	atomic_t trace_index;
1490 
1491 	char cfg_table_start[8];
1492 #define IPR_CFG_TBL_START		"cfg"
1493 	union {
1494 		struct ipr_config_table *cfg_table;
1495 		struct ipr_config_table64 *cfg_table64;
1496 	} u;
1497 	dma_addr_t cfg_table_dma;
1498 	u32 cfg_table_size;
1499 	u32 max_devs_supported;
1500 
1501 	char resource_table_label[8];
1502 #define IPR_RES_TABLE_LABEL		"res_tbl"
1503 	struct ipr_resource_entry *res_entries;
1504 	struct list_head free_res_q;
1505 	struct list_head used_res_q;
1506 
1507 	char ipr_hcam_label[8];
1508 #define IPR_HCAM_LABEL			"hcams"
1509 	struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1510 	dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1511 	struct list_head hostrcb_free_q;
1512 	struct list_head hostrcb_pending_q;
1513 
1514 	struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1515 	u32 hrrq_num;
1516 	atomic_t  hrrq_index;
1517 	u16 identify_hrrq_index;
1518 
1519 	struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1520 
1521 	unsigned int transop_timeout;
1522 	const struct ipr_chip_cfg_t *chip_cfg;
1523 	const struct ipr_chip_t *ipr_chip;
1524 
1525 	void __iomem *hdw_dma_regs;	/* iomapped PCI memory space */
1526 	unsigned long hdw_dma_regs_pci;	/* raw PCI memory space */
1527 	void __iomem *ioa_mailbox;
1528 	struct ipr_interrupts regs;
1529 
1530 	u16 saved_pcix_cmd_reg;
1531 	u16 reset_retries;
1532 
1533 	u32 errors_logged;
1534 	u32 doorbell;
1535 
1536 	struct Scsi_Host *host;
1537 	struct pci_dev *pdev;
1538 	struct ipr_sglist *ucode_sglist;
1539 	u8 saved_mode_page_len;
1540 
1541 	struct work_struct work_q;
1542 
1543 	wait_queue_head_t reset_wait_q;
1544 	wait_queue_head_t msi_wait_q;
1545 	wait_queue_head_t eeh_wait_q;
1546 
1547 	struct ipr_dump *dump;
1548 	enum ipr_sdt_state sdt_state;
1549 
1550 	struct ipr_misc_cbs *vpd_cbs;
1551 	dma_addr_t vpd_cbs_dma;
1552 
1553 	struct pci_pool *ipr_cmd_pool;
1554 
1555 	struct ipr_cmnd *reset_cmd;
1556 	int (*reset) (struct ipr_cmnd *);
1557 
1558 	struct ata_host ata_host;
1559 	char ipr_cmd_label[8];
1560 #define IPR_CMD_LABEL		"ipr_cmd"
1561 	u32 max_cmds;
1562 	struct ipr_cmnd **ipr_cmnd_list;
1563 	dma_addr_t *ipr_cmnd_list_dma;
1564 
1565 	u16 intr_flag;
1566 	unsigned int nvectors;
1567 
1568 	struct {
1569 		unsigned short vec;
1570 		char desc[22];
1571 	} vectors_info[IPR_MAX_MSIX_VECTORS];
1572 
1573 	u32 iopoll_weight;
1574 
1575 }; /* struct ipr_ioa_cfg */
1576 
1577 struct ipr_cmnd {
1578 	struct ipr_ioarcb ioarcb;
1579 	union {
1580 		struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1581 		struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1582 		struct ipr_ata64_ioadl ata_ioadl;
1583 	} i;
1584 	union {
1585 		struct ipr_ioasa ioasa;
1586 		struct ipr_ioasa64 ioasa64;
1587 	} s;
1588 	struct list_head queue;
1589 	struct scsi_cmnd *scsi_cmd;
1590 	struct ata_queued_cmd *qc;
1591 	struct completion completion;
1592 	struct timer_list timer;
1593 	void (*fast_done) (struct ipr_cmnd *);
1594 	void (*done) (struct ipr_cmnd *);
1595 	int (*job_step) (struct ipr_cmnd *);
1596 	int (*job_step_failed) (struct ipr_cmnd *);
1597 	u16 cmd_index;
1598 	u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1599 	dma_addr_t sense_buffer_dma;
1600 	unsigned short dma_use_sg;
1601 	dma_addr_t dma_addr;
1602 	struct ipr_cmnd *sibling;
1603 	union {
1604 		enum ipr_shutdown_type shutdown_type;
1605 		struct ipr_hostrcb *hostrcb;
1606 		unsigned long time_left;
1607 		unsigned long scratch;
1608 		struct ipr_resource_entry *res;
1609 		struct scsi_device *sdev;
1610 	} u;
1611 
1612 	struct completion *eh_comp;
1613 	struct ipr_hrr_queue *hrrq;
1614 	struct ipr_ioa_cfg *ioa_cfg;
1615 };
1616 
1617 struct ipr_ses_table_entry {
1618 	char product_id[17];
1619 	char compare_product_id_byte[17];
1620 	u32 max_bus_speed_limit;	/* MB/sec limit for this backplane */
1621 };
1622 
1623 struct ipr_dump_header {
1624 	u32 eye_catcher;
1625 #define IPR_DUMP_EYE_CATCHER		0xC5D4E3F2
1626 	u32 len;
1627 	u32 num_entries;
1628 	u32 first_entry_offset;
1629 	u32 status;
1630 #define IPR_DUMP_STATUS_SUCCESS			0
1631 #define IPR_DUMP_STATUS_QUAL_SUCCESS		2
1632 #define IPR_DUMP_STATUS_FAILED			0xffffffff
1633 	u32 os;
1634 #define IPR_DUMP_OS_LINUX	0x4C4E5558
1635 	u32 driver_name;
1636 #define IPR_DUMP_DRIVER_NAME	0x49505232
1637 }__attribute__((packed, aligned (4)));
1638 
1639 struct ipr_dump_entry_header {
1640 	u32 eye_catcher;
1641 #define IPR_DUMP_EYE_CATCHER		0xC5D4E3F2
1642 	u32 len;
1643 	u32 num_elems;
1644 	u32 offset;
1645 	u32 data_type;
1646 #define IPR_DUMP_DATA_TYPE_ASCII	0x41534349
1647 #define IPR_DUMP_DATA_TYPE_BINARY	0x42494E41
1648 	u32 id;
1649 #define IPR_DUMP_IOA_DUMP_ID		0x494F4131
1650 #define IPR_DUMP_LOCATION_ID		0x4C4F4341
1651 #define IPR_DUMP_TRACE_ID		0x54524143
1652 #define IPR_DUMP_DRIVER_VERSION_ID	0x44525652
1653 #define IPR_DUMP_DRIVER_TYPE_ID	0x54595045
1654 #define IPR_DUMP_IOA_CTRL_BLK		0x494F4342
1655 #define IPR_DUMP_PEND_OPS		0x414F5053
1656 	u32 status;
1657 }__attribute__((packed, aligned (4)));
1658 
1659 struct ipr_dump_location_entry {
1660 	struct ipr_dump_entry_header hdr;
1661 	u8 location[20];
1662 }__attribute__((packed));
1663 
1664 struct ipr_dump_trace_entry {
1665 	struct ipr_dump_entry_header hdr;
1666 	u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1667 }__attribute__((packed, aligned (4)));
1668 
1669 struct ipr_dump_version_entry {
1670 	struct ipr_dump_entry_header hdr;
1671 	u8 version[sizeof(IPR_DRIVER_VERSION)];
1672 };
1673 
1674 struct ipr_dump_ioa_type_entry {
1675 	struct ipr_dump_entry_header hdr;
1676 	u32 type;
1677 	u32 fw_version;
1678 };
1679 
1680 struct ipr_driver_dump {
1681 	struct ipr_dump_header hdr;
1682 	struct ipr_dump_version_entry version_entry;
1683 	struct ipr_dump_location_entry location_entry;
1684 	struct ipr_dump_ioa_type_entry ioa_type_entry;
1685 	struct ipr_dump_trace_entry trace_entry;
1686 }__attribute__((packed));
1687 
1688 struct ipr_ioa_dump {
1689 	struct ipr_dump_entry_header hdr;
1690 	struct ipr_sdt sdt;
1691 	__be32 **ioa_data;
1692 	u32 reserved;
1693 	u32 next_page_index;
1694 	u32 page_offset;
1695 	u32 format;
1696 }__attribute__((packed, aligned (4)));
1697 
1698 struct ipr_dump {
1699 	struct kref kref;
1700 	struct ipr_ioa_cfg *ioa_cfg;
1701 	struct ipr_driver_dump driver_dump;
1702 	struct ipr_ioa_dump ioa_dump;
1703 };
1704 
1705 struct ipr_error_table_t {
1706 	u32 ioasc;
1707 	int log_ioasa;
1708 	int log_hcam;
1709 	char *error;
1710 };
1711 
1712 struct ipr_software_inq_lid_info {
1713 	__be32 load_id;
1714 	__be32 timestamp[3];
1715 }__attribute__((packed, aligned (4)));
1716 
1717 struct ipr_ucode_image_header {
1718 	__be32 header_length;
1719 	__be32 lid_table_offset;
1720 	u8 major_release;
1721 	u8 card_type;
1722 	u8 minor_release[2];
1723 	u8 reserved[20];
1724 	char eyecatcher[16];
1725 	__be32 num_lids;
1726 	struct ipr_software_inq_lid_info lid[1];
1727 }__attribute__((packed, aligned (4)));
1728 
1729 /*
1730  * Macros
1731  */
1732 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1733 
1734 #ifdef CONFIG_SCSI_IPR_TRACE
1735 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1736 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1737 #else
1738 #define ipr_create_trace_file(kobj, attr) 0
1739 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1740 #endif
1741 
1742 #ifdef CONFIG_SCSI_IPR_DUMP
1743 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1744 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1745 #else
1746 #define ipr_create_dump_file(kobj, attr) 0
1747 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1748 #endif
1749 
1750 /*
1751  * Error logging macros
1752  */
1753 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1754 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1755 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1756 
1757 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1758 	printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1759 		bus, target, lun, ##__VA_ARGS__)
1760 
1761 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1762 	ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1763 
1764 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1765 	printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1766 		(ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1767 
1768 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1769 	ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1770 
1771 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)			\
1772 {									\
1773 	if ((res).bus >= IPR_MAX_NUM_BUSES) {				\
1774 		ipr_err(fmt": unknown\n", ##__VA_ARGS__);		\
1775 	} else {							\
1776 		ipr_err(fmt": %d:%d:%d:%d\n",				\
1777 			##__VA_ARGS__, (ioa_cfg)->host->host_no,	\
1778 			(res).bus, (res).target, (res).lun);		\
1779 	}								\
1780 }
1781 
1782 #define ipr_hcam_err(hostrcb, fmt, ...)					\
1783 {									\
1784 	if (ipr_is_device(hostrcb)) {					\
1785 		if ((hostrcb)->ioa_cfg->sis64) {			\
1786 			printk(KERN_ERR IPR_NAME ": %s: " fmt, 		\
1787 				ipr_format_res_path(hostrcb->ioa_cfg,	\
1788 					hostrcb->hcam.u.error64.fd_res_path, \
1789 					hostrcb->rp_buffer,		\
1790 					sizeof(hostrcb->rp_buffer)),	\
1791 				__VA_ARGS__);				\
1792 		} else {						\
1793 			ipr_ra_err((hostrcb)->ioa_cfg,			\
1794 				(hostrcb)->hcam.u.error.fd_res_addr,	\
1795 				fmt, __VA_ARGS__);			\
1796 		}							\
1797 	} else {							\
1798 		dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1799 	}								\
1800 }
1801 
1802 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1803 	__FILE__, __func__, __LINE__)
1804 
1805 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1806 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1807 
1808 #define ipr_err_separator \
1809 ipr_err("----------------------------------------------------------\n")
1810 
1811 
1812 /*
1813  * Inlines
1814  */
1815 
1816 /**
1817  * ipr_is_ioa_resource - Determine if a resource is the IOA
1818  * @res:	resource entry struct
1819  *
1820  * Return value:
1821  * 	1 if IOA / 0 if not IOA
1822  **/
ipr_is_ioa_resource(struct ipr_resource_entry * res)1823 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1824 {
1825 	return res->type == IPR_RES_TYPE_IOAFP;
1826 }
1827 
1828 /**
1829  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1830  * @res:	resource entry struct
1831  *
1832  * Return value:
1833  * 	1 if AF DASD / 0 if not AF DASD
1834  **/
ipr_is_af_dasd_device(struct ipr_resource_entry * res)1835 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1836 {
1837 	return res->type == IPR_RES_TYPE_AF_DASD ||
1838 		res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1839 }
1840 
1841 /**
1842  * ipr_is_vset_device - Determine if a resource is a VSET
1843  * @res:	resource entry struct
1844  *
1845  * Return value:
1846  * 	1 if VSET / 0 if not VSET
1847  **/
ipr_is_vset_device(struct ipr_resource_entry * res)1848 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1849 {
1850 	return res->type == IPR_RES_TYPE_VOLUME_SET;
1851 }
1852 
1853 /**
1854  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1855  * @res:	resource entry struct
1856  *
1857  * Return value:
1858  * 	1 if GSCSI / 0 if not GSCSI
1859  **/
ipr_is_gscsi(struct ipr_resource_entry * res)1860 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1861 {
1862 	return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1863 }
1864 
1865 /**
1866  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1867  * @res:	resource entry struct
1868  *
1869  * Return value:
1870  * 	1 if SCSI disk / 0 if not SCSI disk
1871  **/
ipr_is_scsi_disk(struct ipr_resource_entry * res)1872 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1873 {
1874 	if (ipr_is_af_dasd_device(res) ||
1875 	    (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1876 		return 1;
1877 	else
1878 		return 0;
1879 }
1880 
1881 /**
1882  * ipr_is_gata - Determine if a resource is a generic ATA resource
1883  * @res:	resource entry struct
1884  *
1885  * Return value:
1886  * 	1 if GATA / 0 if not GATA
1887  **/
ipr_is_gata(struct ipr_resource_entry * res)1888 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1889 {
1890 	return res->type == IPR_RES_TYPE_GENERIC_ATA;
1891 }
1892 
1893 /**
1894  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1895  * @res:	resource entry struct
1896  *
1897  * Return value:
1898  * 	1 if NACA queueing model / 0 if not NACA queueing model
1899  **/
ipr_is_naca_model(struct ipr_resource_entry * res)1900 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1901 {
1902 	if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1903 		return 1;
1904 	return 0;
1905 }
1906 
1907 /**
1908  * ipr_is_device - Determine if the hostrcb structure is related to a device
1909  * @hostrcb:	host resource control blocks struct
1910  *
1911  * Return value:
1912  * 	1 if AF / 0 if not AF
1913  **/
ipr_is_device(struct ipr_hostrcb * hostrcb)1914 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1915 {
1916 	struct ipr_res_addr *res_addr;
1917 	u8 *res_path;
1918 
1919 	if (hostrcb->ioa_cfg->sis64) {
1920 		res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1921 		if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1922 		    res_path[0] == 0x81) && res_path[2] != 0xFF)
1923 			return 1;
1924 	} else {
1925 		res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1926 
1927 		if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1928 		    (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1929 			return 1;
1930 	}
1931 	return 0;
1932 }
1933 
1934 /**
1935  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1936  * @sdt_word:	SDT address
1937  *
1938  * Return value:
1939  * 	1 if format 2 / 0 if not
1940  **/
ipr_sdt_is_fmt2(u32 sdt_word)1941 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1942 {
1943 	u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1944 
1945 	switch (bar_sel) {
1946 	case IPR_SDT_FMT2_BAR0_SEL:
1947 	case IPR_SDT_FMT2_BAR1_SEL:
1948 	case IPR_SDT_FMT2_BAR2_SEL:
1949 	case IPR_SDT_FMT2_BAR3_SEL:
1950 	case IPR_SDT_FMT2_BAR4_SEL:
1951 	case IPR_SDT_FMT2_BAR5_SEL:
1952 	case IPR_SDT_FMT2_EXP_ROM_SEL:
1953 		return 1;
1954 	};
1955 
1956 	return 0;
1957 }
1958 
1959 #ifndef writeq
writeq(u64 val,void __iomem * addr)1960 static inline void writeq(u64 val, void __iomem *addr)
1961 {
1962         writel(((u32) (val >> 32)), addr);
1963         writel(((u32) (val)), (addr + 4));
1964 }
1965 #endif
1966 
1967 #endif /* _IPR_H */
1968