1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_CPUTYPE_H 17 #define __ASM_CPUTYPE_H 18 19 #define INVALID_HWID ULONG_MAX 20 21 #define MPIDR_UP_BITMASK (0x1 << 30) 22 #define MPIDR_MT_BITMASK (0x1 << 24) 23 #define MPIDR_HWID_BITMASK 0xff00ffffff 24 25 #define MPIDR_LEVEL_BITS_SHIFT 3 26 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) 27 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 28 29 #define MPIDR_LEVEL_SHIFT(level) \ 30 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 31 32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 34 35 #define MIDR_REVISION_MASK 0xf 36 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) 37 #define MIDR_PARTNUM_SHIFT 4 38 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) 39 #define MIDR_PARTNUM(midr) \ 40 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) 41 #define MIDR_ARCHITECTURE_SHIFT 16 42 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) 43 #define MIDR_ARCHITECTURE(midr) \ 44 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) 45 #define MIDR_VARIANT_SHIFT 20 46 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) 47 #define MIDR_VARIANT(midr) \ 48 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) 49 #define MIDR_IMPLEMENTOR_SHIFT 24 50 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) 51 #define MIDR_IMPLEMENTOR(midr) \ 52 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) 53 54 #define MIDR_CPU_PART(imp, partnum) \ 55 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ 56 (0xf << MIDR_ARCHITECTURE_SHIFT) | \ 57 ((partnum) << MIDR_PARTNUM_SHIFT)) 58 59 #define ARM_CPU_IMP_ARM 0x41 60 #define ARM_CPU_IMP_APM 0x50 61 62 #define ARM_CPU_PART_AEM_V8 0xD0F 63 #define ARM_CPU_PART_FOUNDATION 0xD00 64 #define ARM_CPU_PART_CORTEX_A57 0xD07 65 #define ARM_CPU_PART_CORTEX_A53 0xD03 66 67 #define APM_CPU_PART_POTENZA 0x000 68 69 #ifndef __ASSEMBLY__ 70 71 #include <asm/sysreg.h> 72 73 #define read_cpuid(reg) ({ \ 74 u64 __val; \ 75 asm("mrs_s %0, " __stringify(reg) : "=r" (__val)); \ 76 __val; \ 77 }) 78 79 /* 80 * The CPU ID never changes at run time, so we might as well tell the 81 * compiler that it's constant. Use this function to read the CPU ID 82 * rather than directly reading processor_id or read_cpuid() directly. 83 */ read_cpuid_id(void)84static inline u32 __attribute_const__ read_cpuid_id(void) 85 { 86 return read_cpuid(SYS_MIDR_EL1); 87 } 88 read_cpuid_mpidr(void)89static inline u64 __attribute_const__ read_cpuid_mpidr(void) 90 { 91 return read_cpuid(SYS_MPIDR_EL1); 92 } 93 read_cpuid_implementor(void)94static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 95 { 96 return MIDR_IMPLEMENTOR(read_cpuid_id()); 97 } 98 read_cpuid_part_number(void)99static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 100 { 101 return MIDR_PARTNUM(read_cpuid_id()); 102 } 103 read_cpuid_cachetype(void)104static inline u32 __attribute_const__ read_cpuid_cachetype(void) 105 { 106 return read_cpuid(SYS_CTR_EL0); 107 } 108 #endif /* __ASSEMBLY__ */ 109 110 #endif 111