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Searched defs:N (Results 1 – 25 of 44) sorted by relevance

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/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_mpu_macros.h96 #define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ argument
100 #define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ argument
104 #define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ argument
108 #define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ argument
112 #define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ argument
116 #define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ argument
120 #define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ argument
124 #define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ argument
128 #define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ argument
132 #define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ argument
[all …]
/arch/frv/include/asm/
Dgdb-stub.h51 #define GDB_REG_GR(N) (N) argument
52 #define GDB_REG_FR(N) (64+(N)) argument
59 #define GDB_REG_DBAR(N) (137+(N)) argument
60 #define GDB_REG_SCR(N) (141+(N)) argument
64 #define GDB_REG_ACC(N) (150+(N)) argument
65 #define GDB_REG_ACCG(N) (158+(N)/4) argument
66 #define GDB_REG_MSR(N) (160+(N)) argument
67 #define GDB_REG_GNER(N) (162+(N)) argument
68 #define GDB_REG_FNER(N) (164+(N)) argument
Dirc-regs.h46 #define __get_IRR(N) ({ __reg(0xfeff9840 + (N) * 8); }) argument
47 #define __set_IRR(N,V) do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0) argument
49 #define __get_IITMR(N) ({ __reg(0xfeff9880 + (N) * 8); }) argument
50 #define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0) argument
Dmb86943a.h28 #define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N))) argument
29 #define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N))) argument
30 #define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N))) argument
/arch/mips/fw/arc/
Dfile.c17 ULONG N, ULONG *Count) in ArcGetDirectoryEntry()
35 ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) in ArcRead()
47 ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) in ArcWrite()
/arch/mn10300/proc-mn103e010/include/proc/
Ddmactl-regs.h20 #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ argument
67 #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ argument
69 #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ argument
71 #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ argument
74 #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent argument
/arch/mn10300/proc-mn2ws0050/include/proc/
Ddmactl-regs.h19 #define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */ argument
69 #define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */ argument
71 #define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */ argument
73 #define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */ argument
76 #define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */ argument
/arch/ia64/lib/
Dmemcpy.S37 # define N (MEM_LAT + 4) macro
176 # define N (MEM_LAT + 5) /* number of stages */ macro
Dcopy_page_mck.S97 #define N (D + 1) macro
/arch/alpha/include/asm/
Dswitch_to.h8 #define switch_to(P,N,L) \ argument
/arch/x86/xen/
Dtrace.c4 #define N(x) [__HYPERVISOR_##x] = "("#x")" macro
/arch/avr32/mach-at32ap/include/mach/
Dat32ap700x.h27 #define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N)) argument
28 #define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N)) argument
29 #define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N)) argument
30 #define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N)) argument
31 #define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N)) argument
/arch/tile/include/gxio/
Dtrio.h271 #define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N) argument
275 #define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N) argument
/arch/sparc/crypto/
Dcamellia_asm.S76 #define ROTL128(S01, S23, TMP1, TMP2, N) \ argument
/arch/arm64/include/asm/
Dhw_breakpoint.h100 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
104 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
/arch/tile/include/hv/
Ddrv_trio_intf.h179 #define HV_TRIO_FLAG_TC(N) \ argument
185 #define HV_TRIO_FLAG_VFUNC(N) \ argument
/arch/arm/include/asm/
Dhw_breakpoint.h105 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
109 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
/arch/frv/kernel/
Dirq.c38 #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16)) argument
/arch/mips/include/asm/mips-boards/
Dbonito64.h351 #define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N))) argument
352 #define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N))) argument
353 #define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N))) argument
372 #define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N))) argument
373 #define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N))) argument
374 #define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N))) argument
/arch/sh/math-emu/
Dmath.c68 #define CMP_X(SZ,R,M,N) do{ \ argument
72 #define EQ_X(SZ,R,M,N) do{ \ argument
99 #define ARITH_X(SZ,OP,M,N) do{ \ argument
285 #define EMU_FLOAT_X(SZ,N) do { \ in NOTYETn() argument
301 #define EMU_FTRC_X(SZ,N) do { \ argument
/arch/frv/include/uapi/asm/
Dregisters.h60 #define __OFFSET(X,N) ((X)+(N)*4) argument
61 #define __OFFSETC(X,N) xxxxxxxxxxxxxxxxxxxxxxxx argument
63 #define __OFFSET(X,N) ((X)+(N)*4) argument
64 #define __OFFSETC(X,N) ((X)+(N)) argument
/arch/m68k/fpsp040/
Dstan.S158 .set N,L_SCR3 define
Dstwotox.S175 .set N,L_SCR1 define
/arch/sparc/include/asm/
Dhead_64.h11 #define GET_GL_GLOBAL(N) \ argument
/arch/cris/boot/compressed/
Dmisc.c140 #define SEROUT(S, N) \ argument
146 #define SEROUT(S, N) do { \ argument

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