1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16 #include "odm_precomp.h"
17 #include "usb_ops_linux.h"
18
19 static const u16 dB_Invert_Table[8][12] = {
20 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
21 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
22 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
23 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
24 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
25 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
26 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
27 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
28 };
29
30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { /* UL DL */
31 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
32 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
33 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
34 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
35 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
36 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
37 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
38 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP => 92U AP */
40 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
41 };
42
43 /* EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 */
44
45 /* Global var */
46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
47 0x7f8001fe, /* 0, +6.0dB */
48 0x788001e2, /* 1, +5.5dB */
49 0x71c001c7, /* 2, +5.0dB */
50 0x6b8001ae, /* 3, +4.5dB */
51 0x65400195, /* 4, +4.0dB */
52 0x5fc0017f, /* 5, +3.5dB */
53 0x5a400169, /* 6, +3.0dB */
54 0x55400155, /* 7, +2.5dB */
55 0x50800142, /* 8, +2.0dB */
56 0x4c000130, /* 9, +1.5dB */
57 0x47c0011f, /* 10, +1.0dB */
58 0x43c0010f, /* 11, +0.5dB */
59 0x40000100, /* 12, +0dB */
60 0x3c8000f2, /* 13, -0.5dB */
61 0x390000e4, /* 14, -1.0dB */
62 0x35c000d7, /* 15, -1.5dB */
63 0x32c000cb, /* 16, -2.0dB */
64 0x300000c0, /* 17, -2.5dB */
65 0x2d4000b5, /* 18, -3.0dB */
66 0x2ac000ab, /* 19, -3.5dB */
67 0x288000a2, /* 20, -4.0dB */
68 0x26000098, /* 21, -4.5dB */
69 0x24000090, /* 22, -5.0dB */
70 0x22000088, /* 23, -5.5dB */
71 0x20000080, /* 24, -6.0dB */
72 0x1e400079, /* 25, -6.5dB */
73 0x1c800072, /* 26, -7.0dB */
74 0x1b00006c, /* 27. -7.5dB */
75 0x19800066, /* 28, -8.0dB */
76 0x18000060, /* 29, -8.5dB */
77 0x16c0005b, /* 30, -9.0dB */
78 0x15800056, /* 31, -9.5dB */
79 0x14400051, /* 32, -10.0dB */
80 0x1300004c, /* 33, -10.5dB */
81 0x12000048, /* 34, -11.0dB */
82 0x11000044, /* 35, -11.5dB */
83 0x10000040, /* 36, -12.0dB */
84 0x0f00003c,/* 37, -12.5dB */
85 0x0e400039,/* 38, -13.0dB */
86 0x0d800036,/* 39, -13.5dB */
87 0x0cc00033,/* 40, -14.0dB */
88 0x0c000030,/* 41, -14.5dB */
89 0x0b40002d,/* 42, -15.0dB */
90 };
91
92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
93 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
94 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
95 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
96 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
97 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
98 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
99 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
100 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
101 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
102 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
103 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
104 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
105 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
106 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
107 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
108 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
109 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
110 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
111 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
112 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
113 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
114 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
115 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
116 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
117 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
118 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
119 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
120 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
121 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
122 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
123 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
124 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
125 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
126 };
127
128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
129 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
130 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
131 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
132 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
133 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
134 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
135 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
136 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
137 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
138 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
139 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
140 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
141 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
142 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
143 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
144 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
145 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
146 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
147 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
148 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
149 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
150 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
151 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
152 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
153 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
154 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
155 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
156 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
157 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
158 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
159 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
160 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
161 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
162 };
163
164 /* Local Function predefine. */
165
166 /* START------------COMMON INFO RELATED--------------- */
167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
168
169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
170
171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
172
173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
174
175 /* START---------------DIG--------------------------- */
176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
177
178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
179
180 void odm_DIG23a(struct rtw_adapter *adapter);
181
182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
183 /* END---------------DIG--------------------------- */
184
185 /* START-------BB POWER SAVE----------------------- */
186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
187
188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
189
190 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm);
191 /* END---------BB POWER SAVE----------------------- */
192
193 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm);
194
195 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
196
197 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm);
198
199 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
200
201 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm);
202
203 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm);
204
205 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
206 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm);
207
208 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
209 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
210
211 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
212
213 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
214
215 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm);
216
217 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
218
219 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
220
221 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
222
223 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm);
224
225 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
226
227 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
228 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
229
230 #define RxDefaultAnt1 0x65a9
231 #define RxDefaultAnt2 0x569a
232
233 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
234 u32 OFDM_Ant1_Cnt,
235 u32 OFDM_Ant2_Cnt,
236 u32 CCK_Ant1_Cnt,
237 u32 CCK_Ant2_Cnt,
238 u8 *pDefAnt
239 );
240
241 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
242 u8 Ant,
243 bool bDualPath
244 );
245
246 /* 3 Export Interface */
247
248 /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
ODM23a_DMInit(struct dm_odm_t * pDM_Odm)249 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
250 {
251 /* For all IC series */
252 odm_CommonInfoSelfInit23a(pDM_Odm);
253 odm_CmnInfoInit_Debug23a(pDM_Odm);
254 odm_DIG23aInit(pDM_Odm);
255 odm_RateAdaptiveMaskInit23a(pDM_Odm);
256
257 odm23a_DynBBPSInit(pDM_Odm);
258 odm_DynamicTxPower23aInit(pDM_Odm);
259 odm_TXPowerTrackingInit23a(pDM_Odm);
260 ODM_EdcaTurboInit23a(pDM_Odm);
261 }
262
263 /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
264 /* You can not add any dummy function here, be care, you can only use DM structure */
265 /* to perform any new ODM_DM. */
ODM_DMWatchdog23a(struct rtw_adapter * adapter)266 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
267 {
268 struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
269 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
270 struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
271
272 /* 2012.05.03 Luke: For all IC series */
273 odm_CmnInfoUpdate_Debug23a(pDM_Odm);
274 odm_CommonInfoSelfUpdate(pHalData);
275 odm_FalseAlarmCounterStatistics23a(pDM_Odm);
276 odm_RSSIMonitorCheck23a(pDM_Odm);
277
278 /* 8723A or 8189ES platform */
279 /* NeilChen--2012--08--24-- */
280 /* Fix Leave LPS issue */
281 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
282 (pDM_Odm->SupportICType & ODM_RTL8723A)) {
283 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
284 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
285 odm_DIG23abyRSSI_LPS(pDM_Odm);
286 } else {
287 odm_DIG23a(adapter);
288 }
289
290 odm_CCKPacketDetectionThresh23a(pDM_Odm);
291
292 if (pwrctrlpriv->bpower_saving)
293 return;
294
295 odm_RefreshRateAdaptiveMask23a(pDM_Odm);
296
297 odm_DynamicBBPowerSaving23a(pDM_Odm);
298
299 ODM_TXPowerTrackingCheck23a(pDM_Odm);
300 odm_EdcaTurboCheck23a(pDM_Odm);
301
302 odm_dtc(pDM_Odm);
303 }
304
305 /* */
306 /* Init /.. Fixed HW value. Only init time. */
307 /* */
ODM_CmnInfoInit23a(struct dm_odm_t * pDM_Odm,enum odm_cmninfo CmnInfo,u32 Value)308 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
309 enum odm_cmninfo CmnInfo,
310 u32 Value
311 )
312 {
313 /* ODM_RT_TRACE(pDM_Odm,); */
314
315 /* */
316 /* This section is used for init value */
317 /* */
318 switch (CmnInfo) {
319 /* Fixed ODM value. */
320 case ODM_CMNINFO_PLATFORM:
321 break;
322 case ODM_CMNINFO_INTERFACE:
323 pDM_Odm->SupportInterface = (u8)Value;
324 break;
325 case ODM_CMNINFO_MP_TEST_CHIP:
326 pDM_Odm->bIsMPChip = (u8)Value;
327 break;
328 case ODM_CMNINFO_IC_TYPE:
329 pDM_Odm->SupportICType = Value;
330 break;
331 case ODM_CMNINFO_CUT_VER:
332 pDM_Odm->CutVersion = (u8)Value;
333 break;
334 case ODM_CMNINFO_FAB_VER:
335 pDM_Odm->FabVersion = (u8)Value;
336 break;
337 case ODM_CMNINFO_RF_TYPE:
338 pDM_Odm->RFType = (u8)Value;
339 break;
340 case ODM_CMNINFO_BOARD_TYPE:
341 pDM_Odm->BoardType = (u8)Value;
342 break;
343 case ODM_CMNINFO_EXT_LNA:
344 pDM_Odm->ExtLNA = (u8)Value;
345 break;
346 case ODM_CMNINFO_EXT_PA:
347 pDM_Odm->ExtPA = (u8)Value;
348 break;
349 case ODM_CMNINFO_EXT_TRSW:
350 pDM_Odm->ExtTRSW = (u8)Value;
351 break;
352 case ODM_CMNINFO_PATCH_ID:
353 pDM_Odm->PatchID = (u8)Value;
354 break;
355 case ODM_CMNINFO_BINHCT_TEST:
356 pDM_Odm->bInHctTest = (bool)Value;
357 break;
358 case ODM_CMNINFO_BWIFI_TEST:
359 pDM_Odm->bWIFITest = (bool)Value;
360 break;
361 case ODM_CMNINFO_SMART_CONCURRENT:
362 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
363 break;
364 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
365 default:
366 /* do nothing */
367 break;
368 }
369
370 /* */
371 /* Tx power tracking BB swing table. */
372 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
373 /* */
374 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
375 pDM_Odm->BbSwingIdxOfdmCurrent = 12;
376 pDM_Odm->BbSwingFlagOfdm = false;
377
378 }
379
ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t * pDM_Odm,enum odm_cmninfo CmnInfo,u16 Index,void * pValue)380 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
381 u16 Index, void *pValue)
382 {
383 /* Hook call by reference pointer. */
384 switch (CmnInfo) {
385 /* Dynamic call by reference pointer. */
386 case ODM_CMNINFO_STA_STATUS:
387 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
388 break;
389 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
390 default:
391 /* do nothing */
392 break;
393 }
394 }
395
396 /* Update Band/CHannel/.. The values are dynamic but non-per-packet. */
ODM_CmnInfoUpdate23a(struct dm_odm_t * pDM_Odm,u32 CmnInfo,u64 Value)397 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
398 {
399 /* This init variable may be changed in run time. */
400 switch (CmnInfo) {
401 case ODM_CMNINFO_RF_TYPE:
402 pDM_Odm->RFType = (u8)Value;
403 break;
404 case ODM_CMNINFO_WIFI_DIRECT:
405 pDM_Odm->bWIFI_Direct = (bool)Value;
406 break;
407 case ODM_CMNINFO_WIFI_DISPLAY:
408 pDM_Odm->bWIFI_Display = (bool)Value;
409 break;
410 case ODM_CMNINFO_LINK:
411 pDM_Odm->bLinked = (bool)Value;
412 break;
413 case ODM_CMNINFO_RSSI_MIN:
414 pDM_Odm->RSSI_Min = (u8)Value;
415 break;
416 case ODM_CMNINFO_DBG_COMP:
417 pDM_Odm->DebugComponents = Value;
418 break;
419 case ODM_CMNINFO_DBG_LEVEL:
420 pDM_Odm->DebugLevel = (u32)Value;
421 break;
422 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
423 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
424 break;
425 case ODM_CMNINFO_RA_THRESHOLD_LOW:
426 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
427 break;
428 }
429
430 }
431
odm_CommonInfoSelfInit23a(struct dm_odm_t * pDM_Odm)432 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
433 )
434 {
435 pDM_Odm->bCckHighPower =
436 (bool) ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter2, BIT(9));
437 pDM_Odm->RFPathRxEnable =
438 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F);
439
440 ODM_InitDebugSetting23a(pDM_Odm);
441 }
442
odm_CommonInfoSelfUpdate(struct hal_data_8723a * pHalData)443 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
444 {
445 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
446 struct sta_info *pEntry;
447 u8 EntryCnt = 0;
448 u8 i;
449
450 if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
451 if (pHalData->nCur40MhzPrimeSC == 1)
452 pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
453 else if (pHalData->nCur40MhzPrimeSC == 2)
454 pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
455 } else {
456 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
457 }
458
459 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
460 pEntry = pDM_Odm->pODM_StaInfo[i];
461 if (pEntry)
462 EntryCnt++;
463 }
464 if (EntryCnt == 1)
465 pDM_Odm->bOneEntryOnly = true;
466 else
467 pDM_Odm->bOneEntryOnly = false;
468 }
469
odm_CmnInfoInit_Debug23a(struct dm_odm_t * pDM_Odm)470 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
471 {
472 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
473 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
484 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
485 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
486 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
487
488 }
489
odm_CmnInfoUpdate_Debug23a(struct dm_odm_t * pDM_Odm)490 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
491 {
492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
497 }
498
ODM_Write_DIG23a(struct dm_odm_t * pDM_Odm,u8 CurrentIGI)499 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
500 u8 CurrentIGI
501 )
502 {
503 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
504
505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
506 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
507
508 if (pDM_DigTable->CurIGValue != CurrentIGI) {
509 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
511 pDM_DigTable->CurIGValue = CurrentIGI;
512 }
513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
514 ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
515 }
516
517 /* Need LPS mode for CE platform --2012--08--24--- */
518 /* 8723AS/8189ES */
odm_DIG23abyRSSI_LPS(struct dm_odm_t * pDM_Odm)519 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
520 {
521 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
522 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
523 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
524 u8 bFwCurrentInPSMode = false;
525 u8 CurrentIGI = pDM_Odm->RSSI_Min;
526
527 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
528 return;
529
530 CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
531 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
532
533 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
534
535 /* Using FW PS mode to make IGI */
536 if (bFwCurrentInPSMode) {
537 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
538 /* Adjust by FA in LPS MODE */
539 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
540 CurrentIGI = CurrentIGI+2;
541 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
542 CurrentIGI = CurrentIGI+1;
543 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
544 CurrentIGI = CurrentIGI-1;
545 } else {
546 CurrentIGI = RSSI_Lower;
547 }
548
549 /* Lower bound checking */
550
551 /* RSSI Lower bound check */
552 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
553 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
554 else
555 RSSI_Lower = DM_DIG_MIN_NIC;
556
557 /* Upper and Lower Bound checking */
558 if (CurrentIGI > DM_DIG_MAX_NIC)
559 CurrentIGI = DM_DIG_MAX_NIC;
560 else if (CurrentIGI < RSSI_Lower)
561 CurrentIGI = RSSI_Lower;
562
563 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
564
565 }
566
odm_DIG23aInit(struct dm_odm_t * pDM_Odm)567 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
568 {
569 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
570
571 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
572 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
573 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
574 pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW;
575 pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH;
576 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
577 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
578 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
579 } else {
580 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
581 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
582 }
583 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
584 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
585 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
586 pDM_DigTable->PreCCK_CCAThres = 0xFF;
587 pDM_DigTable->CurCCK_CCAThres = 0x83;
588 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
589 pDM_DigTable->LargeFAHit = 0;
590 pDM_DigTable->Recover_cnt = 0;
591 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
592 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
593 pDM_DigTable->bMediaConnect_0 = false;
594 pDM_DigTable->bMediaConnect_1 = false;
595 }
596
odm_DIG23a(struct rtw_adapter * adapter)597 void odm_DIG23a(struct rtw_adapter *adapter)
598 {
599 struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
600 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
601 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
602 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
603 u8 DIG_Dynamic_MIN;
604 u8 DIG_MaxOfMin;
605 bool FirstConnect, FirstDisConnect;
606 u8 dm_dig_max, dm_dig_min;
607 u8 CurrentIGI = pDM_DigTable->CurIGValue;
608
609 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
610 /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
611 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
612 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
613 ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
614 return;
615 }
616
617 if (adapter->mlmepriv.bScanInProcess) {
618 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
619 return;
620 }
621
622 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
623 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
624 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
625
626 /* 1 Boundary Decision */
627 if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
628 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
629 dm_dig_max = DM_DIG_MAX_NIC_HP;
630 dm_dig_min = DM_DIG_MIN_NIC_HP;
631 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
632 } else {
633 dm_dig_max = DM_DIG_MAX_NIC;
634 dm_dig_min = DM_DIG_MIN_NIC;
635 DIG_MaxOfMin = DM_DIG_MAX_AP;
636 }
637
638 if (pDM_Odm->bLinked) {
639 /* 2 8723A Series, offset need to be 10 */
640 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
641 /* 2 Upper Bound */
642 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
643 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
644 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
645 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
646 else
647 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
648
649 /* 2 If BT is Concurrent, need to set Lower Bound */
650 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
651 } else {
652 /* 2 Modify DIG upper bound */
653 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
654 pDM_DigTable->rx_gain_range_max = dm_dig_max;
655 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
656 pDM_DigTable->rx_gain_range_max = dm_dig_min;
657 else
658 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
659
660 /* 2 Modify DIG lower bound */
661 if (pDM_Odm->bOneEntryOnly) {
662 if (pDM_Odm->RSSI_Min < dm_dig_min)
663 DIG_Dynamic_MIN = dm_dig_min;
664 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
665 DIG_Dynamic_MIN = DIG_MaxOfMin;
666 else
667 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
668 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
669 ("odm_DIG23a() : bOneEntryOnly = true, DIG_Dynamic_MIN = 0x%x\n",
670 DIG_Dynamic_MIN));
671 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
672 ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
673 pDM_Odm->RSSI_Min));
674 } else {
675 DIG_Dynamic_MIN = dm_dig_min;
676 }
677 }
678 } else {
679 pDM_DigTable->rx_gain_range_max = dm_dig_max;
680 DIG_Dynamic_MIN = dm_dig_min;
681 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
682 }
683
684 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
685 if (pFalseAlmCnt->Cnt_all > 10000) {
686 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
687 ("dm_DIG(): Abnornally false alarm case. \n"));
688
689 if (pDM_DigTable->LargeFAHit != 3)
690 pDM_DigTable->LargeFAHit++;
691 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
692 pDM_DigTable->ForbiddenIGI = CurrentIGI;
693 pDM_DigTable->LargeFAHit = 1;
694 }
695
696 if (pDM_DigTable->LargeFAHit >= 3) {
697 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
698 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
699 else
700 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
701 pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
702 }
703 } else {
704 /* Recovery mechanism for IGI lower bound */
705 if (pDM_DigTable->Recover_cnt != 0) {
706 pDM_DigTable->Recover_cnt--;
707 } else {
708 if (pDM_DigTable->LargeFAHit < 3) {
709 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
710 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
711 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
712 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
713 ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
714 } else {
715 pDM_DigTable->ForbiddenIGI--;
716 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
717 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
718 ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
719 }
720 } else {
721 pDM_DigTable->LargeFAHit = 0;
722 }
723 }
724 }
725 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
726
727 /* 1 Adjust initial gain by false alarm */
728 if (pDM_Odm->bLinked) {
729 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
730 if (FirstConnect) {
731 CurrentIGI = pDM_Odm->RSSI_Min;
732 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
733 } else {
734 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
735 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
736 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
737 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
738 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
739 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
740 }
741 } else {
742 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
743 if (FirstDisConnect) {
744 CurrentIGI = pDM_DigTable->rx_gain_range_min;
745 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
746 } else {
747 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
748 if (pFalseAlmCnt->Cnt_all > 10000)
749 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
750 else if (pFalseAlmCnt->Cnt_all > 8000)
751 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
752 else if (pFalseAlmCnt->Cnt_all < 500)
753 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
754 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
755 }
756 }
757 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
758 /* 1 Check initial gain by upper/lower bound */
759 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
760 CurrentIGI = pDM_DigTable->rx_gain_range_max;
761 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
762 CurrentIGI = pDM_DigTable->rx_gain_range_min;
763
764 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
765 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
766 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
767 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
768
769 /* 2 High power RSSI threshold */
770
771 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
772 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
773 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
774 }
775
776 /* 3 ============================================================ */
777 /* 3 FASLE ALARM CHECK */
778 /* 3 ============================================================ */
779
odm_FalseAlarmCounterStatistics23a(struct dm_odm_t * pDM_Odm)780 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
781 {
782 u32 ret_value;
783 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
784
785 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
786 return;
787
788 /* hold ofdm counter */
789 /* hold page C counter */
790 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
791 /* hold page D counter */
792 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
793 ret_value =
794 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
795 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
796 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
797 ret_value =
798 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
799 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
800 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
801 ret_value =
802 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
803 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
804 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
805 ret_value =
806 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
807 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
808
809 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
810 FalseAlmCnt->Cnt_Rate_Illegal +
811 FalseAlmCnt->Cnt_Crc8_fail +
812 FalseAlmCnt->Cnt_Mcs_fail +
813 FalseAlmCnt->Cnt_Fast_Fsync +
814 FalseAlmCnt->Cnt_SB_Search_fail;
815 /* hold cck counter */
816 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
817 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
818
819 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
820 FalseAlmCnt->Cnt_Cck_fail = ret_value;
821 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
822 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
823
824 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
825 FalseAlmCnt->Cnt_CCK_CCA =
826 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
827
828 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
829 FalseAlmCnt->Cnt_SB_Search_fail +
830 FalseAlmCnt->Cnt_Parity_Fail +
831 FalseAlmCnt->Cnt_Rate_Illegal +
832 FalseAlmCnt->Cnt_Crc8_fail +
833 FalseAlmCnt->Cnt_Mcs_fail +
834 FalseAlmCnt->Cnt_Cck_fail);
835
836 FalseAlmCnt->Cnt_CCA_all =
837 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
838
839 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
840 /* reset false alarm counter registers */
841 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
842 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
843 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
844 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
845 /* update ofdm counter */
846 /* update page C counter */
847 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
848 /* update page D counter */
849 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
850
851 /* reset CCK CCA counter */
852 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
853 BIT(13) | BIT(12), 0);
854 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
855 BIT(13) | BIT(12), 2);
856 /* reset CCK FA counter */
857 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
858 BIT(15) | BIT(14), 0);
859 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
860 BIT(15) | BIT(14), 2);
861 }
862
863 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
864 ("Enter odm_FalseAlarmCounterStatistics23a\n"));
865 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
866 ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
867 FalseAlmCnt->Cnt_Fast_Fsync,
868 FalseAlmCnt->Cnt_SB_Search_fail));
869 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
870 ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
871 FalseAlmCnt->Cnt_Parity_Fail,
872 FalseAlmCnt->Cnt_Rate_Illegal));
873 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
874 ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
875 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
876
877 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
878 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
879 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
880 }
881
882 /* 3 ============================================================ */
883 /* 3 CCK Packet Detect Threshold */
884 /* 3 ============================================================ */
885
odm_CCKPacketDetectionThresh23a(struct dm_odm_t * pDM_Odm)886 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
887 {
888 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
889 u8 CurCCK_CCAThres;
890
891 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
892 return;
893
894 if (pDM_Odm->ExtLNA)
895 return;
896
897 if (pDM_Odm->bLinked) {
898 if (pDM_Odm->RSSI_Min > 25) {
899 CurCCK_CCAThres = 0xcd;
900 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
901 CurCCK_CCAThres = 0x83;
902 } else {
903 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
904 CurCCK_CCAThres = 0x83;
905 else
906 CurCCK_CCAThres = 0x40;
907 }
908 } else {
909 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
910 CurCCK_CCAThres = 0x83;
911 else
912 CurCCK_CCAThres = 0x40;
913 }
914
915 ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
916 }
917
ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t * pDM_Odm,u8 CurCCK_CCAThres)918 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
919 {
920 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
921
922 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
923 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
924 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
925 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
926
927 }
928
929 /* 3 ============================================================ */
930 /* 3 BB Power Save */
931 /* 3 ============================================================ */
odm23a_DynBBPSInit(struct dm_odm_t * pDM_Odm)932 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
933 {
934 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
935
936 pDM_PSTable->PreCCAState = CCA_MAX;
937 pDM_PSTable->CurCCAState = CCA_MAX;
938 pDM_PSTable->PreRFState = RF_MAX;
939 pDM_PSTable->CurRFState = RF_MAX;
940 pDM_PSTable->Rssi_val_min = 0;
941 pDM_PSTable->initialize = 0;
942 }
943
odm_DynamicBBPowerSaving23a(struct dm_odm_t * pDM_Odm)944 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
945 {
946 return;
947 }
948
odm_1R_CCA23a(struct dm_odm_t * pDM_Odm)949 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm)
950 {
951 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
952
953 if (pDM_Odm->RSSI_Min != 0xFF) {
954 if (pDM_PSTable->PreCCAState == CCA_2R) {
955 if (pDM_Odm->RSSI_Min >= 35)
956 pDM_PSTable->CurCCAState = CCA_1R;
957 else
958 pDM_PSTable->CurCCAState = CCA_2R;
959 } else {
960 if (pDM_Odm->RSSI_Min <= 30)
961 pDM_PSTable->CurCCAState = CCA_2R;
962 else
963 pDM_PSTable->CurCCAState = CCA_1R;
964 }
965 } else {
966 pDM_PSTable->CurCCAState = CCA_MAX;
967 }
968
969 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
970 if (pDM_PSTable->CurCCAState == CCA_1R) {
971 if (pDM_Odm->RFType == ODM_2T2R)
972 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
973 else
974 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
975 } else {
976 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
977 /* PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x63); */
978 }
979 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
980 }
981 }
982
ODM_RF_Saving23a(struct dm_odm_t * pDM_Odm,u8 bForceInNormal)983 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
984 {
985 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
986 u8 Rssi_Up_bound = 30 ;
987 u8 Rssi_Low_bound = 25;
988 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
989 Rssi_Up_bound = 50 ;
990 Rssi_Low_bound = 45;
991 }
992 if (pDM_PSTable->initialize == 0) {
993
994 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
995 pDM_PSTable->RegC70 =
996 (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
997 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
998 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
999 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
1000 pDM_PSTable->initialize = 1;
1001 }
1002
1003 if (!bForceInNormal) {
1004 if (pDM_Odm->RSSI_Min != 0xFF) {
1005 if (pDM_PSTable->PreRFState == RF_Normal) {
1006 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1007 pDM_PSTable->CurRFState = RF_Save;
1008 else
1009 pDM_PSTable->CurRFState = RF_Normal;
1010 } else {
1011 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1012 pDM_PSTable->CurRFState = RF_Normal;
1013 else
1014 pDM_PSTable->CurRFState = RF_Save;
1015 }
1016 } else {
1017 pDM_PSTable->CurRFState = RF_MAX;
1018 }
1019 } else {
1020 pDM_PSTable->CurRFState = RF_Normal;
1021 }
1022
1023 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1024 if (pDM_PSTable->CurRFState == RF_Save) {
1025 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
1026 /* Suggested by SD3 Yu-Nan. 2011.01.20. */
1027 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1028 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
1029 ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
1030 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
1031 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
1032 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
1033 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
1034 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
1035 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
1036 } else {
1037 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
1038 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
1039 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1040 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1041 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
1042
1043 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1044 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
1045 }
1046 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1047 }
1048 }
1049
1050 /* 3 ============================================================ */
1051 /* 3 RATR MASK */
1052 /* 3 ============================================================ */
1053 /* 3 ============================================================ */
1054 /* 3 Rate Adaptive */
1055 /* 3 ============================================================ */
1056
odm_RateAdaptiveMaskInit23a(struct dm_odm_t * pDM_Odm)1057 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1058 {
1059 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1060
1061 pOdmRA->Type = DM_Type_ByDriver;
1062 if (pOdmRA->Type == DM_Type_ByDriver)
1063 pDM_Odm->bUseRAMask = true;
1064 else
1065 pDM_Odm->bUseRAMask = false;
1066
1067 pOdmRA->RATRState = DM_RATR_STA_INIT;
1068 pOdmRA->HighRSSIThresh = 50;
1069 pOdmRA->LowRSSIThresh = 20;
1070 }
1071
ODM_Get_Rate_Bitmap23a(struct hal_data_8723a * pHalData,u32 macid,u32 ra_mask,u8 rssi_level)1072 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
1073 u32 ra_mask, u8 rssi_level)
1074 {
1075 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1076 struct sta_info *pEntry;
1077 u32 rate_bitmap = 0x0fffffff;
1078 u8 WirelessMode;
1079
1080 pEntry = pDM_Odm->pODM_StaInfo[macid];
1081 if (!pEntry)
1082 return ra_mask;
1083
1084 WirelessMode = pEntry->wireless_mode;
1085
1086 switch (WirelessMode) {
1087 case ODM_WM_B:
1088 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
1089 rate_bitmap = 0x0000000d;
1090 else
1091 rate_bitmap = 0x0000000f;
1092 break;
1093 case (ODM_WM_A|ODM_WM_G):
1094 if (rssi_level == DM_RATR_STA_HIGH)
1095 rate_bitmap = 0x00000f00;
1096 else
1097 rate_bitmap = 0x00000ff0;
1098 break;
1099 case (ODM_WM_B|ODM_WM_G):
1100 if (rssi_level == DM_RATR_STA_HIGH)
1101 rate_bitmap = 0x00000f00;
1102 else if (rssi_level == DM_RATR_STA_MIDDLE)
1103 rate_bitmap = 0x00000ff0;
1104 else
1105 rate_bitmap = 0x00000ff5;
1106 break;
1107 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1108 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1109 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1110 if (rssi_level == DM_RATR_STA_HIGH) {
1111 rate_bitmap = 0x000f0000;
1112 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1113 rate_bitmap = 0x000ff000;
1114 } else {
1115 if (pHalData->CurrentChannelBW ==
1116 HT_CHANNEL_WIDTH_40)
1117 rate_bitmap = 0x000ff015;
1118 else
1119 rate_bitmap = 0x000ff005;
1120 }
1121 } else {
1122 if (rssi_level == DM_RATR_STA_HIGH) {
1123 rate_bitmap = 0x0f8f0000;
1124 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1125 rate_bitmap = 0x0f8ff000;
1126 } else {
1127 if (pHalData->CurrentChannelBW ==
1128 HT_CHANNEL_WIDTH_40)
1129 rate_bitmap = 0x0f8ff015;
1130 else
1131 rate_bitmap = 0x0f8ff005;
1132 }
1133 }
1134 break;
1135 default:
1136 /* case WIRELESS_11_24N: */
1137 /* case WIRELESS_11_5N: */
1138 if (pDM_Odm->RFType == RF_1T2R)
1139 rate_bitmap = 0x000fffff;
1140 else
1141 rate_bitmap = 0x0fffffff;
1142 break;
1143 }
1144
1145 /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1146 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1147
1148 return rate_bitmap;
1149
1150 }
1151
1152 /*-----------------------------------------------------------------------------
1153 * Function: odm_RefreshRateAdaptiveMask23a()
1154 *
1155 * Overview: Update rate table mask according to rssi
1156 *
1157 * Input: NONE
1158 *
1159 * Output: NONE
1160 *
1161 * Return: NONE
1162 *
1163 * Revised History:
1164 *When Who Remark
1165 *05/27/2009 hpfan Create Version 0.
1166 *
1167 *---------------------------------------------------------------------------*/
odm_RefreshRateAdaptiveMask23a(struct dm_odm_t * pDM_Odm)1168 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1169 {
1170 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1171 return;
1172 /* */
1173 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1174 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1175 /* HW dynamic mechanism. */
1176 /* */
1177 odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1178 }
1179
odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t * pDM_Odm)1180 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm)
1181 {
1182 }
1183
odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t * pDM_Odm)1184 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1185 {
1186 u8 i;
1187 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
1188
1189 if (pAdapter->bDriverStopped) {
1190 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1191 ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1192 return;
1193 }
1194
1195 if (!pDM_Odm->bUseRAMask) {
1196 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1197 ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1198 return;
1199 }
1200
1201 /* printk("==> %s \n", __func__); */
1202
1203 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1204 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1205 if (pstat) {
1206 if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1207 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1208 ("RSSI:%d, RSSI_LEVEL:%d\n",
1209 pstat->rssi_stat.UndecoratedSmoothedPWDB,
1210 pstat->rssi_level));
1211 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1212 }
1213
1214 }
1215 }
1216
1217 }
1218
odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t * pDM_Odm)1219 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm)
1220 {
1221 }
1222
1223 /* Return Value: bool */
1224 /* - true: RATRState is changed. */
ODM_RAStateCheck23a(struct dm_odm_t * pDM_Odm,s32 RSSI,bool bForceUpdate,u8 * pRATRState)1225 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1226 u8 *pRATRState)
1227 {
1228 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1229 const u8 GoUpGap = 5;
1230 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1231 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1232 u8 RATRState;
1233
1234 /* Threshold Adjustment: */
1235 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1236 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
1237 switch (*pRATRState) {
1238 case DM_RATR_STA_INIT:
1239 case DM_RATR_STA_HIGH:
1240 break;
1241 case DM_RATR_STA_MIDDLE:
1242 HighRSSIThreshForRA += GoUpGap;
1243 break;
1244 case DM_RATR_STA_LOW:
1245 HighRSSIThreshForRA += GoUpGap;
1246 LowRSSIThreshForRA += GoUpGap;
1247 break;
1248 default:
1249 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1250 break;
1251 }
1252
1253 /* Decide RATRState by RSSI. */
1254 if (RSSI > HighRSSIThreshForRA)
1255 RATRState = DM_RATR_STA_HIGH;
1256 else if (RSSI > LowRSSIThreshForRA)
1257 RATRState = DM_RATR_STA_MIDDLE;
1258 else
1259 RATRState = DM_RATR_STA_LOW;
1260
1261 if (*pRATRState != RATRState || bForceUpdate) {
1262 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1263 ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1264 *pRATRState = RATRState;
1265 return true;
1266 }
1267 return false;
1268 }
1269
1270 /* 3 ============================================================ */
1271 /* 3 Dynamic Tx Power */
1272 /* 3 ============================================================ */
1273
odm_DynamicTxPower23aInit(struct dm_odm_t * pDM_Odm)1274 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1275 {
1276 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1277 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1278 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1279
1280 /*
1281 * This is never changed, so we should be able to clean up the
1282 * code checking for different values in rtl8723a_rf6052.c
1283 */
1284 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1285 }
1286
1287 /* 3 ============================================================ */
1288 /* 3 RSSI Monitor */
1289 /* 3 ============================================================ */
1290
odm_RSSIMonitorInit(struct dm_odm_t * pDM_Odm)1291 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm)
1292 {
1293 }
1294
odm_RSSIMonitorCheck23a(struct dm_odm_t * pDM_Odm)1295 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1296 {
1297 /* For AP/ADSL use struct rtl8723a_priv * */
1298 /* For CE/NIC use struct rtw_adapter * */
1299
1300 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1301 return;
1302
1303 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1304 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1305 /* HW dynamic mechanism. */
1306 odm_RSSIMonitorCheck23aCE(pDM_Odm);
1307 } /* odm_RSSIMonitorCheck23a */
1308
odm_RSSIMonitorCheck23aMP(struct dm_odm_t * pDM_Odm)1309 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm)
1310 {
1311 }
1312
1313 static void
FindMinimumRSSI(struct rtw_adapter * pAdapter)1314 FindMinimumRSSI(
1315 struct rtw_adapter *pAdapter
1316 )
1317 {
1318 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1319 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1320 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1321
1322 /* 1 1.Determine the minimum RSSI */
1323
1324 if ((!pDM_Odm->bLinked) &&
1325 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1326 pdmpriv->MinUndecoratedPWDBForDM = 0;
1327 else
1328 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1329 }
1330
odm_RSSIMonitorCheck23aCE(struct dm_odm_t * pDM_Odm)1331 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1332 {
1333 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1334 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1335 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1336 int i;
1337 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1338 u8 sta_cnt = 0;
1339 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1340 struct sta_info *psta;
1341
1342 if (!pDM_Odm->bLinked)
1343 return;
1344
1345 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1346 psta = pDM_Odm->pODM_StaInfo[i];
1347 if (psta) {
1348 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1349 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1350
1351 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1352 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1353
1354 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1355 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1356 }
1357 }
1358
1359 for (i = 0; i < sta_cnt; i++) {
1360 if (PWDB_rssi[i] != (0)) {
1361 if (pHalData->fw_ractrl) /* Report every sta's RSSI to FW */
1362 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1363 }
1364 }
1365
1366 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
1367 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1368 else
1369 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1370
1371 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
1372 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1373 else
1374 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1375
1376 FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1377
1378 ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1379 }
1380
odm_RSSIMonitorCheck23aAP(struct dm_odm_t * pDM_Odm)1381 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm)
1382 {
1383 }
1384
1385 /* endif */
1386 /* 3 ============================================================ */
1387 /* 3 Tx Power Tracking */
1388 /* 3 ============================================================ */
1389
odm_TXPowerTrackingInit23a(struct dm_odm_t * pDM_Odm)1390 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1391 {
1392 odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1393 }
1394
odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t * pDM_Odm)1395 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1396 {
1397 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1398 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1399 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1400
1401 pdmpriv->bTXPowerTracking = true;
1402 pdmpriv->TXPowercount = 0;
1403 pdmpriv->bTXPowerTrackingInit = false;
1404 pdmpriv->TxPowerTrackControl = true;
1405 MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1406
1407 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1408 }
1409
ODM_TXPowerTrackingCheck23a(struct dm_odm_t * pDM_Odm)1410 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1411 {
1412 /* For AP/ADSL use struct rtl8723a_priv * */
1413 /* For CE/NIC use struct rtw_adapter * */
1414
1415 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1416 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1417 /* HW dynamic mechanism. */
1418 odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1419 }
1420
odm_TXPowerTrackingCheckCE23a(struct dm_odm_t * pDM_Odm)1421 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1422 {
1423 }
1424
odm_TXPowerTrackingCheckMP(struct dm_odm_t * pDM_Odm)1425 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm)
1426 {
1427 }
1428
odm_TXPowerTrackingCheckAP(struct dm_odm_t * pDM_Odm)1429 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm)
1430 {
1431 }
1432
1433 /* EDCA Turbo */
ODM_EdcaTurboInit23a(struct dm_odm_t * pDM_Odm)1434 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1435 {
1436
1437 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1438 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1439 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1440 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1441
1442 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1443 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1444 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1445 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1446
1447 } /* ODM_InitEdcaTurbo */
1448
odm_EdcaTurboCheck23a(struct dm_odm_t * pDM_Odm)1449 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1450 {
1451 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1452 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1453 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1454 struct recv_priv *precvpriv = &Adapter->recvpriv;
1455 struct registry_priv *pregpriv = &Adapter->registrypriv;
1456 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1457 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1458 u32 trafficIndex;
1459 u32 edca_param;
1460 u64 cur_tx_bytes = 0;
1461 u64 cur_rx_bytes = 0;
1462 u8 bbtchange = false;
1463
1464 /* For AP/ADSL use struct rtl8723a_priv * */
1465 /* For CE/NIC use struct rtw_adapter * */
1466
1467 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1468 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1469 /* HW dynamic mechanism. */
1470
1471 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1472 return;
1473
1474 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1475 goto dm_CheckEdcaTurbo_EXIT;
1476
1477 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1478 goto dm_CheckEdcaTurbo_EXIT;
1479
1480 if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1481 goto dm_CheckEdcaTurbo_EXIT;
1482
1483 /* Check if the status needs to be changed. */
1484 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1485 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1486 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1487
1488 /* traffic, TX or RX */
1489 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1490 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1491 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1492 /* Uplink TP is present. */
1493 trafficIndex = UP_LINK;
1494 } else { /* Balance TP is present. */
1495 trafficIndex = DOWN_LINK;
1496 }
1497 } else {
1498 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1499 /* Downlink TP is present. */
1500 trafficIndex = DOWN_LINK;
1501 } else { /* Balance TP is present. */
1502 trafficIndex = UP_LINK;
1503 }
1504 }
1505
1506 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1507 (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1508 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1509 (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1510 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1511 else
1512 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1513 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1514 edca_param);
1515
1516 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1517 }
1518
1519 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1520 } else {
1521 /* Turn Off EDCA turbo here. */
1522 /* Restore original EDCA according to the declaration of AP. */
1523 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1524 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1525 pHalData->AcParam_BE);
1526 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1527 }
1528 }
1529
1530 dm_CheckEdcaTurbo_EXIT:
1531 /* Set variables for next time. */
1532 precvpriv->bIsAnyNonBEPkts = false;
1533 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1534 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1535 }
1536
GetPSDData(struct dm_odm_t * pDM_Odm,unsigned int point,u8 initial_gain_psd)1537 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1538 {
1539 u32 psd_report;
1540
1541 /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1542 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1543
1544 /* Start PSD calculation, Reg808[22]= 0->1 */
1545 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1546 /* Need to wait for HW PSD report */
1547 udelay(30);
1548 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1549 /* Read PSD report, Reg8B4[15:0] */
1550 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1551
1552 psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1553
1554 return psd_report;
1555 }
1556
1557 u32
ConvertTo_dB23a(u32 Value)1558 ConvertTo_dB23a(
1559 u32 Value)
1560 {
1561 u8 i;
1562 u8 j;
1563 u32 dB;
1564
1565 Value = Value & 0xFFFF;
1566
1567 for (i = 0; i < 8; i++) {
1568 if (Value <= dB_Invert_Table[i][11])
1569 break;
1570 }
1571
1572 if (i >= 8)
1573 return 96; /* maximum 96 dB */
1574
1575 for (j = 0; j < 12; j++) {
1576 if (Value <= dB_Invert_Table[i][j])
1577 break;
1578 }
1579
1580 dB = i*12 + j + 1;
1581
1582 return dB;
1583 }
1584
1585 /* */
1586 /* Description: */
1587 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1588 /* */
1589 /* Added by Joseph, 2012.03.22 */
1590 /* */
ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t * pDM_Odm)1591 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1592 {
1593 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1594 pDM_SWAT_Table->ANTA_ON = true;
1595 pDM_SWAT_Table->ANTB_ON = true;
1596 }
1597
1598 /* 2 8723A ANT DETECT */
1599
odm_PHY_SaveAFERegisters(struct dm_odm_t * pDM_Odm,u32 * AFEReg,u32 * AFEBackup,u32 RegisterNum)1600 static void odm_PHY_SaveAFERegisters(
1601 struct dm_odm_t *pDM_Odm,
1602 u32 *AFEReg,
1603 u32 *AFEBackup,
1604 u32 RegisterNum
1605 )
1606 {
1607 u32 i;
1608
1609 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1610 for (i = 0 ; i < RegisterNum ; i++)
1611 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1612 }
1613
odm_PHY_ReloadAFERegisters(struct dm_odm_t * pDM_Odm,u32 * AFEReg,u32 * AFEBackup,u32 RegiesterNum)1614 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1615 u32 *AFEBackup, u32 RegiesterNum)
1616 {
1617 u32 i;
1618
1619 for (i = 0 ; i < RegiesterNum; i++)
1620 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1621 }
1622
1623 /* 2 8723A ANT DETECT */
1624 /* Description: */
1625 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1626 /* This function is cooperated with BB team Neil. */
ODM_SingleDualAntennaDetection(struct dm_odm_t * pDM_Odm,u8 mode)1627 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1628 {
1629 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1630 u32 CurrentChannel, RfLoopReg;
1631 u8 n;
1632 u32 Reg88c, Regc08, Reg874, Regc50;
1633 u8 initial_gain = 0x5a;
1634 u32 PSD_report_tmp;
1635 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1636 bool bResult = true;
1637 u32 AFE_Backup[16];
1638 u32 AFE_REG_8723A[16] = {
1639 rRx_Wait_CCA, rTx_CCK_RFON,
1640 rTx_CCK_BBON, rTx_OFDM_RFON,
1641 rTx_OFDM_BBON, rTx_To_Rx,
1642 rTx_To_Tx, rRx_CCK,
1643 rRx_OFDM, rRx_Wait_RIFS,
1644 rRx_TO_Rx, rStandby,
1645 rSleep, rPMPD_ANAEN,
1646 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1647
1648 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1649 return bResult;
1650
1651 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1652 return bResult;
1653 /* 1 Backup Current RF/BB Settings */
1654
1655 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1656 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1657 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
1658 /* Step 1: USE IQK to transmitter single tone */
1659
1660 udelay(10);
1661
1662 /* Store A Path Register 88c, c08, 874, c50 */
1663 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1664 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1665 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1666 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1667
1668 /* Store AFE Registers */
1669 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1670
1671 /* Set PSD 128 pts */
1672 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1673
1674 /* To SET CH1 to do */
1675 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
1676
1677 /* AFE all on step */
1678 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1679 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1680 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1681 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1682 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1683 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1684 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1685 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1686 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1687 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1688 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1689 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1690 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1691 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1692 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1693 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1694
1695 /* 3 wire Disable */
1696 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1697
1698 /* BB IQK Setting */
1699 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1700 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1701
1702 /* IQK setting tone@ 4.34Mhz */
1703 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1704 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1705
1706 /* Page B init */
1707 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1708 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1709 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1710 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1711 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1712 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1713 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1714
1715 /* RF loop Setting */
1716 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1717
1718 /* IQK Single tone start */
1719 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1720 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1721 udelay(1000);
1722 PSD_report_tmp = 0x0;
1723
1724 for (n = 0; n < 2; n++) {
1725 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1726 if (PSD_report_tmp > AntA_report)
1727 AntA_report = PSD_report_tmp;
1728 }
1729
1730 PSD_report_tmp = 0x0;
1731
1732 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
1733 udelay(10);
1734
1735 for (n = 0; n < 2; n++) {
1736 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1737 if (PSD_report_tmp > AntB_report)
1738 AntB_report = PSD_report_tmp;
1739 }
1740
1741 /* change to open case */
1742 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
1743 udelay(10);
1744
1745 for (n = 0; n < 2; n++) {
1746 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1747 if (PSD_report_tmp > AntO_report)
1748 AntO_report = PSD_report_tmp;
1749 }
1750
1751 /* Close IQK Single Tone function */
1752 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1753 PSD_report_tmp = 0x0;
1754
1755 /* 1 Return to antanna A */
1756 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1757 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1758 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1759 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1760 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1761 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1762 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1763 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1764
1765 /* Reload AFE Registers */
1766 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1767
1768 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1769 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1770 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1771
1772 /* 2 Test Ant B based on Ant A is ON */
1773 if (mode == ANTTESTB) {
1774 if (AntA_report >= 100) {
1775 if (AntB_report > (AntA_report+1)) {
1776 pDM_SWAT_Table->ANTB_ON = false;
1777 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1778 } else {
1779 pDM_SWAT_Table->ANTB_ON = true;
1780 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1781 }
1782 } else {
1783 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1784 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1785 bResult = false;
1786 }
1787 } else if (mode == ANTTESTALL) {
1788 /* 2 Test Ant A and B based on DPDT Open */
1789 if ((AntO_report >= 100) & (AntO_report < 118)) {
1790 if (AntA_report > (AntO_report+1)) {
1791 pDM_SWAT_Table->ANTA_ON = false;
1792 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1793 } else {
1794 pDM_SWAT_Table->ANTA_ON = true;
1795 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1796 }
1797
1798 if (AntB_report > (AntO_report+2)) {
1799 pDM_SWAT_Table->ANTB_ON = false;
1800 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1801 } else {
1802 pDM_SWAT_Table->ANTB_ON = true;
1803 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1804 }
1805 }
1806 } else {
1807 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1808 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
1809 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1810 bResult = false;
1811 }
1812 return bResult;
1813 }
1814
1815 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
odm_dtc(struct dm_odm_t * pDM_Odm)1816 void odm_dtc(struct dm_odm_t *pDM_Odm)
1817 {
1818 }
1819