1 #ifndef __KVM_X86_MMU_H
2 #define __KVM_X86_MMU_H
3
4 #include <linux/kvm_host.h>
5 #include "kvm_cache_regs.h"
6
7 #define PT64_PT_BITS 9
8 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9 #define PT32_PT_BITS 10
10 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
11
12 #define PT_WRITABLE_SHIFT 1
13
14 #define PT_PRESENT_MASK (1ULL << 0)
15 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
16 #define PT_USER_MASK (1ULL << 2)
17 #define PT_PWT_MASK (1ULL << 3)
18 #define PT_PCD_MASK (1ULL << 4)
19 #define PT_ACCESSED_SHIFT 5
20 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
21 #define PT_DIRTY_SHIFT 6
22 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
23 #define PT_PAGE_SIZE_SHIFT 7
24 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
25 #define PT_PAT_MASK (1ULL << 7)
26 #define PT_GLOBAL_MASK (1ULL << 8)
27 #define PT64_NX_SHIFT 63
28 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
29
30 #define PT_PAT_SHIFT 7
31 #define PT_DIR_PAT_SHIFT 12
32 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
33
34 #define PT32_DIR_PSE36_SIZE 4
35 #define PT32_DIR_PSE36_SHIFT 13
36 #define PT32_DIR_PSE36_MASK \
37 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
38
39 #define PT64_ROOT_LEVEL 4
40 #define PT32_ROOT_LEVEL 2
41 #define PT32E_ROOT_LEVEL 3
42
43 #define PT_PDPE_LEVEL 3
44 #define PT_DIRECTORY_LEVEL 2
45 #define PT_PAGE_TABLE_LEVEL 1
46
47 #define PFERR_PRESENT_BIT 0
48 #define PFERR_WRITE_BIT 1
49 #define PFERR_USER_BIT 2
50 #define PFERR_RSVD_BIT 3
51 #define PFERR_FETCH_BIT 4
52
53 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
54 #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
55 #define PFERR_USER_MASK (1U << PFERR_USER_BIT)
56 #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
57 #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
58
rsvd_bits(int s,int e)59 static inline u64 rsvd_bits(int s, int e)
60 {
61 return ((1ULL << (e - s + 1)) - 1) << s;
62 }
63
64 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
65 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
66
67 /*
68 * Return values of handle_mmio_page_fault_common:
69 * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
70 * directly.
71 * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
72 * fault path update the mmio spte.
73 * RET_MMIO_PF_RETRY: let CPU fault again on the address.
74 * RET_MMIO_PF_BUG: bug is detected.
75 */
76 enum {
77 RET_MMIO_PF_EMULATE = 1,
78 RET_MMIO_PF_INVALID = 2,
79 RET_MMIO_PF_RETRY = 0,
80 RET_MMIO_PF_BUG = -1
81 };
82
83 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct);
84 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
85 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
86 bool execonly);
87
kvm_mmu_available_pages(struct kvm * kvm)88 static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
89 {
90 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
91 return kvm->arch.n_max_mmu_pages -
92 kvm->arch.n_used_mmu_pages;
93
94 return 0;
95 }
96
kvm_mmu_reload(struct kvm_vcpu * vcpu)97 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
98 {
99 if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
100 return 0;
101
102 return kvm_mmu_load(vcpu);
103 }
104
is_present_gpte(unsigned long pte)105 static inline int is_present_gpte(unsigned long pte)
106 {
107 return pte & PT_PRESENT_MASK;
108 }
109
110 /*
111 * Currently, we have two sorts of write-protection, a) the first one
112 * write-protects guest page to sync the guest modification, b) another one is
113 * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences
114 * between these two sorts are:
115 * 1) the first case clears SPTE_MMU_WRITEABLE bit.
116 * 2) the first case requires flushing tlb immediately avoiding corrupting
117 * shadow page table between all vcpus so it should be in the protection of
118 * mmu-lock. And the another case does not need to flush tlb until returning
119 * the dirty bitmap to userspace since it only write-protects the page
120 * logged in the bitmap, that means the page in the dirty bitmap is not
121 * missed, so it can flush tlb out of mmu-lock.
122 *
123 * So, there is the problem: the first case can meet the corrupted tlb caused
124 * by another case which write-protects pages but without flush tlb
125 * immediately. In order to making the first case be aware this problem we let
126 * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit
127 * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit.
128 *
129 * Anyway, whenever a spte is updated (only permission and status bits are
130 * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes
131 * readonly, if that happens, we need to flush tlb. Fortunately,
132 * mmu_spte_update() has already handled it perfectly.
133 *
134 * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK:
135 * - if we want to see if it has writable tlb entry or if the spte can be
136 * writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most
137 * case, otherwise
138 * - if we fix page fault on the spte or do write-protection by dirty logging,
139 * check PT_WRITABLE_MASK.
140 *
141 * TODO: introduce APIs to split these two cases.
142 */
is_writable_pte(unsigned long pte)143 static inline int is_writable_pte(unsigned long pte)
144 {
145 return pte & PT_WRITABLE_MASK;
146 }
147
is_write_protection(struct kvm_vcpu * vcpu)148 static inline bool is_write_protection(struct kvm_vcpu *vcpu)
149 {
150 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
151 }
152
153 /*
154 * Will a fault with a given page-fault error code (pfec) cause a permission
155 * fault with the given access (in ACC_* format)?
156 */
permission_fault(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu,unsigned pte_access,unsigned pfec)157 static inline bool permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
158 unsigned pte_access, unsigned pfec)
159 {
160 int cpl = kvm_x86_ops->get_cpl(vcpu);
161 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
162
163 /*
164 * If CPL < 3, SMAP prevention are disabled if EFLAGS.AC = 1.
165 *
166 * If CPL = 3, SMAP applies to all supervisor-mode data accesses
167 * (these are implicit supervisor accesses) regardless of the value
168 * of EFLAGS.AC.
169 *
170 * This computes (cpl < 3) && (rflags & X86_EFLAGS_AC), leaving
171 * the result in X86_EFLAGS_AC. We then insert it in place of
172 * the PFERR_RSVD_MASK bit; this bit will always be zero in pfec,
173 * but it will be one in index if SMAP checks are being overridden.
174 * It is important to keep this branchless.
175 */
176 unsigned long smap = (cpl - 3) & (rflags & X86_EFLAGS_AC);
177 int index = (pfec >> 1) +
178 (smap >> (X86_EFLAGS_AC_BIT - PFERR_RSVD_BIT + 1));
179
180 WARN_ON(pfec & PFERR_RSVD_MASK);
181
182 return (mmu->permissions[index] >> pte_access) & 1;
183 }
184
185 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
186 #endif
187