1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67 #include <linux/interval_tree.h>
68 #include <linux/hashtable.h>
69 #include <linux/fence.h>
70
71 #include <ttm/ttm_bo_api.h>
72 #include <ttm/ttm_bo_driver.h>
73 #include <ttm/ttm_placement.h>
74 #include <ttm/ttm_module.h>
75 #include <ttm/ttm_execbuf_util.h>
76
77 #include <drm/drm_gem.h>
78
79 #include "radeon_family.h"
80 #include "radeon_mode.h"
81 #include "radeon_reg.h"
82
83 /*
84 * Modules parameters.
85 */
86 extern int radeon_no_wb;
87 extern int radeon_modeset;
88 extern int radeon_dynclks;
89 extern int radeon_r4xx_atom;
90 extern int radeon_agpmode;
91 extern int radeon_vram_limit;
92 extern int radeon_gart_size;
93 extern int radeon_benchmarking;
94 extern int radeon_testing;
95 extern int radeon_connector_table;
96 extern int radeon_tv;
97 extern int radeon_audio;
98 extern int radeon_disp_priority;
99 extern int radeon_hw_i2c;
100 extern int radeon_pcie_gen2;
101 extern int radeon_msi;
102 extern int radeon_lockup_timeout;
103 extern int radeon_fastfb;
104 extern int radeon_dpm;
105 extern int radeon_aspm;
106 extern int radeon_runtime_pm;
107 extern int radeon_hard_reset;
108 extern int radeon_vm_size;
109 extern int radeon_vm_block_size;
110 extern int radeon_deep_color;
111 extern int radeon_use_pflipirq;
112 extern int radeon_bapm;
113 extern int radeon_backlight;
114
115 /*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
119 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
121 /* RADEON_IB_POOL_SIZE must be a power of 2 */
122 #define RADEON_IB_POOL_SIZE 16
123 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
124 #define RADEONFB_CONN_LIMIT 4
125 #define RADEON_BIOS_NUM_SCRATCH 8
126
127 /* internal ring indices */
128 /* r1xx+ has gfx CP ring */
129 #define RADEON_RING_TYPE_GFX_INDEX 0
130
131 /* cayman has 2 compute CP rings */
132 #define CAYMAN_RING_TYPE_CP1_INDEX 1
133 #define CAYMAN_RING_TYPE_CP2_INDEX 2
134
135 /* R600+ has an async dma ring */
136 #define R600_RING_TYPE_DMA_INDEX 3
137 /* cayman add a second async dma ring */
138 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
139
140 /* R600+ */
141 #define R600_RING_TYPE_UVD_INDEX 5
142
143 /* TN+ */
144 #define TN_RING_TYPE_VCE1_INDEX 6
145 #define TN_RING_TYPE_VCE2_INDEX 7
146
147 /* max number of rings */
148 #define RADEON_NUM_RINGS 8
149
150 /* number of hw syncs before falling back on blocking */
151 #define RADEON_NUM_SYNCS 4
152
153 /* number of hw syncs before falling back on blocking */
154 #define RADEON_NUM_SYNCS 4
155
156 /* hardcode those limit for now */
157 #define RADEON_VA_IB_OFFSET (1 << 20)
158 #define RADEON_VA_RESERVED_SIZE (8 << 20)
159 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
160
161 /* hard reset data */
162 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
164 /* reset flags */
165 #define RADEON_RESET_GFX (1 << 0)
166 #define RADEON_RESET_COMPUTE (1 << 1)
167 #define RADEON_RESET_DMA (1 << 2)
168 #define RADEON_RESET_CP (1 << 3)
169 #define RADEON_RESET_GRBM (1 << 4)
170 #define RADEON_RESET_DMA1 (1 << 5)
171 #define RADEON_RESET_RLC (1 << 6)
172 #define RADEON_RESET_SEM (1 << 7)
173 #define RADEON_RESET_IH (1 << 8)
174 #define RADEON_RESET_VMC (1 << 9)
175 #define RADEON_RESET_MC (1 << 10)
176 #define RADEON_RESET_DISPLAY (1 << 11)
177
178 /* CG block flags */
179 #define RADEON_CG_BLOCK_GFX (1 << 0)
180 #define RADEON_CG_BLOCK_MC (1 << 1)
181 #define RADEON_CG_BLOCK_SDMA (1 << 2)
182 #define RADEON_CG_BLOCK_UVD (1 << 3)
183 #define RADEON_CG_BLOCK_VCE (1 << 4)
184 #define RADEON_CG_BLOCK_HDP (1 << 5)
185 #define RADEON_CG_BLOCK_BIF (1 << 6)
186
187 /* CG flags */
188 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206 /* PG flags */
207 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
208 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210 #define RADEON_PG_SUPPORT_UVD (1 << 3)
211 #define RADEON_PG_SUPPORT_VCE (1 << 4)
212 #define RADEON_PG_SUPPORT_CP (1 << 5)
213 #define RADEON_PG_SUPPORT_GDS (1 << 6)
214 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
216 #define RADEON_PG_SUPPORT_ACP (1 << 9)
217 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
219 /* max cursor sizes (in pixels) */
220 #define CURSOR_WIDTH 64
221 #define CURSOR_HEIGHT 64
222
223 #define CIK_CURSOR_WIDTH 128
224 #define CIK_CURSOR_HEIGHT 128
225
226 /*
227 * Errata workarounds.
228 */
229 enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233 };
234
235
236 struct radeon_device;
237
238
239 /*
240 * BIOS.
241 */
242 bool radeon_get_bios(struct radeon_device *rdev);
243
244 /*
245 * Dummy page
246 */
247 struct radeon_dummy_page {
248 uint64_t entry;
249 struct page *page;
250 dma_addr_t addr;
251 };
252 int radeon_dummy_page_init(struct radeon_device *rdev);
253 void radeon_dummy_page_fini(struct radeon_device *rdev);
254
255
256 /*
257 * Clocks
258 */
259 struct radeon_clock {
260 struct radeon_pll p1pll;
261 struct radeon_pll p2pll;
262 struct radeon_pll dcpll;
263 struct radeon_pll spll;
264 struct radeon_pll mpll;
265 /* 10 Khz units */
266 uint32_t default_mclk;
267 uint32_t default_sclk;
268 uint32_t default_dispclk;
269 uint32_t current_dispclk;
270 uint32_t dp_extclk;
271 uint32_t max_pixel_clock;
272 };
273
274 /*
275 * Power management
276 */
277 int radeon_pm_init(struct radeon_device *rdev);
278 int radeon_pm_late_init(struct radeon_device *rdev);
279 void radeon_pm_fini(struct radeon_device *rdev);
280 void radeon_pm_compute_clocks(struct radeon_device *rdev);
281 void radeon_pm_suspend(struct radeon_device *rdev);
282 void radeon_pm_resume(struct radeon_device *rdev);
283 void radeon_combios_get_power_modes(struct radeon_device *rdev);
284 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
285 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
286 u8 clock_type,
287 u32 clock,
288 bool strobe_mode,
289 struct atom_clock_dividers *dividers);
290 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
291 u32 clock,
292 bool strobe_mode,
293 struct atom_mpll_param *mpll_param);
294 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
295 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
296 u16 voltage_level, u8 voltage_type,
297 u32 *gpio_value, u32 *gpio_mask);
298 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
299 u32 eng_clock, u32 mem_clock);
300 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
301 u8 voltage_type, u16 *voltage_step);
302 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
303 u16 voltage_id, u16 *voltage);
304 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
305 u16 *voltage,
306 u16 leakage_idx);
307 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
308 u16 *leakage_id);
309 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
310 u16 *vddc, u16 *vddci,
311 u16 virtual_voltage_id,
312 u16 vbios_voltage_id);
313 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
314 u16 virtual_voltage_id,
315 u16 *voltage);
316 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
317 u8 voltage_type,
318 u16 nominal_voltage,
319 u16 *true_voltage);
320 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *min_voltage);
322 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
323 u8 voltage_type, u16 *max_voltage);
324 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
325 u8 voltage_type, u8 voltage_mode,
326 struct atom_voltage_table *voltage_table);
327 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
328 u8 voltage_type, u8 voltage_mode);
329 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
330 u8 voltage_type,
331 u8 *svd_gpio_id, u8 *svc_gpio_id);
332 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
333 u32 mem_clock);
334 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
335 u32 mem_clock);
336 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
337 u8 module_index,
338 struct atom_mc_reg_table *reg_table);
339 int radeon_atom_get_memory_info(struct radeon_device *rdev,
340 u8 module_index, struct atom_memory_info *mem_info);
341 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
342 bool gddr5, u8 module_index,
343 struct atom_memory_clock_range_table *mclk_range_table);
344 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
345 u16 voltage_id, u16 *voltage);
346 void rs690_pm_info(struct radeon_device *rdev);
347 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
348 unsigned *bankh, unsigned *mtaspect,
349 unsigned *tile_split);
350
351 /*
352 * Fences.
353 */
354 struct radeon_fence_driver {
355 struct radeon_device *rdev;
356 uint32_t scratch_reg;
357 uint64_t gpu_addr;
358 volatile uint32_t *cpu_addr;
359 /* sync_seq is protected by ring emission lock */
360 uint64_t sync_seq[RADEON_NUM_RINGS];
361 atomic64_t last_seq;
362 bool initialized, delayed_irq;
363 struct delayed_work lockup_work;
364 };
365
366 struct radeon_fence {
367 struct fence base;
368
369 struct radeon_device *rdev;
370 uint64_t seq;
371 /* RB, DMA, etc. */
372 unsigned ring;
373
374 wait_queue_t fence_wake;
375 };
376
377 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
378 int radeon_fence_driver_init(struct radeon_device *rdev);
379 void radeon_fence_driver_fini(struct radeon_device *rdev);
380 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
381 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
382 void radeon_fence_process(struct radeon_device *rdev, int ring);
383 bool radeon_fence_signaled(struct radeon_fence *fence);
384 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
385 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
386 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
387 int radeon_fence_wait_any(struct radeon_device *rdev,
388 struct radeon_fence **fences,
389 bool intr);
390 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
391 void radeon_fence_unref(struct radeon_fence **fence);
392 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
393 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
394 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)395 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
396 struct radeon_fence *b)
397 {
398 if (!a) {
399 return b;
400 }
401
402 if (!b) {
403 return a;
404 }
405
406 BUG_ON(a->ring != b->ring);
407
408 if (a->seq > b->seq) {
409 return a;
410 } else {
411 return b;
412 }
413 }
414
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)415 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
416 struct radeon_fence *b)
417 {
418 if (!a) {
419 return false;
420 }
421
422 if (!b) {
423 return true;
424 }
425
426 BUG_ON(a->ring != b->ring);
427
428 return a->seq < b->seq;
429 }
430
431 /*
432 * Tiling registers
433 */
434 struct radeon_surface_reg {
435 struct radeon_bo *bo;
436 };
437
438 #define RADEON_GEM_MAX_SURFACES 8
439
440 /*
441 * TTM.
442 */
443 struct radeon_mman {
444 struct ttm_bo_global_ref bo_global_ref;
445 struct drm_global_reference mem_global_ref;
446 struct ttm_bo_device bdev;
447 bool mem_global_referenced;
448 bool initialized;
449
450 #if defined(CONFIG_DEBUG_FS)
451 struct dentry *vram;
452 struct dentry *gtt;
453 #endif
454 };
455
456 /* bo virtual address in a specific vm */
457 struct radeon_bo_va {
458 /* protected by bo being reserved */
459 struct list_head bo_list;
460 uint32_t flags;
461 uint64_t addr;
462 unsigned ref_count;
463
464 /* protected by vm mutex */
465 struct interval_tree_node it;
466 struct list_head vm_status;
467
468 /* constant after initialization */
469 struct radeon_vm *vm;
470 struct radeon_bo *bo;
471 };
472
473 struct radeon_bo {
474 /* Protected by gem.mutex */
475 struct list_head list;
476 /* Protected by tbo.reserved */
477 u32 initial_domain;
478 struct ttm_place placements[3];
479 struct ttm_placement placement;
480 struct ttm_buffer_object tbo;
481 struct ttm_bo_kmap_obj kmap;
482 u32 flags;
483 unsigned pin_count;
484 void *kptr;
485 u32 tiling_flags;
486 u32 pitch;
487 int surface_reg;
488 /* list of all virtual address to which this bo
489 * is associated to
490 */
491 struct list_head va;
492 /* Constant after initialization */
493 struct radeon_device *rdev;
494 struct drm_gem_object gem_base;
495
496 struct ttm_bo_kmap_obj dma_buf_vmap;
497 pid_t pid;
498
499 struct radeon_mn *mn;
500 struct interval_tree_node mn_it;
501 };
502 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
503
504 int radeon_gem_debugfs_init(struct radeon_device *rdev);
505
506 /* sub-allocation manager, it has to be protected by another lock.
507 * By conception this is an helper for other part of the driver
508 * like the indirect buffer or semaphore, which both have their
509 * locking.
510 *
511 * Principe is simple, we keep a list of sub allocation in offset
512 * order (first entry has offset == 0, last entry has the highest
513 * offset).
514 *
515 * When allocating new object we first check if there is room at
516 * the end total_size - (last_object_offset + last_object_size) >=
517 * alloc_size. If so we allocate new object there.
518 *
519 * When there is not enough room at the end, we start waiting for
520 * each sub object until we reach object_offset+object_size >=
521 * alloc_size, this object then become the sub object we return.
522 *
523 * Alignment can't be bigger than page size.
524 *
525 * Hole are not considered for allocation to keep things simple.
526 * Assumption is that there won't be hole (all object on same
527 * alignment).
528 */
529 struct radeon_sa_manager {
530 wait_queue_head_t wq;
531 struct radeon_bo *bo;
532 struct list_head *hole;
533 struct list_head flist[RADEON_NUM_RINGS];
534 struct list_head olist;
535 unsigned size;
536 uint64_t gpu_addr;
537 void *cpu_ptr;
538 uint32_t domain;
539 uint32_t align;
540 };
541
542 struct radeon_sa_bo;
543
544 /* sub-allocation buffer */
545 struct radeon_sa_bo {
546 struct list_head olist;
547 struct list_head flist;
548 struct radeon_sa_manager *manager;
549 unsigned soffset;
550 unsigned eoffset;
551 struct radeon_fence *fence;
552 };
553
554 /*
555 * GEM objects.
556 */
557 struct radeon_gem {
558 struct mutex mutex;
559 struct list_head objects;
560 };
561
562 int radeon_gem_init(struct radeon_device *rdev);
563 void radeon_gem_fini(struct radeon_device *rdev);
564 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
565 int alignment, int initial_domain,
566 u32 flags, bool kernel,
567 struct drm_gem_object **obj);
568
569 int radeon_mode_dumb_create(struct drm_file *file_priv,
570 struct drm_device *dev,
571 struct drm_mode_create_dumb *args);
572 int radeon_mode_dumb_mmap(struct drm_file *filp,
573 struct drm_device *dev,
574 uint32_t handle, uint64_t *offset_p);
575
576 /*
577 * Semaphores.
578 */
579 struct radeon_semaphore {
580 struct radeon_sa_bo *sa_bo;
581 signed waiters;
582 uint64_t gpu_addr;
583 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
584 };
585
586 int radeon_semaphore_create(struct radeon_device *rdev,
587 struct radeon_semaphore **semaphore);
588 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
589 struct radeon_semaphore *semaphore);
590 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
591 struct radeon_semaphore *semaphore);
592 void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
593 struct radeon_fence *fence);
594 int radeon_semaphore_sync_resv(struct radeon_device *rdev,
595 struct radeon_semaphore *semaphore,
596 struct reservation_object *resv,
597 bool shared);
598 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
599 struct radeon_semaphore *semaphore,
600 int waiting_ring);
601 void radeon_semaphore_free(struct radeon_device *rdev,
602 struct radeon_semaphore **semaphore,
603 struct radeon_fence *fence);
604
605 /*
606 * GART structures, functions & helpers
607 */
608 struct radeon_mc;
609
610 #define RADEON_GPU_PAGE_SIZE 4096
611 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
612 #define RADEON_GPU_PAGE_SHIFT 12
613 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
614
615 #define RADEON_GART_PAGE_DUMMY 0
616 #define RADEON_GART_PAGE_VALID (1 << 0)
617 #define RADEON_GART_PAGE_READ (1 << 1)
618 #define RADEON_GART_PAGE_WRITE (1 << 2)
619 #define RADEON_GART_PAGE_SNOOP (1 << 3)
620
621 struct radeon_gart {
622 dma_addr_t table_addr;
623 struct radeon_bo *robj;
624 void *ptr;
625 unsigned num_gpu_pages;
626 unsigned num_cpu_pages;
627 unsigned table_size;
628 struct page **pages;
629 dma_addr_t *pages_addr;
630 uint64_t *pages_entry;
631 bool ready;
632 };
633
634 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
635 void radeon_gart_table_ram_free(struct radeon_device *rdev);
636 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
637 void radeon_gart_table_vram_free(struct radeon_device *rdev);
638 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
639 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
640 int radeon_gart_init(struct radeon_device *rdev);
641 void radeon_gart_fini(struct radeon_device *rdev);
642 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
643 int pages);
644 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
645 int pages, struct page **pagelist,
646 dma_addr_t *dma_addr, uint32_t flags);
647
648
649 /*
650 * GPU MC structures, functions & helpers
651 */
652 struct radeon_mc {
653 resource_size_t aper_size;
654 resource_size_t aper_base;
655 resource_size_t agp_base;
656 /* for some chips with <= 32MB we need to lie
657 * about vram size near mc fb location */
658 u64 mc_vram_size;
659 u64 visible_vram_size;
660 u64 gtt_size;
661 u64 gtt_start;
662 u64 gtt_end;
663 u64 vram_start;
664 u64 vram_end;
665 unsigned vram_width;
666 u64 real_vram_size;
667 int vram_mtrr;
668 bool vram_is_ddr;
669 bool igp_sideport_enabled;
670 u64 gtt_base_align;
671 u64 mc_mask;
672 };
673
674 bool radeon_combios_sideport_present(struct radeon_device *rdev);
675 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
676
677 /*
678 * GPU scratch registers structures, functions & helpers
679 */
680 struct radeon_scratch {
681 unsigned num_reg;
682 uint32_t reg_base;
683 bool free[32];
684 uint32_t reg[32];
685 };
686
687 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
688 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
689
690 /*
691 * GPU doorbell structures, functions & helpers
692 */
693 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
694
695 struct radeon_doorbell {
696 /* doorbell mmio */
697 resource_size_t base;
698 resource_size_t size;
699 u32 __iomem *ptr;
700 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
701 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
702 };
703
704 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
705 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
706
707 /*
708 * IRQS.
709 */
710
711 struct radeon_flip_work {
712 struct work_struct flip_work;
713 struct work_struct unpin_work;
714 struct radeon_device *rdev;
715 int crtc_id;
716 uint64_t base;
717 struct drm_pending_vblank_event *event;
718 struct radeon_bo *old_rbo;
719 struct fence *fence;
720 };
721
722 struct r500_irq_stat_regs {
723 u32 disp_int;
724 u32 hdmi0_status;
725 };
726
727 struct r600_irq_stat_regs {
728 u32 disp_int;
729 u32 disp_int_cont;
730 u32 disp_int_cont2;
731 u32 d1grph_int;
732 u32 d2grph_int;
733 u32 hdmi0_status;
734 u32 hdmi1_status;
735 };
736
737 struct evergreen_irq_stat_regs {
738 u32 disp_int;
739 u32 disp_int_cont;
740 u32 disp_int_cont2;
741 u32 disp_int_cont3;
742 u32 disp_int_cont4;
743 u32 disp_int_cont5;
744 u32 d1grph_int;
745 u32 d2grph_int;
746 u32 d3grph_int;
747 u32 d4grph_int;
748 u32 d5grph_int;
749 u32 d6grph_int;
750 u32 afmt_status1;
751 u32 afmt_status2;
752 u32 afmt_status3;
753 u32 afmt_status4;
754 u32 afmt_status5;
755 u32 afmt_status6;
756 };
757
758 struct cik_irq_stat_regs {
759 u32 disp_int;
760 u32 disp_int_cont;
761 u32 disp_int_cont2;
762 u32 disp_int_cont3;
763 u32 disp_int_cont4;
764 u32 disp_int_cont5;
765 u32 disp_int_cont6;
766 u32 d1grph_int;
767 u32 d2grph_int;
768 u32 d3grph_int;
769 u32 d4grph_int;
770 u32 d5grph_int;
771 u32 d6grph_int;
772 };
773
774 union radeon_irq_stat_regs {
775 struct r500_irq_stat_regs r500;
776 struct r600_irq_stat_regs r600;
777 struct evergreen_irq_stat_regs evergreen;
778 struct cik_irq_stat_regs cik;
779 };
780
781 struct radeon_irq {
782 bool installed;
783 spinlock_t lock;
784 atomic_t ring_int[RADEON_NUM_RINGS];
785 bool crtc_vblank_int[RADEON_MAX_CRTCS];
786 atomic_t pflip[RADEON_MAX_CRTCS];
787 wait_queue_head_t vblank_queue;
788 bool hpd[RADEON_MAX_HPD_PINS];
789 bool afmt[RADEON_MAX_AFMT_BLOCKS];
790 union radeon_irq_stat_regs stat_regs;
791 bool dpm_thermal;
792 };
793
794 int radeon_irq_kms_init(struct radeon_device *rdev);
795 void radeon_irq_kms_fini(struct radeon_device *rdev);
796 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
797 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
798 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
799 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
800 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
801 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
802 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
803 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
804 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
805
806 /*
807 * CP & rings.
808 */
809
810 struct radeon_ib {
811 struct radeon_sa_bo *sa_bo;
812 uint32_t length_dw;
813 uint64_t gpu_addr;
814 uint32_t *ptr;
815 int ring;
816 struct radeon_fence *fence;
817 struct radeon_vm *vm;
818 bool is_const_ib;
819 struct radeon_semaphore *semaphore;
820 };
821
822 struct radeon_ring {
823 struct radeon_bo *ring_obj;
824 volatile uint32_t *ring;
825 unsigned rptr_offs;
826 unsigned rptr_save_reg;
827 u64 next_rptr_gpu_addr;
828 volatile u32 *next_rptr_cpu_addr;
829 unsigned wptr;
830 unsigned wptr_old;
831 unsigned ring_size;
832 unsigned ring_free_dw;
833 int count_dw;
834 atomic_t last_rptr;
835 atomic64_t last_activity;
836 uint64_t gpu_addr;
837 uint32_t align_mask;
838 uint32_t ptr_mask;
839 bool ready;
840 u32 nop;
841 u32 idx;
842 u64 last_semaphore_signal_addr;
843 u64 last_semaphore_wait_addr;
844 /* for CIK queues */
845 u32 me;
846 u32 pipe;
847 u32 queue;
848 struct radeon_bo *mqd_obj;
849 u32 doorbell_index;
850 unsigned wptr_offs;
851 };
852
853 struct radeon_mec {
854 struct radeon_bo *hpd_eop_obj;
855 u64 hpd_eop_gpu_addr;
856 u32 num_pipe;
857 u32 num_mec;
858 u32 num_queue;
859 };
860
861 /*
862 * VM
863 */
864
865 /* maximum number of VMIDs */
866 #define RADEON_NUM_VM 16
867
868 /* number of entries in page table */
869 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
870
871 /* PTBs (Page Table Blocks) need to be aligned to 32K */
872 #define RADEON_VM_PTB_ALIGN_SIZE 32768
873 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
874 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
875
876 #define R600_PTE_VALID (1 << 0)
877 #define R600_PTE_SYSTEM (1 << 1)
878 #define R600_PTE_SNOOPED (1 << 2)
879 #define R600_PTE_READABLE (1 << 5)
880 #define R600_PTE_WRITEABLE (1 << 6)
881
882 /* PTE (Page Table Entry) fragment field for different page sizes */
883 #define R600_PTE_FRAG_4KB (0 << 7)
884 #define R600_PTE_FRAG_64KB (4 << 7)
885 #define R600_PTE_FRAG_256KB (6 << 7)
886
887 /* flags needed to be set so we can copy directly from the GART table */
888 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
889 R600_PTE_SYSTEM | R600_PTE_VALID )
890
891 struct radeon_vm_pt {
892 struct radeon_bo *bo;
893 uint64_t addr;
894 };
895
896 struct radeon_vm {
897 struct rb_root va;
898 unsigned id;
899
900 /* BOs moved, but not yet updated in the PT */
901 struct list_head invalidated;
902
903 /* BOs freed, but not yet updated in the PT */
904 struct list_head freed;
905
906 /* contains the page directory */
907 struct radeon_bo *page_directory;
908 uint64_t pd_gpu_addr;
909 unsigned max_pde_used;
910
911 /* array of page tables, one for each page directory entry */
912 struct radeon_vm_pt *page_tables;
913
914 struct radeon_bo_va *ib_bo_va;
915
916 struct mutex mutex;
917 /* last fence for cs using this vm */
918 struct radeon_fence *fence;
919 /* last flush or NULL if we still need to flush */
920 struct radeon_fence *last_flush;
921 /* last use of vmid */
922 struct radeon_fence *last_id_use;
923 };
924
925 struct radeon_vm_manager {
926 struct radeon_fence *active[RADEON_NUM_VM];
927 uint32_t max_pfn;
928 /* number of VMIDs */
929 unsigned nvm;
930 /* vram base address for page table entry */
931 u64 vram_base_offset;
932 /* is vm enabled? */
933 bool enabled;
934 /* for hw to save the PD addr on suspend/resume */
935 uint32_t saved_table_addr[RADEON_NUM_VM];
936 };
937
938 /*
939 * file private structure
940 */
941 struct radeon_fpriv {
942 struct radeon_vm vm;
943 };
944
945 /*
946 * R6xx+ IH ring
947 */
948 struct r600_ih {
949 struct radeon_bo *ring_obj;
950 volatile uint32_t *ring;
951 unsigned rptr;
952 unsigned ring_size;
953 uint64_t gpu_addr;
954 uint32_t ptr_mask;
955 atomic_t lock;
956 bool enabled;
957 };
958
959 /*
960 * RLC stuff
961 */
962 #include "clearstate_defs.h"
963
964 struct radeon_rlc {
965 /* for power gating */
966 struct radeon_bo *save_restore_obj;
967 uint64_t save_restore_gpu_addr;
968 volatile uint32_t *sr_ptr;
969 const u32 *reg_list;
970 u32 reg_list_size;
971 /* for clear state */
972 struct radeon_bo *clear_state_obj;
973 uint64_t clear_state_gpu_addr;
974 volatile uint32_t *cs_ptr;
975 const struct cs_section_def *cs_data;
976 u32 clear_state_size;
977 /* for cp tables */
978 struct radeon_bo *cp_table_obj;
979 uint64_t cp_table_gpu_addr;
980 volatile uint32_t *cp_table_ptr;
981 u32 cp_table_size;
982 };
983
984 int radeon_ib_get(struct radeon_device *rdev, int ring,
985 struct radeon_ib *ib, struct radeon_vm *vm,
986 unsigned size);
987 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
988 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
989 struct radeon_ib *const_ib, bool hdp_flush);
990 int radeon_ib_pool_init(struct radeon_device *rdev);
991 void radeon_ib_pool_fini(struct radeon_device *rdev);
992 int radeon_ib_ring_tests(struct radeon_device *rdev);
993 /* Ring access between begin & end cannot sleep */
994 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
995 struct radeon_ring *ring);
996 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
997 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
998 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
999 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1000 bool hdp_flush);
1001 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1002 bool hdp_flush);
1003 void radeon_ring_undo(struct radeon_ring *ring);
1004 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1005 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1006 void radeon_ring_lockup_update(struct radeon_device *rdev,
1007 struct radeon_ring *ring);
1008 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1009 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1010 uint32_t **data);
1011 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1012 unsigned size, uint32_t *data);
1013 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1014 unsigned rptr_offs, u32 nop);
1015 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1016
1017
1018 /* r600 async dma */
1019 void r600_dma_stop(struct radeon_device *rdev);
1020 int r600_dma_resume(struct radeon_device *rdev);
1021 void r600_dma_fini(struct radeon_device *rdev);
1022
1023 void cayman_dma_stop(struct radeon_device *rdev);
1024 int cayman_dma_resume(struct radeon_device *rdev);
1025 void cayman_dma_fini(struct radeon_device *rdev);
1026
1027 /*
1028 * CS.
1029 */
1030 struct radeon_cs_reloc {
1031 struct drm_gem_object *gobj;
1032 struct radeon_bo *robj;
1033 struct ttm_validate_buffer tv;
1034 uint64_t gpu_offset;
1035 unsigned prefered_domains;
1036 unsigned allowed_domains;
1037 uint32_t tiling_flags;
1038 uint32_t handle;
1039 };
1040
1041 struct radeon_cs_chunk {
1042 uint32_t chunk_id;
1043 uint32_t length_dw;
1044 uint32_t *kdata;
1045 void __user *user_ptr;
1046 };
1047
1048 struct radeon_cs_parser {
1049 struct device *dev;
1050 struct radeon_device *rdev;
1051 struct drm_file *filp;
1052 /* chunks */
1053 unsigned nchunks;
1054 struct radeon_cs_chunk *chunks;
1055 uint64_t *chunks_array;
1056 /* IB */
1057 unsigned idx;
1058 /* relocations */
1059 unsigned nrelocs;
1060 struct radeon_cs_reloc *relocs;
1061 struct radeon_cs_reloc **relocs_ptr;
1062 struct radeon_cs_reloc *vm_bos;
1063 struct list_head validated;
1064 unsigned dma_reloc_idx;
1065 /* indices of various chunks */
1066 int chunk_ib_idx;
1067 int chunk_relocs_idx;
1068 int chunk_flags_idx;
1069 int chunk_const_ib_idx;
1070 struct radeon_ib ib;
1071 struct radeon_ib const_ib;
1072 void *track;
1073 unsigned family;
1074 int parser_error;
1075 u32 cs_flags;
1076 u32 ring;
1077 s32 priority;
1078 struct ww_acquire_ctx ticket;
1079 };
1080
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1081 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1082 {
1083 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1084
1085 if (ibc->kdata)
1086 return ibc->kdata[idx];
1087 return p->ib.ptr[idx];
1088 }
1089
1090
1091 struct radeon_cs_packet {
1092 unsigned idx;
1093 unsigned type;
1094 unsigned reg;
1095 unsigned opcode;
1096 int count;
1097 unsigned one_reg_wr;
1098 };
1099
1100 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1101 struct radeon_cs_packet *pkt,
1102 unsigned idx, unsigned reg);
1103 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1104 struct radeon_cs_packet *pkt);
1105
1106
1107 /*
1108 * AGP
1109 */
1110 int radeon_agp_init(struct radeon_device *rdev);
1111 void radeon_agp_resume(struct radeon_device *rdev);
1112 void radeon_agp_suspend(struct radeon_device *rdev);
1113 void radeon_agp_fini(struct radeon_device *rdev);
1114
1115
1116 /*
1117 * Writeback
1118 */
1119 struct radeon_wb {
1120 struct radeon_bo *wb_obj;
1121 volatile uint32_t *wb;
1122 uint64_t gpu_addr;
1123 bool enabled;
1124 bool use_event;
1125 };
1126
1127 #define RADEON_WB_SCRATCH_OFFSET 0
1128 #define RADEON_WB_RING0_NEXT_RPTR 256
1129 #define RADEON_WB_CP_RPTR_OFFSET 1024
1130 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1131 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1132 #define R600_WB_DMA_RPTR_OFFSET 1792
1133 #define R600_WB_IH_WPTR_OFFSET 2048
1134 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1135 #define R600_WB_EVENT_OFFSET 3072
1136 #define CIK_WB_CP1_WPTR_OFFSET 3328
1137 #define CIK_WB_CP2_WPTR_OFFSET 3584
1138 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1139 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1140
1141 /**
1142 * struct radeon_pm - power management datas
1143 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1144 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1145 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1146 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1147 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1148 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1149 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1150 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1151 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1152 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1153 * @needed_bandwidth: current bandwidth needs
1154 *
1155 * It keeps track of various data needed to take powermanagement decision.
1156 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1157 * Equation between gpu/memory clock and available bandwidth is hw dependent
1158 * (type of memory, bus size, efficiency, ...)
1159 */
1160
1161 enum radeon_pm_method {
1162 PM_METHOD_PROFILE,
1163 PM_METHOD_DYNPM,
1164 PM_METHOD_DPM,
1165 };
1166
1167 enum radeon_dynpm_state {
1168 DYNPM_STATE_DISABLED,
1169 DYNPM_STATE_MINIMUM,
1170 DYNPM_STATE_PAUSED,
1171 DYNPM_STATE_ACTIVE,
1172 DYNPM_STATE_SUSPENDED,
1173 };
1174 enum radeon_dynpm_action {
1175 DYNPM_ACTION_NONE,
1176 DYNPM_ACTION_MINIMUM,
1177 DYNPM_ACTION_DOWNCLOCK,
1178 DYNPM_ACTION_UPCLOCK,
1179 DYNPM_ACTION_DEFAULT
1180 };
1181
1182 enum radeon_voltage_type {
1183 VOLTAGE_NONE = 0,
1184 VOLTAGE_GPIO,
1185 VOLTAGE_VDDC,
1186 VOLTAGE_SW
1187 };
1188
1189 enum radeon_pm_state_type {
1190 /* not used for dpm */
1191 POWER_STATE_TYPE_DEFAULT,
1192 POWER_STATE_TYPE_POWERSAVE,
1193 /* user selectable states */
1194 POWER_STATE_TYPE_BATTERY,
1195 POWER_STATE_TYPE_BALANCED,
1196 POWER_STATE_TYPE_PERFORMANCE,
1197 /* internal states */
1198 POWER_STATE_TYPE_INTERNAL_UVD,
1199 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1200 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1201 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1202 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1203 POWER_STATE_TYPE_INTERNAL_BOOT,
1204 POWER_STATE_TYPE_INTERNAL_THERMAL,
1205 POWER_STATE_TYPE_INTERNAL_ACPI,
1206 POWER_STATE_TYPE_INTERNAL_ULV,
1207 POWER_STATE_TYPE_INTERNAL_3DPERF,
1208 };
1209
1210 enum radeon_pm_profile_type {
1211 PM_PROFILE_DEFAULT,
1212 PM_PROFILE_AUTO,
1213 PM_PROFILE_LOW,
1214 PM_PROFILE_MID,
1215 PM_PROFILE_HIGH,
1216 };
1217
1218 #define PM_PROFILE_DEFAULT_IDX 0
1219 #define PM_PROFILE_LOW_SH_IDX 1
1220 #define PM_PROFILE_MID_SH_IDX 2
1221 #define PM_PROFILE_HIGH_SH_IDX 3
1222 #define PM_PROFILE_LOW_MH_IDX 4
1223 #define PM_PROFILE_MID_MH_IDX 5
1224 #define PM_PROFILE_HIGH_MH_IDX 6
1225 #define PM_PROFILE_MAX 7
1226
1227 struct radeon_pm_profile {
1228 int dpms_off_ps_idx;
1229 int dpms_on_ps_idx;
1230 int dpms_off_cm_idx;
1231 int dpms_on_cm_idx;
1232 };
1233
1234 enum radeon_int_thermal_type {
1235 THERMAL_TYPE_NONE,
1236 THERMAL_TYPE_EXTERNAL,
1237 THERMAL_TYPE_EXTERNAL_GPIO,
1238 THERMAL_TYPE_RV6XX,
1239 THERMAL_TYPE_RV770,
1240 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1241 THERMAL_TYPE_EVERGREEN,
1242 THERMAL_TYPE_SUMO,
1243 THERMAL_TYPE_NI,
1244 THERMAL_TYPE_SI,
1245 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1246 THERMAL_TYPE_CI,
1247 THERMAL_TYPE_KV,
1248 };
1249
1250 struct radeon_voltage {
1251 enum radeon_voltage_type type;
1252 /* gpio voltage */
1253 struct radeon_gpio_rec gpio;
1254 u32 delay; /* delay in usec from voltage drop to sclk change */
1255 bool active_high; /* voltage drop is active when bit is high */
1256 /* VDDC voltage */
1257 u8 vddc_id; /* index into vddc voltage table */
1258 u8 vddci_id; /* index into vddci voltage table */
1259 bool vddci_enabled;
1260 /* r6xx+ sw */
1261 u16 voltage;
1262 /* evergreen+ vddci */
1263 u16 vddci;
1264 };
1265
1266 /* clock mode flags */
1267 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1268
1269 struct radeon_pm_clock_info {
1270 /* memory clock */
1271 u32 mclk;
1272 /* engine clock */
1273 u32 sclk;
1274 /* voltage info */
1275 struct radeon_voltage voltage;
1276 /* standardized clock flags */
1277 u32 flags;
1278 };
1279
1280 /* state flags */
1281 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1282
1283 struct radeon_power_state {
1284 enum radeon_pm_state_type type;
1285 struct radeon_pm_clock_info *clock_info;
1286 /* number of valid clock modes in this power state */
1287 int num_clock_modes;
1288 struct radeon_pm_clock_info *default_clock_mode;
1289 /* standardized state flags */
1290 u32 flags;
1291 u32 misc; /* vbios specific flags */
1292 u32 misc2; /* vbios specific flags */
1293 int pcie_lanes; /* pcie lanes */
1294 };
1295
1296 /*
1297 * Some modes are overclocked by very low value, accept them
1298 */
1299 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1300
1301 enum radeon_dpm_auto_throttle_src {
1302 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1303 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1304 };
1305
1306 enum radeon_dpm_event_src {
1307 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1308 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1309 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1310 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1311 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1312 };
1313
1314 #define RADEON_MAX_VCE_LEVELS 6
1315
1316 enum radeon_vce_level {
1317 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1318 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1319 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1320 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1321 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1322 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1323 };
1324
1325 struct radeon_ps {
1326 u32 caps; /* vbios flags */
1327 u32 class; /* vbios flags */
1328 u32 class2; /* vbios flags */
1329 /* UVD clocks */
1330 u32 vclk;
1331 u32 dclk;
1332 /* VCE clocks */
1333 u32 evclk;
1334 u32 ecclk;
1335 bool vce_active;
1336 enum radeon_vce_level vce_level;
1337 /* asic priv */
1338 void *ps_priv;
1339 };
1340
1341 struct radeon_dpm_thermal {
1342 /* thermal interrupt work */
1343 struct work_struct work;
1344 /* low temperature threshold */
1345 int min_temp;
1346 /* high temperature threshold */
1347 int max_temp;
1348 /* was interrupt low to high or high to low */
1349 bool high_to_low;
1350 };
1351
1352 enum radeon_clk_action
1353 {
1354 RADEON_SCLK_UP = 1,
1355 RADEON_SCLK_DOWN
1356 };
1357
1358 struct radeon_blacklist_clocks
1359 {
1360 u32 sclk;
1361 u32 mclk;
1362 enum radeon_clk_action action;
1363 };
1364
1365 struct radeon_clock_and_voltage_limits {
1366 u32 sclk;
1367 u32 mclk;
1368 u16 vddc;
1369 u16 vddci;
1370 };
1371
1372 struct radeon_clock_array {
1373 u32 count;
1374 u32 *values;
1375 };
1376
1377 struct radeon_clock_voltage_dependency_entry {
1378 u32 clk;
1379 u16 v;
1380 };
1381
1382 struct radeon_clock_voltage_dependency_table {
1383 u32 count;
1384 struct radeon_clock_voltage_dependency_entry *entries;
1385 };
1386
1387 union radeon_cac_leakage_entry {
1388 struct {
1389 u16 vddc;
1390 u32 leakage;
1391 };
1392 struct {
1393 u16 vddc1;
1394 u16 vddc2;
1395 u16 vddc3;
1396 };
1397 };
1398
1399 struct radeon_cac_leakage_table {
1400 u32 count;
1401 union radeon_cac_leakage_entry *entries;
1402 };
1403
1404 struct radeon_phase_shedding_limits_entry {
1405 u16 voltage;
1406 u32 sclk;
1407 u32 mclk;
1408 };
1409
1410 struct radeon_phase_shedding_limits_table {
1411 u32 count;
1412 struct radeon_phase_shedding_limits_entry *entries;
1413 };
1414
1415 struct radeon_uvd_clock_voltage_dependency_entry {
1416 u32 vclk;
1417 u32 dclk;
1418 u16 v;
1419 };
1420
1421 struct radeon_uvd_clock_voltage_dependency_table {
1422 u8 count;
1423 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1424 };
1425
1426 struct radeon_vce_clock_voltage_dependency_entry {
1427 u32 ecclk;
1428 u32 evclk;
1429 u16 v;
1430 };
1431
1432 struct radeon_vce_clock_voltage_dependency_table {
1433 u8 count;
1434 struct radeon_vce_clock_voltage_dependency_entry *entries;
1435 };
1436
1437 struct radeon_ppm_table {
1438 u8 ppm_design;
1439 u16 cpu_core_number;
1440 u32 platform_tdp;
1441 u32 small_ac_platform_tdp;
1442 u32 platform_tdc;
1443 u32 small_ac_platform_tdc;
1444 u32 apu_tdp;
1445 u32 dgpu_tdp;
1446 u32 dgpu_ulv_power;
1447 u32 tj_max;
1448 };
1449
1450 struct radeon_cac_tdp_table {
1451 u16 tdp;
1452 u16 configurable_tdp;
1453 u16 tdc;
1454 u16 battery_power_limit;
1455 u16 small_power_limit;
1456 u16 low_cac_leakage;
1457 u16 high_cac_leakage;
1458 u16 maximum_power_delivery_limit;
1459 };
1460
1461 struct radeon_dpm_dynamic_state {
1462 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1463 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1464 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1465 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1466 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1467 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1468 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1469 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1470 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1471 struct radeon_clock_array valid_sclk_values;
1472 struct radeon_clock_array valid_mclk_values;
1473 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1474 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1475 u32 mclk_sclk_ratio;
1476 u32 sclk_mclk_delta;
1477 u16 vddc_vddci_delta;
1478 u16 min_vddc_for_pcie_gen2;
1479 struct radeon_cac_leakage_table cac_leakage_table;
1480 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1481 struct radeon_ppm_table *ppm_table;
1482 struct radeon_cac_tdp_table *cac_tdp_table;
1483 };
1484
1485 struct radeon_dpm_fan {
1486 u16 t_min;
1487 u16 t_med;
1488 u16 t_high;
1489 u16 pwm_min;
1490 u16 pwm_med;
1491 u16 pwm_high;
1492 u8 t_hyst;
1493 u32 cycle_delay;
1494 u16 t_max;
1495 bool ucode_fan_control;
1496 };
1497
1498 enum radeon_pcie_gen {
1499 RADEON_PCIE_GEN1 = 0,
1500 RADEON_PCIE_GEN2 = 1,
1501 RADEON_PCIE_GEN3 = 2,
1502 RADEON_PCIE_GEN_INVALID = 0xffff
1503 };
1504
1505 enum radeon_dpm_forced_level {
1506 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1507 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1508 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1509 };
1510
1511 struct radeon_vce_state {
1512 /* vce clocks */
1513 u32 evclk;
1514 u32 ecclk;
1515 /* gpu clocks */
1516 u32 sclk;
1517 u32 mclk;
1518 u8 clk_idx;
1519 u8 pstate;
1520 };
1521
1522 struct radeon_dpm {
1523 struct radeon_ps *ps;
1524 /* number of valid power states */
1525 int num_ps;
1526 /* current power state that is active */
1527 struct radeon_ps *current_ps;
1528 /* requested power state */
1529 struct radeon_ps *requested_ps;
1530 /* boot up power state */
1531 struct radeon_ps *boot_ps;
1532 /* default uvd power state */
1533 struct radeon_ps *uvd_ps;
1534 /* vce requirements */
1535 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1536 enum radeon_vce_level vce_level;
1537 enum radeon_pm_state_type state;
1538 enum radeon_pm_state_type user_state;
1539 u32 platform_caps;
1540 u32 voltage_response_time;
1541 u32 backbias_response_time;
1542 void *priv;
1543 u32 new_active_crtcs;
1544 int new_active_crtc_count;
1545 u32 current_active_crtcs;
1546 int current_active_crtc_count;
1547 bool single_display;
1548 struct radeon_dpm_dynamic_state dyn_state;
1549 struct radeon_dpm_fan fan;
1550 u32 tdp_limit;
1551 u32 near_tdp_limit;
1552 u32 near_tdp_limit_adjusted;
1553 u32 sq_ramping_threshold;
1554 u32 cac_leakage;
1555 u16 tdp_od_limit;
1556 u32 tdp_adjustment;
1557 u16 load_line_slope;
1558 bool power_control;
1559 bool ac_power;
1560 /* special states active */
1561 bool thermal_active;
1562 bool uvd_active;
1563 bool vce_active;
1564 /* thermal handling */
1565 struct radeon_dpm_thermal thermal;
1566 /* forced levels */
1567 enum radeon_dpm_forced_level forced_level;
1568 /* track UVD streams */
1569 unsigned sd;
1570 unsigned hd;
1571 };
1572
1573 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1574 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1575
1576 struct radeon_pm {
1577 struct mutex mutex;
1578 /* write locked while reprogramming mclk */
1579 struct rw_semaphore mclk_lock;
1580 u32 active_crtcs;
1581 int active_crtc_count;
1582 int req_vblank;
1583 bool vblank_sync;
1584 fixed20_12 max_bandwidth;
1585 fixed20_12 igp_sideport_mclk;
1586 fixed20_12 igp_system_mclk;
1587 fixed20_12 igp_ht_link_clk;
1588 fixed20_12 igp_ht_link_width;
1589 fixed20_12 k8_bandwidth;
1590 fixed20_12 sideport_bandwidth;
1591 fixed20_12 ht_bandwidth;
1592 fixed20_12 core_bandwidth;
1593 fixed20_12 sclk;
1594 fixed20_12 mclk;
1595 fixed20_12 needed_bandwidth;
1596 struct radeon_power_state *power_state;
1597 /* number of valid power states */
1598 int num_power_states;
1599 int current_power_state_index;
1600 int current_clock_mode_index;
1601 int requested_power_state_index;
1602 int requested_clock_mode_index;
1603 int default_power_state_index;
1604 u32 current_sclk;
1605 u32 current_mclk;
1606 u16 current_vddc;
1607 u16 current_vddci;
1608 u32 default_sclk;
1609 u32 default_mclk;
1610 u16 default_vddc;
1611 u16 default_vddci;
1612 struct radeon_i2c_chan *i2c_bus;
1613 /* selected pm method */
1614 enum radeon_pm_method pm_method;
1615 /* dynpm power management */
1616 struct delayed_work dynpm_idle_work;
1617 enum radeon_dynpm_state dynpm_state;
1618 enum radeon_dynpm_action dynpm_planned_action;
1619 unsigned long dynpm_action_timeout;
1620 bool dynpm_can_upclock;
1621 bool dynpm_can_downclock;
1622 /* profile-based power management */
1623 enum radeon_pm_profile_type profile;
1624 int profile_index;
1625 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1626 /* internal thermal controller on rv6xx+ */
1627 enum radeon_int_thermal_type int_thermal_type;
1628 struct device *int_hwmon_dev;
1629 /* dpm */
1630 bool dpm_enabled;
1631 bool sysfs_initialized;
1632 struct radeon_dpm dpm;
1633 };
1634
1635 int radeon_pm_get_type_index(struct radeon_device *rdev,
1636 enum radeon_pm_state_type ps_type,
1637 int instance);
1638 /*
1639 * UVD
1640 */
1641 #define RADEON_MAX_UVD_HANDLES 10
1642 #define RADEON_UVD_STACK_SIZE (1024*1024)
1643 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1644
1645 struct radeon_uvd {
1646 struct radeon_bo *vcpu_bo;
1647 void *cpu_addr;
1648 uint64_t gpu_addr;
1649 void *saved_bo;
1650 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1651 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1652 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1653 struct delayed_work idle_work;
1654 };
1655
1656 int radeon_uvd_init(struct radeon_device *rdev);
1657 void radeon_uvd_fini(struct radeon_device *rdev);
1658 int radeon_uvd_suspend(struct radeon_device *rdev);
1659 int radeon_uvd_resume(struct radeon_device *rdev);
1660 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1661 uint32_t handle, struct radeon_fence **fence);
1662 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1663 uint32_t handle, struct radeon_fence **fence);
1664 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1665 uint32_t allowed_domains);
1666 void radeon_uvd_free_handles(struct radeon_device *rdev,
1667 struct drm_file *filp);
1668 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1669 void radeon_uvd_note_usage(struct radeon_device *rdev);
1670 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1671 unsigned vclk, unsigned dclk,
1672 unsigned vco_min, unsigned vco_max,
1673 unsigned fb_factor, unsigned fb_mask,
1674 unsigned pd_min, unsigned pd_max,
1675 unsigned pd_even,
1676 unsigned *optimal_fb_div,
1677 unsigned *optimal_vclk_div,
1678 unsigned *optimal_dclk_div);
1679 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1680 unsigned cg_upll_func_cntl);
1681
1682 /*
1683 * VCE
1684 */
1685 #define RADEON_MAX_VCE_HANDLES 16
1686 #define RADEON_VCE_STACK_SIZE (1024*1024)
1687 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1688
1689 struct radeon_vce {
1690 struct radeon_bo *vcpu_bo;
1691 uint64_t gpu_addr;
1692 unsigned fw_version;
1693 unsigned fb_version;
1694 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1695 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1696 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1697 struct delayed_work idle_work;
1698 };
1699
1700 int radeon_vce_init(struct radeon_device *rdev);
1701 void radeon_vce_fini(struct radeon_device *rdev);
1702 int radeon_vce_suspend(struct radeon_device *rdev);
1703 int radeon_vce_resume(struct radeon_device *rdev);
1704 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1705 uint32_t handle, struct radeon_fence **fence);
1706 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1707 uint32_t handle, struct radeon_fence **fence);
1708 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1709 void radeon_vce_note_usage(struct radeon_device *rdev);
1710 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1711 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1712 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1713 struct radeon_ring *ring,
1714 struct radeon_semaphore *semaphore,
1715 bool emit_wait);
1716 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1717 void radeon_vce_fence_emit(struct radeon_device *rdev,
1718 struct radeon_fence *fence);
1719 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1720 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1721
1722 struct r600_audio_pin {
1723 int channels;
1724 int rate;
1725 int bits_per_sample;
1726 u8 status_bits;
1727 u8 category_code;
1728 u32 offset;
1729 bool connected;
1730 u32 id;
1731 };
1732
1733 struct r600_audio {
1734 bool enabled;
1735 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1736 int num_pins;
1737 };
1738
1739 /*
1740 * Benchmarking
1741 */
1742 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1743
1744
1745 /*
1746 * Testing
1747 */
1748 void radeon_test_moves(struct radeon_device *rdev);
1749 void radeon_test_ring_sync(struct radeon_device *rdev,
1750 struct radeon_ring *cpA,
1751 struct radeon_ring *cpB);
1752 void radeon_test_syncing(struct radeon_device *rdev);
1753
1754 /*
1755 * MMU Notifier
1756 */
1757 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1758 void radeon_mn_unregister(struct radeon_bo *bo);
1759
1760 /*
1761 * Debugfs
1762 */
1763 struct radeon_debugfs {
1764 struct drm_info_list *files;
1765 unsigned num_files;
1766 };
1767
1768 int radeon_debugfs_add_files(struct radeon_device *rdev,
1769 struct drm_info_list *files,
1770 unsigned nfiles);
1771 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1772
1773 /*
1774 * ASIC ring specific functions.
1775 */
1776 struct radeon_asic_ring {
1777 /* ring read/write ptr handling */
1778 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1779 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1780 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1781
1782 /* validating and patching of IBs */
1783 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1784 int (*cs_parse)(struct radeon_cs_parser *p);
1785
1786 /* command emmit functions */
1787 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1788 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1789 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1790 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1791 struct radeon_semaphore *semaphore, bool emit_wait);
1792 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1793
1794 /* testing functions */
1795 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1796 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1797 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1798
1799 /* deprecated */
1800 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1801 };
1802
1803 /*
1804 * ASIC specific functions.
1805 */
1806 struct radeon_asic {
1807 int (*init)(struct radeon_device *rdev);
1808 void (*fini)(struct radeon_device *rdev);
1809 int (*resume)(struct radeon_device *rdev);
1810 int (*suspend)(struct radeon_device *rdev);
1811 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1812 int (*asic_reset)(struct radeon_device *rdev);
1813 /* Flush the HDP cache via MMIO */
1814 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1815 /* check if 3D engine is idle */
1816 bool (*gui_idle)(struct radeon_device *rdev);
1817 /* wait for mc_idle */
1818 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1819 /* get the reference clock */
1820 u32 (*get_xclk)(struct radeon_device *rdev);
1821 /* get the gpu clock counter */
1822 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1823 /* gart */
1824 struct {
1825 void (*tlb_flush)(struct radeon_device *rdev);
1826 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1827 void (*set_page)(struct radeon_device *rdev, unsigned i,
1828 uint64_t entry);
1829 } gart;
1830 struct {
1831 int (*init)(struct radeon_device *rdev);
1832 void (*fini)(struct radeon_device *rdev);
1833 void (*copy_pages)(struct radeon_device *rdev,
1834 struct radeon_ib *ib,
1835 uint64_t pe, uint64_t src,
1836 unsigned count);
1837 void (*write_pages)(struct radeon_device *rdev,
1838 struct radeon_ib *ib,
1839 uint64_t pe,
1840 uint64_t addr, unsigned count,
1841 uint32_t incr, uint32_t flags);
1842 void (*set_pages)(struct radeon_device *rdev,
1843 struct radeon_ib *ib,
1844 uint64_t pe,
1845 uint64_t addr, unsigned count,
1846 uint32_t incr, uint32_t flags);
1847 void (*pad_ib)(struct radeon_ib *ib);
1848 } vm;
1849 /* ring specific callbacks */
1850 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1851 /* irqs */
1852 struct {
1853 int (*set)(struct radeon_device *rdev);
1854 int (*process)(struct radeon_device *rdev);
1855 } irq;
1856 /* displays */
1857 struct {
1858 /* display watermarks */
1859 void (*bandwidth_update)(struct radeon_device *rdev);
1860 /* get frame count */
1861 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1862 /* wait for vblank */
1863 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1864 /* set backlight level */
1865 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1866 /* get backlight level */
1867 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1868 /* audio callbacks */
1869 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1870 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1871 } display;
1872 /* copy functions for bo handling */
1873 struct {
1874 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1875 uint64_t src_offset,
1876 uint64_t dst_offset,
1877 unsigned num_gpu_pages,
1878 struct reservation_object *resv);
1879 u32 blit_ring_index;
1880 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1881 uint64_t src_offset,
1882 uint64_t dst_offset,
1883 unsigned num_gpu_pages,
1884 struct reservation_object *resv);
1885 u32 dma_ring_index;
1886 /* method used for bo copy */
1887 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1888 uint64_t src_offset,
1889 uint64_t dst_offset,
1890 unsigned num_gpu_pages,
1891 struct reservation_object *resv);
1892 /* ring used for bo copies */
1893 u32 copy_ring_index;
1894 } copy;
1895 /* surfaces */
1896 struct {
1897 int (*set_reg)(struct radeon_device *rdev, int reg,
1898 uint32_t tiling_flags, uint32_t pitch,
1899 uint32_t offset, uint32_t obj_size);
1900 void (*clear_reg)(struct radeon_device *rdev, int reg);
1901 } surface;
1902 /* hotplug detect */
1903 struct {
1904 void (*init)(struct radeon_device *rdev);
1905 void (*fini)(struct radeon_device *rdev);
1906 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1907 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1908 } hpd;
1909 /* static power management */
1910 struct {
1911 void (*misc)(struct radeon_device *rdev);
1912 void (*prepare)(struct radeon_device *rdev);
1913 void (*finish)(struct radeon_device *rdev);
1914 void (*init_profile)(struct radeon_device *rdev);
1915 void (*get_dynpm_state)(struct radeon_device *rdev);
1916 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1917 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1918 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1919 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1920 int (*get_pcie_lanes)(struct radeon_device *rdev);
1921 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1922 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1923 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1924 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1925 int (*get_temperature)(struct radeon_device *rdev);
1926 } pm;
1927 /* dynamic power management */
1928 struct {
1929 int (*init)(struct radeon_device *rdev);
1930 void (*setup_asic)(struct radeon_device *rdev);
1931 int (*enable)(struct radeon_device *rdev);
1932 int (*late_enable)(struct radeon_device *rdev);
1933 void (*disable)(struct radeon_device *rdev);
1934 int (*pre_set_power_state)(struct radeon_device *rdev);
1935 int (*set_power_state)(struct radeon_device *rdev);
1936 void (*post_set_power_state)(struct radeon_device *rdev);
1937 void (*display_configuration_changed)(struct radeon_device *rdev);
1938 void (*fini)(struct radeon_device *rdev);
1939 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1940 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1941 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1942 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1943 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1944 bool (*vblank_too_short)(struct radeon_device *rdev);
1945 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1946 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1947 } dpm;
1948 /* pageflipping */
1949 struct {
1950 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1951 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1952 } pflip;
1953 };
1954
1955 /*
1956 * Asic structures
1957 */
1958 struct r100_asic {
1959 const unsigned *reg_safe_bm;
1960 unsigned reg_safe_bm_size;
1961 u32 hdp_cntl;
1962 };
1963
1964 struct r300_asic {
1965 const unsigned *reg_safe_bm;
1966 unsigned reg_safe_bm_size;
1967 u32 resync_scratch;
1968 u32 hdp_cntl;
1969 };
1970
1971 struct r600_asic {
1972 unsigned max_pipes;
1973 unsigned max_tile_pipes;
1974 unsigned max_simds;
1975 unsigned max_backends;
1976 unsigned max_gprs;
1977 unsigned max_threads;
1978 unsigned max_stack_entries;
1979 unsigned max_hw_contexts;
1980 unsigned max_gs_threads;
1981 unsigned sx_max_export_size;
1982 unsigned sx_max_export_pos_size;
1983 unsigned sx_max_export_smx_size;
1984 unsigned sq_num_cf_insts;
1985 unsigned tiling_nbanks;
1986 unsigned tiling_npipes;
1987 unsigned tiling_group_size;
1988 unsigned tile_config;
1989 unsigned backend_map;
1990 unsigned active_simds;
1991 };
1992
1993 struct rv770_asic {
1994 unsigned max_pipes;
1995 unsigned max_tile_pipes;
1996 unsigned max_simds;
1997 unsigned max_backends;
1998 unsigned max_gprs;
1999 unsigned max_threads;
2000 unsigned max_stack_entries;
2001 unsigned max_hw_contexts;
2002 unsigned max_gs_threads;
2003 unsigned sx_max_export_size;
2004 unsigned sx_max_export_pos_size;
2005 unsigned sx_max_export_smx_size;
2006 unsigned sq_num_cf_insts;
2007 unsigned sx_num_of_sets;
2008 unsigned sc_prim_fifo_size;
2009 unsigned sc_hiz_tile_fifo_size;
2010 unsigned sc_earlyz_tile_fifo_fize;
2011 unsigned tiling_nbanks;
2012 unsigned tiling_npipes;
2013 unsigned tiling_group_size;
2014 unsigned tile_config;
2015 unsigned backend_map;
2016 unsigned active_simds;
2017 };
2018
2019 struct evergreen_asic {
2020 unsigned num_ses;
2021 unsigned max_pipes;
2022 unsigned max_tile_pipes;
2023 unsigned max_simds;
2024 unsigned max_backends;
2025 unsigned max_gprs;
2026 unsigned max_threads;
2027 unsigned max_stack_entries;
2028 unsigned max_hw_contexts;
2029 unsigned max_gs_threads;
2030 unsigned sx_max_export_size;
2031 unsigned sx_max_export_pos_size;
2032 unsigned sx_max_export_smx_size;
2033 unsigned sq_num_cf_insts;
2034 unsigned sx_num_of_sets;
2035 unsigned sc_prim_fifo_size;
2036 unsigned sc_hiz_tile_fifo_size;
2037 unsigned sc_earlyz_tile_fifo_size;
2038 unsigned tiling_nbanks;
2039 unsigned tiling_npipes;
2040 unsigned tiling_group_size;
2041 unsigned tile_config;
2042 unsigned backend_map;
2043 unsigned active_simds;
2044 };
2045
2046 struct cayman_asic {
2047 unsigned max_shader_engines;
2048 unsigned max_pipes_per_simd;
2049 unsigned max_tile_pipes;
2050 unsigned max_simds_per_se;
2051 unsigned max_backends_per_se;
2052 unsigned max_texture_channel_caches;
2053 unsigned max_gprs;
2054 unsigned max_threads;
2055 unsigned max_gs_threads;
2056 unsigned max_stack_entries;
2057 unsigned sx_num_of_sets;
2058 unsigned sx_max_export_size;
2059 unsigned sx_max_export_pos_size;
2060 unsigned sx_max_export_smx_size;
2061 unsigned max_hw_contexts;
2062 unsigned sq_num_cf_insts;
2063 unsigned sc_prim_fifo_size;
2064 unsigned sc_hiz_tile_fifo_size;
2065 unsigned sc_earlyz_tile_fifo_size;
2066
2067 unsigned num_shader_engines;
2068 unsigned num_shader_pipes_per_simd;
2069 unsigned num_tile_pipes;
2070 unsigned num_simds_per_se;
2071 unsigned num_backends_per_se;
2072 unsigned backend_disable_mask_per_asic;
2073 unsigned backend_map;
2074 unsigned num_texture_channel_caches;
2075 unsigned mem_max_burst_length_bytes;
2076 unsigned mem_row_size_in_kb;
2077 unsigned shader_engine_tile_size;
2078 unsigned num_gpus;
2079 unsigned multi_gpu_tile_size;
2080
2081 unsigned tile_config;
2082 unsigned active_simds;
2083 };
2084
2085 struct si_asic {
2086 unsigned max_shader_engines;
2087 unsigned max_tile_pipes;
2088 unsigned max_cu_per_sh;
2089 unsigned max_sh_per_se;
2090 unsigned max_backends_per_se;
2091 unsigned max_texture_channel_caches;
2092 unsigned max_gprs;
2093 unsigned max_gs_threads;
2094 unsigned max_hw_contexts;
2095 unsigned sc_prim_fifo_size_frontend;
2096 unsigned sc_prim_fifo_size_backend;
2097 unsigned sc_hiz_tile_fifo_size;
2098 unsigned sc_earlyz_tile_fifo_size;
2099
2100 unsigned num_tile_pipes;
2101 unsigned backend_enable_mask;
2102 unsigned backend_disable_mask_per_asic;
2103 unsigned backend_map;
2104 unsigned num_texture_channel_caches;
2105 unsigned mem_max_burst_length_bytes;
2106 unsigned mem_row_size_in_kb;
2107 unsigned shader_engine_tile_size;
2108 unsigned num_gpus;
2109 unsigned multi_gpu_tile_size;
2110
2111 unsigned tile_config;
2112 uint32_t tile_mode_array[32];
2113 uint32_t active_cus;
2114 };
2115
2116 struct cik_asic {
2117 unsigned max_shader_engines;
2118 unsigned max_tile_pipes;
2119 unsigned max_cu_per_sh;
2120 unsigned max_sh_per_se;
2121 unsigned max_backends_per_se;
2122 unsigned max_texture_channel_caches;
2123 unsigned max_gprs;
2124 unsigned max_gs_threads;
2125 unsigned max_hw_contexts;
2126 unsigned sc_prim_fifo_size_frontend;
2127 unsigned sc_prim_fifo_size_backend;
2128 unsigned sc_hiz_tile_fifo_size;
2129 unsigned sc_earlyz_tile_fifo_size;
2130
2131 unsigned num_tile_pipes;
2132 unsigned backend_enable_mask;
2133 unsigned backend_disable_mask_per_asic;
2134 unsigned backend_map;
2135 unsigned num_texture_channel_caches;
2136 unsigned mem_max_burst_length_bytes;
2137 unsigned mem_row_size_in_kb;
2138 unsigned shader_engine_tile_size;
2139 unsigned num_gpus;
2140 unsigned multi_gpu_tile_size;
2141
2142 unsigned tile_config;
2143 uint32_t tile_mode_array[32];
2144 uint32_t macrotile_mode_array[16];
2145 uint32_t active_cus;
2146 };
2147
2148 union radeon_asic_config {
2149 struct r300_asic r300;
2150 struct r100_asic r100;
2151 struct r600_asic r600;
2152 struct rv770_asic rv770;
2153 struct evergreen_asic evergreen;
2154 struct cayman_asic cayman;
2155 struct si_asic si;
2156 struct cik_asic cik;
2157 };
2158
2159 /*
2160 * asic initizalization from radeon_asic.c
2161 */
2162 void radeon_agp_disable(struct radeon_device *rdev);
2163 int radeon_asic_init(struct radeon_device *rdev);
2164
2165
2166 /*
2167 * IOCTL.
2168 */
2169 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
2171 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *filp);
2173 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
2175 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *file_priv);
2177 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *file_priv);
2179 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2180 struct drm_file *file_priv);
2181 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2182 struct drm_file *file_priv);
2183 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2184 struct drm_file *filp);
2185 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2186 struct drm_file *filp);
2187 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2188 struct drm_file *filp);
2189 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2190 struct drm_file *filp);
2191 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2192 struct drm_file *filp);
2193 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2194 struct drm_file *filp);
2195 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2196 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2197 struct drm_file *filp);
2198 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2199 struct drm_file *filp);
2200
2201 /* VRAM scratch page for HDP bug, default vram page */
2202 struct r600_vram_scratch {
2203 struct radeon_bo *robj;
2204 volatile uint32_t *ptr;
2205 u64 gpu_addr;
2206 };
2207
2208 /*
2209 * ACPI
2210 */
2211 struct radeon_atif_notification_cfg {
2212 bool enabled;
2213 int command_code;
2214 };
2215
2216 struct radeon_atif_notifications {
2217 bool display_switch;
2218 bool expansion_mode_change;
2219 bool thermal_state;
2220 bool forced_power_state;
2221 bool system_power_state;
2222 bool display_conf_change;
2223 bool px_gfx_switch;
2224 bool brightness_change;
2225 bool dgpu_display_event;
2226 };
2227
2228 struct radeon_atif_functions {
2229 bool system_params;
2230 bool sbios_requests;
2231 bool select_active_disp;
2232 bool lid_state;
2233 bool get_tv_standard;
2234 bool set_tv_standard;
2235 bool get_panel_expansion_mode;
2236 bool set_panel_expansion_mode;
2237 bool temperature_change;
2238 bool graphics_device_types;
2239 };
2240
2241 struct radeon_atif {
2242 struct radeon_atif_notifications notifications;
2243 struct radeon_atif_functions functions;
2244 struct radeon_atif_notification_cfg notification_cfg;
2245 struct radeon_encoder *encoder_for_bl;
2246 };
2247
2248 struct radeon_atcs_functions {
2249 bool get_ext_state;
2250 bool pcie_perf_req;
2251 bool pcie_dev_rdy;
2252 bool pcie_bus_width;
2253 };
2254
2255 struct radeon_atcs {
2256 struct radeon_atcs_functions functions;
2257 };
2258
2259 /*
2260 * Core structure, functions and helpers.
2261 */
2262 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2263 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2264
2265 struct radeon_device {
2266 struct device *dev;
2267 struct drm_device *ddev;
2268 struct pci_dev *pdev;
2269 struct rw_semaphore exclusive_lock;
2270 /* ASIC */
2271 union radeon_asic_config config;
2272 enum radeon_family family;
2273 unsigned long flags;
2274 int usec_timeout;
2275 enum radeon_pll_errata pll_errata;
2276 int num_gb_pipes;
2277 int num_z_pipes;
2278 int disp_priority;
2279 /* BIOS */
2280 uint8_t *bios;
2281 bool is_atom_bios;
2282 uint16_t bios_header_start;
2283 struct radeon_bo *stollen_vga_memory;
2284 /* Register mmio */
2285 resource_size_t rmmio_base;
2286 resource_size_t rmmio_size;
2287 /* protects concurrent MM_INDEX/DATA based register access */
2288 spinlock_t mmio_idx_lock;
2289 /* protects concurrent SMC based register access */
2290 spinlock_t smc_idx_lock;
2291 /* protects concurrent PLL register access */
2292 spinlock_t pll_idx_lock;
2293 /* protects concurrent MC register access */
2294 spinlock_t mc_idx_lock;
2295 /* protects concurrent PCIE register access */
2296 spinlock_t pcie_idx_lock;
2297 /* protects concurrent PCIE_PORT register access */
2298 spinlock_t pciep_idx_lock;
2299 /* protects concurrent PIF register access */
2300 spinlock_t pif_idx_lock;
2301 /* protects concurrent CG register access */
2302 spinlock_t cg_idx_lock;
2303 /* protects concurrent UVD register access */
2304 spinlock_t uvd_idx_lock;
2305 /* protects concurrent RCU register access */
2306 spinlock_t rcu_idx_lock;
2307 /* protects concurrent DIDT register access */
2308 spinlock_t didt_idx_lock;
2309 /* protects concurrent ENDPOINT (audio) register access */
2310 spinlock_t end_idx_lock;
2311 void __iomem *rmmio;
2312 radeon_rreg_t mc_rreg;
2313 radeon_wreg_t mc_wreg;
2314 radeon_rreg_t pll_rreg;
2315 radeon_wreg_t pll_wreg;
2316 uint32_t pcie_reg_mask;
2317 radeon_rreg_t pciep_rreg;
2318 radeon_wreg_t pciep_wreg;
2319 /* io port */
2320 void __iomem *rio_mem;
2321 resource_size_t rio_mem_size;
2322 struct radeon_clock clock;
2323 struct radeon_mc mc;
2324 struct radeon_gart gart;
2325 struct radeon_mode_info mode_info;
2326 struct radeon_scratch scratch;
2327 struct radeon_doorbell doorbell;
2328 struct radeon_mman mman;
2329 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2330 wait_queue_head_t fence_queue;
2331 unsigned fence_context;
2332 struct mutex ring_lock;
2333 struct radeon_ring ring[RADEON_NUM_RINGS];
2334 bool ib_pool_ready;
2335 struct radeon_sa_manager ring_tmp_bo;
2336 struct radeon_irq irq;
2337 struct radeon_asic *asic;
2338 struct radeon_gem gem;
2339 struct radeon_pm pm;
2340 struct radeon_uvd uvd;
2341 struct radeon_vce vce;
2342 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2343 struct radeon_wb wb;
2344 struct radeon_dummy_page dummy_page;
2345 bool shutdown;
2346 bool suspend;
2347 bool need_dma32;
2348 bool accel_working;
2349 bool fastfb_working; /* IGP feature*/
2350 bool needs_reset, in_reset;
2351 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2352 const struct firmware *me_fw; /* all family ME firmware */
2353 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2354 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2355 const struct firmware *mc_fw; /* NI MC firmware */
2356 const struct firmware *ce_fw; /* SI CE firmware */
2357 const struct firmware *mec_fw; /* CIK MEC firmware */
2358 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2359 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2360 const struct firmware *smc_fw; /* SMC firmware */
2361 const struct firmware *uvd_fw; /* UVD firmware */
2362 const struct firmware *vce_fw; /* VCE firmware */
2363 bool new_fw;
2364 struct r600_vram_scratch vram_scratch;
2365 int msi_enabled; /* msi enabled */
2366 struct r600_ih ih; /* r6/700 interrupt ring */
2367 struct radeon_rlc rlc;
2368 struct radeon_mec mec;
2369 struct work_struct hotplug_work;
2370 struct work_struct audio_work;
2371 int num_crtc; /* number of crtcs */
2372 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2373 bool has_uvd;
2374 struct r600_audio audio; /* audio stuff */
2375 struct notifier_block acpi_nb;
2376 /* only one userspace can use Hyperz features or CMASK at a time */
2377 struct drm_file *hyperz_filp;
2378 struct drm_file *cmask_filp;
2379 /* i2c buses */
2380 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2381 /* debugfs */
2382 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2383 unsigned debugfs_count;
2384 /* virtual memory */
2385 struct radeon_vm_manager vm_manager;
2386 struct mutex gpu_clock_mutex;
2387 /* memory stats */
2388 atomic64_t vram_usage;
2389 atomic64_t gtt_usage;
2390 atomic64_t num_bytes_moved;
2391 /* ACPI interface */
2392 struct radeon_atif atif;
2393 struct radeon_atcs atcs;
2394 /* srbm instance registers */
2395 struct mutex srbm_mutex;
2396 /* clock, powergating flags */
2397 u32 cg_flags;
2398 u32 pg_flags;
2399
2400 struct dev_pm_domain vga_pm_domain;
2401 bool have_disp_power_ref;
2402 u32 px_quirk_flags;
2403
2404 /* tracking pinned memory */
2405 u64 vram_pin_size;
2406 u64 gart_pin_size;
2407
2408 struct mutex mn_lock;
2409 DECLARE_HASHTABLE(mn_hash, 7);
2410 };
2411
2412 bool radeon_is_px(struct drm_device *dev);
2413 int radeon_device_init(struct radeon_device *rdev,
2414 struct drm_device *ddev,
2415 struct pci_dev *pdev,
2416 uint32_t flags);
2417 void radeon_device_fini(struct radeon_device *rdev);
2418 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2419
2420 #define RADEON_MIN_MMIO_SIZE 0x10000
2421
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2422 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2423 bool always_indirect)
2424 {
2425 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2426 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2427 return readl(((void __iomem *)rdev->rmmio) + reg);
2428 else {
2429 unsigned long flags;
2430 uint32_t ret;
2431
2432 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2433 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2434 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2435 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2436
2437 return ret;
2438 }
2439 }
2440
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2441 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2442 bool always_indirect)
2443 {
2444 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2445 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2446 else {
2447 unsigned long flags;
2448
2449 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2450 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2451 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2452 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2453 }
2454 }
2455
2456 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2457 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2458
2459 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2460 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2461
2462 /*
2463 * Cast helper
2464 */
2465 extern const struct fence_ops radeon_fence_ops;
2466
to_radeon_fence(struct fence * f)2467 static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2468 {
2469 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2470
2471 if (__f->base.ops == &radeon_fence_ops)
2472 return __f;
2473
2474 return NULL;
2475 }
2476
2477 /*
2478 * Registers read & write functions.
2479 */
2480 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2481 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2482 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2483 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2484 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2485 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2486 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2487 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2488 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2489 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2490 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2491 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2492 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2493 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2494 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2495 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2496 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2497 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2498 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2499 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2500 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2501 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2502 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2503 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2504 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2505 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2506 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2507 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2508 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2509 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2510 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2511 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2512 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2513 #define WREG32_P(reg, val, mask) \
2514 do { \
2515 uint32_t tmp_ = RREG32(reg); \
2516 tmp_ &= (mask); \
2517 tmp_ |= ((val) & ~(mask)); \
2518 WREG32(reg, tmp_); \
2519 } while (0)
2520 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2521 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2522 #define WREG32_PLL_P(reg, val, mask) \
2523 do { \
2524 uint32_t tmp_ = RREG32_PLL(reg); \
2525 tmp_ &= (mask); \
2526 tmp_ |= ((val) & ~(mask)); \
2527 WREG32_PLL(reg, tmp_); \
2528 } while (0)
2529 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2530 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2531 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2532
2533 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2534 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2535
2536 /*
2537 * Indirect registers accessor
2538 */
rv370_pcie_rreg(struct radeon_device * rdev,uint32_t reg)2539 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2540 {
2541 unsigned long flags;
2542 uint32_t r;
2543
2544 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2545 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2546 r = RREG32(RADEON_PCIE_DATA);
2547 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2548 return r;
2549 }
2550
rv370_pcie_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)2551 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2552 {
2553 unsigned long flags;
2554
2555 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2556 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2557 WREG32(RADEON_PCIE_DATA, (v));
2558 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2559 }
2560
tn_smc_rreg(struct radeon_device * rdev,u32 reg)2561 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2562 {
2563 unsigned long flags;
2564 u32 r;
2565
2566 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2567 WREG32(TN_SMC_IND_INDEX_0, (reg));
2568 r = RREG32(TN_SMC_IND_DATA_0);
2569 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2570 return r;
2571 }
2572
tn_smc_wreg(struct radeon_device * rdev,u32 reg,u32 v)2573 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2574 {
2575 unsigned long flags;
2576
2577 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2578 WREG32(TN_SMC_IND_INDEX_0, (reg));
2579 WREG32(TN_SMC_IND_DATA_0, (v));
2580 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2581 }
2582
r600_rcu_rreg(struct radeon_device * rdev,u32 reg)2583 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2584 {
2585 unsigned long flags;
2586 u32 r;
2587
2588 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2589 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2590 r = RREG32(R600_RCU_DATA);
2591 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2592 return r;
2593 }
2594
r600_rcu_wreg(struct radeon_device * rdev,u32 reg,u32 v)2595 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2596 {
2597 unsigned long flags;
2598
2599 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2600 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2601 WREG32(R600_RCU_DATA, (v));
2602 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2603 }
2604
eg_cg_rreg(struct radeon_device * rdev,u32 reg)2605 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2606 {
2607 unsigned long flags;
2608 u32 r;
2609
2610 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2611 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2612 r = RREG32(EVERGREEN_CG_IND_DATA);
2613 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2614 return r;
2615 }
2616
eg_cg_wreg(struct radeon_device * rdev,u32 reg,u32 v)2617 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2618 {
2619 unsigned long flags;
2620
2621 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2622 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2623 WREG32(EVERGREEN_CG_IND_DATA, (v));
2624 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2625 }
2626
eg_pif_phy0_rreg(struct radeon_device * rdev,u32 reg)2627 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2628 {
2629 unsigned long flags;
2630 u32 r;
2631
2632 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2633 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2634 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2635 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2636 return r;
2637 }
2638
eg_pif_phy0_wreg(struct radeon_device * rdev,u32 reg,u32 v)2639 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2640 {
2641 unsigned long flags;
2642
2643 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2644 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2645 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2646 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2647 }
2648
eg_pif_phy1_rreg(struct radeon_device * rdev,u32 reg)2649 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2650 {
2651 unsigned long flags;
2652 u32 r;
2653
2654 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2655 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2656 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2657 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2658 return r;
2659 }
2660
eg_pif_phy1_wreg(struct radeon_device * rdev,u32 reg,u32 v)2661 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2662 {
2663 unsigned long flags;
2664
2665 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2666 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2667 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2668 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2669 }
2670
r600_uvd_ctx_rreg(struct radeon_device * rdev,u32 reg)2671 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2672 {
2673 unsigned long flags;
2674 u32 r;
2675
2676 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2677 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2678 r = RREG32(R600_UVD_CTX_DATA);
2679 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2680 return r;
2681 }
2682
r600_uvd_ctx_wreg(struct radeon_device * rdev,u32 reg,u32 v)2683 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2684 {
2685 unsigned long flags;
2686
2687 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2688 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2689 WREG32(R600_UVD_CTX_DATA, (v));
2690 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2691 }
2692
2693
cik_didt_rreg(struct radeon_device * rdev,u32 reg)2694 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2695 {
2696 unsigned long flags;
2697 u32 r;
2698
2699 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2700 WREG32(CIK_DIDT_IND_INDEX, (reg));
2701 r = RREG32(CIK_DIDT_IND_DATA);
2702 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2703 return r;
2704 }
2705
cik_didt_wreg(struct radeon_device * rdev,u32 reg,u32 v)2706 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2707 {
2708 unsigned long flags;
2709
2710 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2711 WREG32(CIK_DIDT_IND_INDEX, (reg));
2712 WREG32(CIK_DIDT_IND_DATA, (v));
2713 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2714 }
2715
2716 void r100_pll_errata_after_index(struct radeon_device *rdev);
2717
2718
2719 /*
2720 * ASICs helpers.
2721 */
2722 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2723 (rdev->pdev->device == 0x5969))
2724 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2725 (rdev->family == CHIP_RV200) || \
2726 (rdev->family == CHIP_RS100) || \
2727 (rdev->family == CHIP_RS200) || \
2728 (rdev->family == CHIP_RV250) || \
2729 (rdev->family == CHIP_RV280) || \
2730 (rdev->family == CHIP_RS300))
2731 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2732 (rdev->family == CHIP_RV350) || \
2733 (rdev->family == CHIP_R350) || \
2734 (rdev->family == CHIP_RV380) || \
2735 (rdev->family == CHIP_R420) || \
2736 (rdev->family == CHIP_R423) || \
2737 (rdev->family == CHIP_RV410) || \
2738 (rdev->family == CHIP_RS400) || \
2739 (rdev->family == CHIP_RS480))
2740 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2741 (rdev->ddev->pdev->device == 0x9443) || \
2742 (rdev->ddev->pdev->device == 0x944B) || \
2743 (rdev->ddev->pdev->device == 0x9506) || \
2744 (rdev->ddev->pdev->device == 0x9509) || \
2745 (rdev->ddev->pdev->device == 0x950F) || \
2746 (rdev->ddev->pdev->device == 0x689C) || \
2747 (rdev->ddev->pdev->device == 0x689D))
2748 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2749 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2750 (rdev->family == CHIP_RS690) || \
2751 (rdev->family == CHIP_RS740) || \
2752 (rdev->family >= CHIP_R600))
2753 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2754 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2755 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2756 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2757 (rdev->flags & RADEON_IS_IGP))
2758 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2759 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2760 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2761 (rdev->flags & RADEON_IS_IGP))
2762 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2763 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2764 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2765 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2766 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2767 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2768 (rdev->family == CHIP_MULLINS))
2769
2770 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2771 (rdev->ddev->pdev->device == 0x6850) || \
2772 (rdev->ddev->pdev->device == 0x6858) || \
2773 (rdev->ddev->pdev->device == 0x6859) || \
2774 (rdev->ddev->pdev->device == 0x6840) || \
2775 (rdev->ddev->pdev->device == 0x6841) || \
2776 (rdev->ddev->pdev->device == 0x6842) || \
2777 (rdev->ddev->pdev->device == 0x6843))
2778
2779 /*
2780 * BIOS helpers.
2781 */
2782 #define RBIOS8(i) (rdev->bios[i])
2783 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2784 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2785
2786 int radeon_combios_init(struct radeon_device *rdev);
2787 void radeon_combios_fini(struct radeon_device *rdev);
2788 int radeon_atombios_init(struct radeon_device *rdev);
2789 void radeon_atombios_fini(struct radeon_device *rdev);
2790
2791
2792 /*
2793 * RING helpers.
2794 */
2795
2796 /**
2797 * radeon_ring_write - write a value to the ring
2798 *
2799 * @ring: radeon_ring structure holding ring information
2800 * @v: dword (dw) value to write
2801 *
2802 * Write a value to the requested ring buffer (all asics).
2803 */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2804 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2805 {
2806 if (ring->count_dw <= 0)
2807 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2808
2809 ring->ring[ring->wptr++] = v;
2810 ring->wptr &= ring->ptr_mask;
2811 ring->count_dw--;
2812 ring->ring_free_dw--;
2813 }
2814
2815 /*
2816 * ASICs macro.
2817 */
2818 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2819 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2820 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2821 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2822 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2823 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2824 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2825 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2826 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2827 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2828 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2829 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2830 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2831 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2832 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2833 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2834 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2835 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2836 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2837 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2838 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2839 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2840 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2841 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2842 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2843 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2844 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2845 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2846 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2847 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2848 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2849 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2850 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2851 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2852 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2853 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2854 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2855 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2856 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2857 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2858 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2859 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2860 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2861 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2862 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2863 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2864 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2865 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2866 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2867 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2868 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2869 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2870 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2871 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2872 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2873 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2874 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2875 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2876 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2877 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2878 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2879 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2880 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2881 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2882 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2883 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2884 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2885 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2886 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2887 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2888 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2889 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2890 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2891 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2892 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2893 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2894 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2895 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2896 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2897 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2898 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2899 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2900 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2901 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2902 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2903 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2904 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2905 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2906
2907 /* Common functions */
2908 /* AGP */
2909 extern int radeon_gpu_reset(struct radeon_device *rdev);
2910 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2911 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2912 extern void radeon_agp_disable(struct radeon_device *rdev);
2913 extern int radeon_modeset_init(struct radeon_device *rdev);
2914 extern void radeon_modeset_fini(struct radeon_device *rdev);
2915 extern bool radeon_card_posted(struct radeon_device *rdev);
2916 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2917 extern void radeon_update_display_priority(struct radeon_device *rdev);
2918 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2919 extern void radeon_scratch_init(struct radeon_device *rdev);
2920 extern void radeon_wb_fini(struct radeon_device *rdev);
2921 extern int radeon_wb_init(struct radeon_device *rdev);
2922 extern void radeon_wb_disable(struct radeon_device *rdev);
2923 extern void radeon_surface_init(struct radeon_device *rdev);
2924 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2925 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2926 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2927 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2928 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2929 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2930 uint32_t flags);
2931 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2932 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2933 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2934 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2935 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2936 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2937 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2938 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2939 const u32 *registers,
2940 const u32 array_size);
2941
2942 /*
2943 * vm
2944 */
2945 int radeon_vm_manager_init(struct radeon_device *rdev);
2946 void radeon_vm_manager_fini(struct radeon_device *rdev);
2947 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2948 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2949 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2950 struct radeon_vm *vm,
2951 struct list_head *head);
2952 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2953 struct radeon_vm *vm, int ring);
2954 void radeon_vm_flush(struct radeon_device *rdev,
2955 struct radeon_vm *vm,
2956 int ring);
2957 void radeon_vm_fence(struct radeon_device *rdev,
2958 struct radeon_vm *vm,
2959 struct radeon_fence *fence);
2960 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2961 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2962 struct radeon_vm *vm);
2963 int radeon_vm_clear_freed(struct radeon_device *rdev,
2964 struct radeon_vm *vm);
2965 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2966 struct radeon_vm *vm);
2967 int radeon_vm_bo_update(struct radeon_device *rdev,
2968 struct radeon_bo_va *bo_va,
2969 struct ttm_mem_reg *mem);
2970 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2971 struct radeon_bo *bo);
2972 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2973 struct radeon_bo *bo);
2974 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2975 struct radeon_vm *vm,
2976 struct radeon_bo *bo);
2977 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2978 struct radeon_bo_va *bo_va,
2979 uint64_t offset,
2980 uint32_t flags);
2981 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2982 struct radeon_bo_va *bo_va);
2983
2984 /* audio */
2985 void r600_audio_update_hdmi(struct work_struct *work);
2986 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2987 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2988 void r600_audio_enable(struct radeon_device *rdev,
2989 struct r600_audio_pin *pin,
2990 u8 enable_mask);
2991 void dce6_audio_enable(struct radeon_device *rdev,
2992 struct r600_audio_pin *pin,
2993 u8 enable_mask);
2994
2995 /*
2996 * R600 vram scratch functions
2997 */
2998 int r600_vram_scratch_init(struct radeon_device *rdev);
2999 void r600_vram_scratch_fini(struct radeon_device *rdev);
3000
3001 /*
3002 * r600 cs checking helper
3003 */
3004 unsigned r600_mip_minify(unsigned size, unsigned level);
3005 bool r600_fmt_is_valid_color(u32 format);
3006 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3007 int r600_fmt_get_blocksize(u32 format);
3008 int r600_fmt_get_nblocksx(u32 format, u32 w);
3009 int r600_fmt_get_nblocksy(u32 format, u32 h);
3010
3011 /*
3012 * r600 functions used by radeon_encoder.c
3013 */
3014 struct radeon_hdmi_acr {
3015 u32 clock;
3016
3017 int n_32khz;
3018 int cts_32khz;
3019
3020 int n_44_1khz;
3021 int cts_44_1khz;
3022
3023 int n_48khz;
3024 int cts_48khz;
3025
3026 };
3027
3028 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3029
3030 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3031 u32 tiling_pipe_num,
3032 u32 max_rb_num,
3033 u32 total_max_rb_num,
3034 u32 enabled_rb_mask);
3035
3036 /*
3037 * evergreen functions used by radeon_encoder.c
3038 */
3039
3040 extern int ni_init_microcode(struct radeon_device *rdev);
3041 extern int ni_mc_load_microcode(struct radeon_device *rdev);
3042
3043 /* radeon_acpi.c */
3044 #if defined(CONFIG_ACPI)
3045 extern int radeon_acpi_init(struct radeon_device *rdev);
3046 extern void radeon_acpi_fini(struct radeon_device *rdev);
3047 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3048 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
3049 u8 perf_req, bool advertise);
3050 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
3051 #else
radeon_acpi_init(struct radeon_device * rdev)3052 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)3053 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3054 #endif
3055
3056 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3057 struct radeon_cs_packet *pkt,
3058 unsigned idx);
3059 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3060 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3061 struct radeon_cs_packet *pkt);
3062 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3063 struct radeon_cs_reloc **cs_reloc,
3064 int nomm);
3065 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3066 uint32_t *vline_start_end,
3067 uint32_t *vline_status);
3068
3069 #include "radeon_object.h"
3070
3071 #endif
3072