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1 /* Defines for using and allocating dma channels. */
2 
3 #ifndef _ASM_ARCH_DMA_H
4 #define _ASM_ARCH_DMA_H
5 
6 #define MAX_DMA_CHANNELS	10
7 
8 /* dma0 and dma1 used for network (ethernet) */
9 #define NETWORK_TX_DMA_NBR 0
10 #define NETWORK_RX_DMA_NBR 1
11 
12 /* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
13 #define PAR0_TX_DMA_NBR 2
14 #define PAR0_RX_DMA_NBR 3
15 #define SCSI0_TX_DMA_NBR 2
16 #define SCSI0_RX_DMA_NBR 3
17 #define SER2_TX_DMA_NBR 2
18 #define SER2_RX_DMA_NBR 3
19 #define ATA_TX_DMA_NBR 2
20 #define ATA_RX_DMA_NBR 3
21 
22 /* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
23 #define PAR1_TX_DMA_NBR 4
24 #define PAR1_RX_DMA_NBR 5
25 #define SCSI1_TX_DMA_NBR 4
26 #define SCSI1_RX_DMA_NBR 5
27 #define SER3_TX_DMA_NBR 4
28 #define SER3_RX_DMA_NBR 5
29 #define EXTDMA0_TX_DMA_NBR 4
30 #define EXTDMA0_RX_DMA_NBR 5
31 
32 /* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
33 #define SER0_TX_DMA_NBR 6
34 #define SER0_RX_DMA_NBR 7
35 #define EXTDMA1_TX_DMA_NBR 6
36 #define EXTDMA1_RX_DMA_NBR 7
37 #define MEM2MEM_TX_DMA_NBR 6
38 #define MEM2MEM_RX_DMA_NBR 7
39 
40 /* dma8 and dma9 shared by ser1 and usb */
41 #define SER1_TX_DMA_NBR 8
42 #define SER1_RX_DMA_NBR 9
43 #define USB_TX_DMA_NBR 8
44 #define USB_RX_DMA_NBR 9
45 
46 #endif
47 
48 enum dma_owner
49 {
50   dma_eth,
51   dma_ser0,
52   dma_ser1, /* Async and sync */
53   dma_ser2,
54   dma_ser3, /* Async and sync */
55   dma_ata,
56   dma_par0,
57   dma_par1,
58   dma_ext0,
59   dma_ext1,
60   dma_int6,
61   dma_int7,
62   dma_usb,
63   dma_scsi0,
64   dma_scsi1
65 };
66 
67 /* Masks used by cris_request_dma options: */
68 #define DMA_VERBOSE_ON_ERROR    (1<<0)
69 #define DMA_PANIC_ON_ERROR     ((1<<1)|DMA_VERBOSE_ON_ERROR)
70 
71 int cris_request_dma(unsigned int dmanr, const char * device_id,
72                      unsigned options, enum dma_owner owner);
73 
74 void cris_free_dma(unsigned int dmanr, const char * device_id);
75