1 #ifndef __MACH_MOTHERBOARD_H 2 #define __MACH_MOTHERBOARD_H 3 4 /* 5 * Physical addresses, offset from V2M_PA_CS0-3 6 */ 7 #define V2M_NOR0 (V2M_PA_CS0) 8 #define V2M_NOR1 (V2M_PA_CS1) 9 #define V2M_SRAM (V2M_PA_CS2) 10 #define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) 11 #define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) 12 #define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) 13 14 /* 15 * Physical addresses, offset from V2M_PA_CS7 16 */ 17 #define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000) 18 #define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000) 19 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000) 20 21 #define V2M_AACI (V2M_PA_CS7 + 0x00004000) 22 #define V2M_MMCI (V2M_PA_CS7 + 0x00005000) 23 #define V2M_KMI0 (V2M_PA_CS7 + 0x00006000) 24 #define V2M_KMI1 (V2M_PA_CS7 + 0x00007000) 25 26 #define V2M_UART0 (V2M_PA_CS7 + 0x00009000) 27 #define V2M_UART1 (V2M_PA_CS7 + 0x0000a000) 28 #define V2M_UART2 (V2M_PA_CS7 + 0x0000b000) 29 #define V2M_UART3 (V2M_PA_CS7 + 0x0000c000) 30 31 #define V2M_WDT (V2M_PA_CS7 + 0x0000f000) 32 33 #define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000) 34 #define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000) 35 36 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000) 37 #define V2M_RTC (V2M_PA_CS7 + 0x00017000) 38 39 #define V2M_CF (V2M_PA_CS7 + 0x0001a000) 40 #define V2M_CLCD (V2M_PA_CS7 + 0x0001f000) 41 42 43 /* 44 * Interrupts. Those in {} are for AMBA devices 45 */ 46 #define IRQ_V2M_WDT { (32 + 0) } 47 #define IRQ_V2M_TIMER0 (32 + 2) 48 #define IRQ_V2M_TIMER1 (32 + 2) 49 #define IRQ_V2M_TIMER2 (32 + 3) 50 #define IRQ_V2M_TIMER3 (32 + 3) 51 #define IRQ_V2M_RTC { (32 + 4) } 52 #define IRQ_V2M_UART0 { (32 + 5) } 53 #define IRQ_V2M_UART1 { (32 + 6) } 54 #define IRQ_V2M_UART2 { (32 + 7) } 55 #define IRQ_V2M_UART3 { (32 + 8) } 56 #define IRQ_V2M_MMCI { (32 + 9), (32 + 10) } 57 #define IRQ_V2M_AACI { (32 + 11) } 58 #define IRQ_V2M_KMI0 { (32 + 12) } 59 #define IRQ_V2M_KMI1 { (32 + 13) } 60 #define IRQ_V2M_CLCD { (32 + 14) } 61 #define IRQ_V2M_LAN9118 (32 + 15) 62 #define IRQ_V2M_ISP1761 (32 + 16) 63 #define IRQ_V2M_PCIE (32 + 17) 64 65 66 /* 67 * Core tile IDs 68 */ 69 #define V2M_CT_ID_CA9 0x0c000191 70 #define V2M_CT_ID_UNSUPPORTED 0xff000191 71 #define V2M_CT_ID_MASK 0xff000fff 72 73 struct ct_desc { 74 u32 id; 75 const char *name; 76 void (*map_io)(void); 77 void (*init_early)(void); 78 void (*init_irq)(void); 79 void (*init_tile)(void); 80 #ifdef CONFIG_SMP 81 void (*init_cpu_map)(void); 82 void (*smp_enable)(unsigned int); 83 #endif 84 }; 85 86 extern struct ct_desc *ct_desc; 87 88 #endif 89