1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11 #ifndef _ASM_S390_PGTABLE_H
12 #define _ASM_S390_PGTABLE_H
13
14 /*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29 #ifndef __ASSEMBLY__
30 #include <linux/sched.h>
31 #include <linux/mm_types.h>
32 #include <linux/page-flags.h>
33 #include <linux/radix-tree.h>
34 #include <asm/bug.h>
35 #include <asm/page.h>
36
37 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
38 extern void paging_init(void);
39 extern void vmem_map_init(void);
40
41 /*
42 * The S390 doesn't have any external MMU info: the kernel page
43 * tables contain all the necessary information.
44 */
45 #define update_mmu_cache(vma, address, ptep) do { } while (0)
46 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
47
48 /*
49 * ZERO_PAGE is a global shared page that is always zero; used
50 * for zero-mapped memory areas etc..
51 */
52
53 extern unsigned long empty_zero_page;
54 extern unsigned long zero_page_mask;
55
56 #define ZERO_PAGE(vaddr) \
57 (virt_to_page((void *)(empty_zero_page + \
58 (((unsigned long)(vaddr)) &zero_page_mask))))
59 #define __HAVE_COLOR_ZERO_PAGE
60
61 /* TODO: s390 cannot support io_remap_pfn_range... */
62 #endif /* !__ASSEMBLY__ */
63
64 /*
65 * PMD_SHIFT determines the size of the area a second-level page
66 * table can map
67 * PGDIR_SHIFT determines what a third-level page table entry can map
68 */
69 #ifndef CONFIG_64BIT
70 # define PMD_SHIFT 20
71 # define PUD_SHIFT 20
72 # define PGDIR_SHIFT 20
73 #else /* CONFIG_64BIT */
74 # define PMD_SHIFT 20
75 # define PUD_SHIFT 31
76 # define PGDIR_SHIFT 42
77 #endif /* CONFIG_64BIT */
78
79 #define PMD_SIZE (1UL << PMD_SHIFT)
80 #define PMD_MASK (~(PMD_SIZE-1))
81 #define PUD_SIZE (1UL << PUD_SHIFT)
82 #define PUD_MASK (~(PUD_SIZE-1))
83 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
84 #define PGDIR_MASK (~(PGDIR_SIZE-1))
85
86 /*
87 * entries per page directory level: the S390 is two-level, so
88 * we don't really have any PMD directory physically.
89 * for S390 segment-table entries are combined to one PGD
90 * that leads to 1024 pte per pgd
91 */
92 #define PTRS_PER_PTE 256
93 #ifndef CONFIG_64BIT
94 #define PTRS_PER_PMD 1
95 #define PTRS_PER_PUD 1
96 #else /* CONFIG_64BIT */
97 #define PTRS_PER_PMD 2048
98 #define PTRS_PER_PUD 2048
99 #endif /* CONFIG_64BIT */
100 #define PTRS_PER_PGD 2048
101
102 #define FIRST_USER_ADDRESS 0
103
104 #define pte_ERROR(e) \
105 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
106 #define pmd_ERROR(e) \
107 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
108 #define pud_ERROR(e) \
109 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
110 #define pgd_ERROR(e) \
111 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
112
113 #ifndef __ASSEMBLY__
114 /*
115 * The vmalloc and module area will always be on the topmost area of the kernel
116 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
117 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
118 * modules will reside. That makes sure that inter module branches always
119 * happen without trampolines and in addition the placement within a 2GB frame
120 * is branch prediction unit friendly.
121 */
122 extern unsigned long VMALLOC_START;
123 extern unsigned long VMALLOC_END;
124 extern struct page *vmemmap;
125
126 #define VMEM_MAX_PHYS ((unsigned long) vmemmap)
127
128 #ifdef CONFIG_64BIT
129 extern unsigned long MODULES_VADDR;
130 extern unsigned long MODULES_END;
131 #define MODULES_VADDR MODULES_VADDR
132 #define MODULES_END MODULES_END
133 #define MODULES_LEN (1UL << 31)
134 #endif
135
136 /*
137 * A 31 bit pagetable entry of S390 has following format:
138 * | PFRA | | OS |
139 * 0 0IP0
140 * 00000000001111111111222222222233
141 * 01234567890123456789012345678901
142 *
143 * I Page-Invalid Bit: Page is not available for address-translation
144 * P Page-Protection Bit: Store access not possible for page
145 *
146 * A 31 bit segmenttable entry of S390 has following format:
147 * | P-table origin | |PTL
148 * 0 IC
149 * 00000000001111111111222222222233
150 * 01234567890123456789012345678901
151 *
152 * I Segment-Invalid Bit: Segment is not available for address-translation
153 * C Common-Segment Bit: Segment is not private (PoP 3-30)
154 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
155 *
156 * The 31 bit segmenttable origin of S390 has following format:
157 *
158 * |S-table origin | | STL |
159 * X **GPS
160 * 00000000001111111111222222222233
161 * 01234567890123456789012345678901
162 *
163 * X Space-Switch event:
164 * G Segment-Invalid Bit: *
165 * P Private-Space Bit: Segment is not private (PoP 3-30)
166 * S Storage-Alteration:
167 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
168 *
169 * A 64 bit pagetable entry of S390 has following format:
170 * | PFRA |0IPC| OS |
171 * 0000000000111111111122222222223333333333444444444455555555556666
172 * 0123456789012345678901234567890123456789012345678901234567890123
173 *
174 * I Page-Invalid Bit: Page is not available for address-translation
175 * P Page-Protection Bit: Store access not possible for page
176 * C Change-bit override: HW is not required to set change bit
177 *
178 * A 64 bit segmenttable entry of S390 has following format:
179 * | P-table origin | TT
180 * 0000000000111111111122222222223333333333444444444455555555556666
181 * 0123456789012345678901234567890123456789012345678901234567890123
182 *
183 * I Segment-Invalid Bit: Segment is not available for address-translation
184 * C Common-Segment Bit: Segment is not private (PoP 3-30)
185 * P Page-Protection Bit: Store access not possible for page
186 * TT Type 00
187 *
188 * A 64 bit region table entry of S390 has following format:
189 * | S-table origin | TF TTTL
190 * 0000000000111111111122222222223333333333444444444455555555556666
191 * 0123456789012345678901234567890123456789012345678901234567890123
192 *
193 * I Segment-Invalid Bit: Segment is not available for address-translation
194 * TT Type 01
195 * TF
196 * TL Table length
197 *
198 * The 64 bit regiontable origin of S390 has following format:
199 * | region table origon | DTTL
200 * 0000000000111111111122222222223333333333444444444455555555556666
201 * 0123456789012345678901234567890123456789012345678901234567890123
202 *
203 * X Space-Switch event:
204 * G Segment-Invalid Bit:
205 * P Private-Space Bit:
206 * S Storage-Alteration:
207 * R Real space
208 * TL Table-Length:
209 *
210 * A storage key has the following format:
211 * | ACC |F|R|C|0|
212 * 0 3 4 5 6 7
213 * ACC: access key
214 * F : fetch protection bit
215 * R : referenced bit
216 * C : changed bit
217 */
218
219 /* Hardware bits in the page table entry */
220 #define _PAGE_PROTECT 0x200 /* HW read-only bit */
221 #define _PAGE_INVALID 0x400 /* HW invalid bit */
222 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
223
224 /* Software bits in the page table entry */
225 #define _PAGE_PRESENT 0x001 /* SW pte present bit */
226 #define _PAGE_TYPE 0x002 /* SW pte type bit */
227 #define _PAGE_YOUNG 0x004 /* SW pte young bit */
228 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
229 #define _PAGE_READ 0x010 /* SW pte read bit */
230 #define _PAGE_WRITE 0x020 /* SW pte write bit */
231 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */
232 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
233 #define __HAVE_ARCH_PTE_SPECIAL
234
235 /* Set of bits not changed in pte_modify */
236 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
237 _PAGE_YOUNG)
238
239 /*
240 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
241 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
242 * is used to distinguish present from not-present ptes. It is changed only
243 * with the page table lock held.
244 *
245 * The following table gives the different possible bit combinations for
246 * the pte hardware and software bits in the last 12 bits of a pte:
247 *
248 * 842100000000
249 * 000084210000
250 * 000000008421
251 * .IR...wrdytp
252 * empty .10...000000
253 * swap .10...xxxx10
254 * file .11...xxxxx0
255 * prot-none, clean, old .11...000001
256 * prot-none, clean, young .11...000101
257 * prot-none, dirty, old .10...001001
258 * prot-none, dirty, young .10...001101
259 * read-only, clean, old .11...010001
260 * read-only, clean, young .01...010101
261 * read-only, dirty, old .11...011001
262 * read-only, dirty, young .01...011101
263 * read-write, clean, old .11...110001
264 * read-write, clean, young .01...110101
265 * read-write, dirty, old .10...111001
266 * read-write, dirty, young .00...111101
267 *
268 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
269 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
270 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
271 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
272 */
273
274 #ifndef CONFIG_64BIT
275
276 /* Bits in the segment table address-space-control-element */
277 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
278 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
279 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
280 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
281 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
282
283 /* Bits in the segment table entry */
284 #define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */
285 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
286 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
287 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
288 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
290
291 #define _SEGMENT_ENTRY_DIRTY 0 /* No sw dirty bit for 31-bit */
292 #define _SEGMENT_ENTRY_YOUNG 0 /* No sw young bit for 31-bit */
293 #define _SEGMENT_ENTRY_READ 0 /* No sw read bit for 31-bit */
294 #define _SEGMENT_ENTRY_WRITE 0 /* No sw write bit for 31-bit */
295 #define _SEGMENT_ENTRY_LARGE 0 /* No large pages for 31-bit */
296 #define _SEGMENT_ENTRY_BITS_LARGE 0
297 #define _SEGMENT_ENTRY_ORIGIN_LARGE 0
298
299 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
300 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
301
302 /*
303 * Segment table entry encoding (I = invalid, R = read-only bit):
304 * ..R...I.....
305 * prot-none ..1...1.....
306 * read-only ..1...0.....
307 * read-write ..0...0.....
308 * empty ..0...1.....
309 */
310
311 /* Page status table bits for virtualization */
312 #define PGSTE_ACC_BITS 0xf0000000UL
313 #define PGSTE_FP_BIT 0x08000000UL
314 #define PGSTE_PCL_BIT 0x00800000UL
315 #define PGSTE_HR_BIT 0x00400000UL
316 #define PGSTE_HC_BIT 0x00200000UL
317 #define PGSTE_GR_BIT 0x00040000UL
318 #define PGSTE_GC_BIT 0x00020000UL
319 #define PGSTE_UC_BIT 0x00008000UL /* user dirty (migration) */
320 #define PGSTE_IN_BIT 0x00004000UL /* IPTE notify bit */
321
322 #else /* CONFIG_64BIT */
323
324 /* Bits in the segment/region table address-space-control-element */
325 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
326 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
327 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
328 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
329 #define _ASCE_REAL_SPACE 0x20 /* real space control */
330 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
331 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
332 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
333 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
334 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
335 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
336
337 /* Bits in the region table entry */
338 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
339 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
340 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
341 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
342 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
343 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
344 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
345 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
346
347 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
348 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
349 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
350 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
351 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
352 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
353
354 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
355 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */
356
357 /* Bits in the segment table entry */
358 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
359 #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL
360 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
361 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
362 #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
363 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
364
365 #define _SEGMENT_ENTRY (0)
366 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
367
368 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
369 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
370 #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */
371 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
372 #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */
373 #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */
374
375 /*
376 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
377 * dy..R...I...wr
378 * prot-none, clean, old 00..1...1...00
379 * prot-none, clean, young 01..1...1...00
380 * prot-none, dirty, old 10..1...1...00
381 * prot-none, dirty, young 11..1...1...00
382 * read-only, clean, old 00..1...1...01
383 * read-only, clean, young 01..1...0...01
384 * read-only, dirty, old 10..1...1...01
385 * read-only, dirty, young 11..1...0...01
386 * read-write, clean, old 00..1...1...11
387 * read-write, clean, young 01..1...0...11
388 * read-write, dirty, old 10..0...1...11
389 * read-write, dirty, young 11..0...0...11
390 * The segment table origin is used to distinguish empty (origin==0) from
391 * read-write, old segment table entries (origin!=0)
392 */
393
394 #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */
395
396 /* Page status table bits for virtualization */
397 #define PGSTE_ACC_BITS 0xf000000000000000UL
398 #define PGSTE_FP_BIT 0x0800000000000000UL
399 #define PGSTE_PCL_BIT 0x0080000000000000UL
400 #define PGSTE_HR_BIT 0x0040000000000000UL
401 #define PGSTE_HC_BIT 0x0020000000000000UL
402 #define PGSTE_GR_BIT 0x0004000000000000UL
403 #define PGSTE_GC_BIT 0x0002000000000000UL
404 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */
405 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */
406
407 #endif /* CONFIG_64BIT */
408
409 /* Guest Page State used for virtualization */
410 #define _PGSTE_GPS_ZERO 0x0000000080000000UL
411 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
412 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
413 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
414
415 /*
416 * A user page table pointer has the space-switch-event bit, the
417 * private-space-control bit and the storage-alteration-event-control
418 * bit set. A kernel page table pointer doesn't need them.
419 */
420 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
421 _ASCE_ALT_EVENT)
422
423 /*
424 * Page protection definitions.
425 */
426 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
427 #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
428 _PAGE_INVALID | _PAGE_PROTECT)
429 #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
430 _PAGE_INVALID | _PAGE_PROTECT)
431
432 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
433 _PAGE_YOUNG | _PAGE_DIRTY)
434 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
435 _PAGE_YOUNG | _PAGE_DIRTY)
436 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
437 _PAGE_PROTECT)
438
439 /*
440 * On s390 the page table entry has an invalid bit and a read-only bit.
441 * Read permission implies execute permission and write permission
442 * implies read permission.
443 */
444 /*xwr*/
445 #define __P000 PAGE_NONE
446 #define __P001 PAGE_READ
447 #define __P010 PAGE_READ
448 #define __P011 PAGE_READ
449 #define __P100 PAGE_READ
450 #define __P101 PAGE_READ
451 #define __P110 PAGE_READ
452 #define __P111 PAGE_READ
453
454 #define __S000 PAGE_NONE
455 #define __S001 PAGE_READ
456 #define __S010 PAGE_WRITE
457 #define __S011 PAGE_WRITE
458 #define __S100 PAGE_READ
459 #define __S101 PAGE_READ
460 #define __S110 PAGE_WRITE
461 #define __S111 PAGE_WRITE
462
463 /*
464 * Segment entry (large page) protection definitions.
465 */
466 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
467 _SEGMENT_ENTRY_PROTECT)
468 #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \
469 _SEGMENT_ENTRY_READ)
470 #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \
471 _SEGMENT_ENTRY_WRITE)
472
mm_has_pgste(struct mm_struct * mm)473 static inline int mm_has_pgste(struct mm_struct *mm)
474 {
475 #ifdef CONFIG_PGSTE
476 if (unlikely(mm->context.has_pgste))
477 return 1;
478 #endif
479 return 0;
480 }
481
mm_use_skey(struct mm_struct * mm)482 static inline int mm_use_skey(struct mm_struct *mm)
483 {
484 #ifdef CONFIG_PGSTE
485 if (mm->context.use_skey)
486 return 1;
487 #endif
488 return 0;
489 }
490
491 /*
492 * pgd/pmd/pte query functions
493 */
494 #ifndef CONFIG_64BIT
495
pgd_present(pgd_t pgd)496 static inline int pgd_present(pgd_t pgd) { return 1; }
pgd_none(pgd_t pgd)497 static inline int pgd_none(pgd_t pgd) { return 0; }
pgd_bad(pgd_t pgd)498 static inline int pgd_bad(pgd_t pgd) { return 0; }
499
pud_present(pud_t pud)500 static inline int pud_present(pud_t pud) { return 1; }
pud_none(pud_t pud)501 static inline int pud_none(pud_t pud) { return 0; }
pud_large(pud_t pud)502 static inline int pud_large(pud_t pud) { return 0; }
pud_bad(pud_t pud)503 static inline int pud_bad(pud_t pud) { return 0; }
504
505 #else /* CONFIG_64BIT */
506
pgd_present(pgd_t pgd)507 static inline int pgd_present(pgd_t pgd)
508 {
509 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
510 return 1;
511 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
512 }
513
pgd_none(pgd_t pgd)514 static inline int pgd_none(pgd_t pgd)
515 {
516 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
517 return 0;
518 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
519 }
520
pgd_bad(pgd_t pgd)521 static inline int pgd_bad(pgd_t pgd)
522 {
523 /*
524 * With dynamic page table levels the pgd can be a region table
525 * entry or a segment table entry. Check for the bit that are
526 * invalid for either table entry.
527 */
528 unsigned long mask =
529 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
530 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
531 return (pgd_val(pgd) & mask) != 0;
532 }
533
pud_present(pud_t pud)534 static inline int pud_present(pud_t pud)
535 {
536 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
537 return 1;
538 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
539 }
540
pud_none(pud_t pud)541 static inline int pud_none(pud_t pud)
542 {
543 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
544 return 0;
545 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
546 }
547
pud_large(pud_t pud)548 static inline int pud_large(pud_t pud)
549 {
550 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
551 return 0;
552 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
553 }
554
pud_bad(pud_t pud)555 static inline int pud_bad(pud_t pud)
556 {
557 /*
558 * With dynamic page table levels the pud can be a region table
559 * entry or a segment table entry. Check for the bit that are
560 * invalid for either table entry.
561 */
562 unsigned long mask =
563 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
564 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
565 return (pud_val(pud) & mask) != 0;
566 }
567
568 #endif /* CONFIG_64BIT */
569
pmd_present(pmd_t pmd)570 static inline int pmd_present(pmd_t pmd)
571 {
572 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
573 }
574
pmd_none(pmd_t pmd)575 static inline int pmd_none(pmd_t pmd)
576 {
577 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
578 }
579
pmd_large(pmd_t pmd)580 static inline int pmd_large(pmd_t pmd)
581 {
582 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
583 }
584
pmd_pfn(pmd_t pmd)585 static inline unsigned long pmd_pfn(pmd_t pmd)
586 {
587 unsigned long origin_mask;
588
589 origin_mask = _SEGMENT_ENTRY_ORIGIN;
590 if (pmd_large(pmd))
591 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
592 return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT;
593 }
594
pmd_bad(pmd_t pmd)595 static inline int pmd_bad(pmd_t pmd)
596 {
597 if (pmd_large(pmd))
598 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
599 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
600 }
601
602 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
603 extern void pmdp_splitting_flush(struct vm_area_struct *vma,
604 unsigned long addr, pmd_t *pmdp);
605
606 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
607 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
608 unsigned long address, pmd_t *pmdp,
609 pmd_t entry, int dirty);
610
611 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
612 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
613 unsigned long address, pmd_t *pmdp);
614
615 #define __HAVE_ARCH_PMD_WRITE
pmd_write(pmd_t pmd)616 static inline int pmd_write(pmd_t pmd)
617 {
618 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
619 }
620
pmd_dirty(pmd_t pmd)621 static inline int pmd_dirty(pmd_t pmd)
622 {
623 int dirty = 1;
624 if (pmd_large(pmd))
625 dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
626 return dirty;
627 }
628
pmd_young(pmd_t pmd)629 static inline int pmd_young(pmd_t pmd)
630 {
631 int young = 1;
632 if (pmd_large(pmd))
633 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
634 return young;
635 }
636
pte_present(pte_t pte)637 static inline int pte_present(pte_t pte)
638 {
639 /* Bit pattern: (pte & 0x001) == 0x001 */
640 return (pte_val(pte) & _PAGE_PRESENT) != 0;
641 }
642
pte_none(pte_t pte)643 static inline int pte_none(pte_t pte)
644 {
645 /* Bit pattern: pte == 0x400 */
646 return pte_val(pte) == _PAGE_INVALID;
647 }
648
pte_swap(pte_t pte)649 static inline int pte_swap(pte_t pte)
650 {
651 /* Bit pattern: (pte & 0x603) == 0x402 */
652 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT |
653 _PAGE_TYPE | _PAGE_PRESENT))
654 == (_PAGE_INVALID | _PAGE_TYPE);
655 }
656
pte_file(pte_t pte)657 static inline int pte_file(pte_t pte)
658 {
659 /* Bit pattern: (pte & 0x601) == 0x600 */
660 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
661 == (_PAGE_INVALID | _PAGE_PROTECT);
662 }
663
pte_special(pte_t pte)664 static inline int pte_special(pte_t pte)
665 {
666 return (pte_val(pte) & _PAGE_SPECIAL);
667 }
668
669 #define __HAVE_ARCH_PTE_SAME
pte_same(pte_t a,pte_t b)670 static inline int pte_same(pte_t a, pte_t b)
671 {
672 return pte_val(a) == pte_val(b);
673 }
674
pgste_get_lock(pte_t * ptep)675 static inline pgste_t pgste_get_lock(pte_t *ptep)
676 {
677 unsigned long new = 0;
678 #ifdef CONFIG_PGSTE
679 unsigned long old;
680
681 preempt_disable();
682 asm(
683 " lg %0,%2\n"
684 "0: lgr %1,%0\n"
685 " nihh %0,0xff7f\n" /* clear PCL bit in old */
686 " oihh %1,0x0080\n" /* set PCL bit in new */
687 " csg %0,%1,%2\n"
688 " jl 0b\n"
689 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
690 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
691 #endif
692 return __pgste(new);
693 }
694
pgste_set_unlock(pte_t * ptep,pgste_t pgste)695 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
696 {
697 #ifdef CONFIG_PGSTE
698 asm(
699 " nihh %1,0xff7f\n" /* clear PCL bit */
700 " stg %1,%0\n"
701 : "=Q" (ptep[PTRS_PER_PTE])
702 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
703 : "cc", "memory");
704 preempt_enable();
705 #endif
706 }
707
pgste_get(pte_t * ptep)708 static inline pgste_t pgste_get(pte_t *ptep)
709 {
710 unsigned long pgste = 0;
711 #ifdef CONFIG_PGSTE
712 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
713 #endif
714 return __pgste(pgste);
715 }
716
pgste_set(pte_t * ptep,pgste_t pgste)717 static inline void pgste_set(pte_t *ptep, pgste_t pgste)
718 {
719 #ifdef CONFIG_PGSTE
720 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
721 #endif
722 }
723
pgste_update_all(pte_t * ptep,pgste_t pgste,struct mm_struct * mm)724 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste,
725 struct mm_struct *mm)
726 {
727 #ifdef CONFIG_PGSTE
728 unsigned long address, bits, skey;
729
730 if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID)
731 return pgste;
732 address = pte_val(*ptep) & PAGE_MASK;
733 skey = (unsigned long) page_get_storage_key(address);
734 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
735 /* Transfer page changed & referenced bit to guest bits in pgste */
736 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
737 /* Copy page access key and fetch protection bit to pgste */
738 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
739 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
740 #endif
741 return pgste;
742
743 }
744
pgste_set_key(pte_t * ptep,pgste_t pgste,pte_t entry,struct mm_struct * mm)745 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry,
746 struct mm_struct *mm)
747 {
748 #ifdef CONFIG_PGSTE
749 unsigned long address;
750 unsigned long nkey;
751
752 if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID)
753 return;
754 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
755 address = pte_val(entry) & PAGE_MASK;
756 /*
757 * Set page access key and fetch protection bit from pgste.
758 * The guest C/R information is still in the PGSTE, set real
759 * key C/R to 0.
760 */
761 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
762 nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48;
763 page_set_storage_key(address, nkey, 0);
764 #endif
765 }
766
pgste_set_pte(pte_t * ptep,pgste_t pgste,pte_t entry)767 static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
768 {
769 if ((pte_val(entry) & _PAGE_PRESENT) &&
770 (pte_val(entry) & _PAGE_WRITE) &&
771 !(pte_val(entry) & _PAGE_INVALID)) {
772 if (!MACHINE_HAS_ESOP) {
773 /*
774 * Without enhanced suppression-on-protection force
775 * the dirty bit on for all writable ptes.
776 */
777 pte_val(entry) |= _PAGE_DIRTY;
778 pte_val(entry) &= ~_PAGE_PROTECT;
779 }
780 if (!(pte_val(entry) & _PAGE_PROTECT))
781 /* This pte allows write access, set user-dirty */
782 pgste_val(pgste) |= PGSTE_UC_BIT;
783 }
784 *ptep = entry;
785 return pgste;
786 }
787
788 /**
789 * struct gmap_struct - guest address space
790 * @crst_list: list of all crst tables used in the guest address space
791 * @mm: pointer to the parent mm_struct
792 * @guest_to_host: radix tree with guest to host address translation
793 * @host_to_guest: radix tree with pointer to segment table entries
794 * @guest_table_lock: spinlock to protect all entries in the guest page table
795 * @table: pointer to the page directory
796 * @asce: address space control element for gmap page table
797 * @pfault_enabled: defines if pfaults are applicable for the guest
798 */
799 struct gmap {
800 struct list_head list;
801 struct list_head crst_list;
802 struct mm_struct *mm;
803 struct radix_tree_root guest_to_host;
804 struct radix_tree_root host_to_guest;
805 spinlock_t guest_table_lock;
806 unsigned long *table;
807 unsigned long asce;
808 unsigned long asce_end;
809 void *private;
810 bool pfault_enabled;
811 };
812
813 /**
814 * struct gmap_notifier - notify function block for page invalidation
815 * @notifier_call: address of callback function
816 */
817 struct gmap_notifier {
818 struct list_head list;
819 void (*notifier_call)(struct gmap *gmap, unsigned long gaddr);
820 };
821
822 struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit);
823 void gmap_free(struct gmap *gmap);
824 void gmap_enable(struct gmap *gmap);
825 void gmap_disable(struct gmap *gmap);
826 int gmap_map_segment(struct gmap *gmap, unsigned long from,
827 unsigned long to, unsigned long len);
828 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
829 unsigned long __gmap_translate(struct gmap *, unsigned long gaddr);
830 unsigned long gmap_translate(struct gmap *, unsigned long gaddr);
831 int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr);
832 int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags);
833 void gmap_discard(struct gmap *, unsigned long from, unsigned long to);
834 void __gmap_zap(struct gmap *, unsigned long gaddr);
835 bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *);
836
837
838 void gmap_register_ipte_notifier(struct gmap_notifier *);
839 void gmap_unregister_ipte_notifier(struct gmap_notifier *);
840 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
841 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
842
pgste_ipte_notify(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pgste_t pgste)843 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
844 unsigned long addr,
845 pte_t *ptep, pgste_t pgste)
846 {
847 #ifdef CONFIG_PGSTE
848 if (pgste_val(pgste) & PGSTE_IN_BIT) {
849 pgste_val(pgste) &= ~PGSTE_IN_BIT;
850 gmap_do_ipte_notify(mm, addr, ptep);
851 }
852 #endif
853 return pgste;
854 }
855
856 /*
857 * Certain architectures need to do special things when PTEs
858 * within a page table are directly modified. Thus, the following
859 * hook is made available.
860 */
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t entry)861 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
862 pte_t *ptep, pte_t entry)
863 {
864 pgste_t pgste;
865
866 if (pte_present(entry))
867 pte_val(entry) &= ~_PAGE_UNUSED;
868 if (mm_has_pgste(mm)) {
869 pgste = pgste_get_lock(ptep);
870 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;
871 pgste_set_key(ptep, pgste, entry, mm);
872 pgste = pgste_set_pte(ptep, pgste, entry);
873 pgste_set_unlock(ptep, pgste);
874 } else {
875 *ptep = entry;
876 }
877 }
878
879 /*
880 * query functions pte_write/pte_dirty/pte_young only work if
881 * pte_present() is true. Undefined behaviour if not..
882 */
pte_write(pte_t pte)883 static inline int pte_write(pte_t pte)
884 {
885 return (pte_val(pte) & _PAGE_WRITE) != 0;
886 }
887
pte_dirty(pte_t pte)888 static inline int pte_dirty(pte_t pte)
889 {
890 return (pte_val(pte) & _PAGE_DIRTY) != 0;
891 }
892
pte_young(pte_t pte)893 static inline int pte_young(pte_t pte)
894 {
895 return (pte_val(pte) & _PAGE_YOUNG) != 0;
896 }
897
898 #define __HAVE_ARCH_PTE_UNUSED
pte_unused(pte_t pte)899 static inline int pte_unused(pte_t pte)
900 {
901 return pte_val(pte) & _PAGE_UNUSED;
902 }
903
904 /*
905 * pgd/pmd/pte modification functions
906 */
907
pgd_clear(pgd_t * pgd)908 static inline void pgd_clear(pgd_t *pgd)
909 {
910 #ifdef CONFIG_64BIT
911 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
912 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
913 #endif
914 }
915
pud_clear(pud_t * pud)916 static inline void pud_clear(pud_t *pud)
917 {
918 #ifdef CONFIG_64BIT
919 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
920 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
921 #endif
922 }
923
pmd_clear(pmd_t * pmdp)924 static inline void pmd_clear(pmd_t *pmdp)
925 {
926 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
927 }
928
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)929 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
930 {
931 pte_val(*ptep) = _PAGE_INVALID;
932 }
933
934 /*
935 * The following pte modification functions only work if
936 * pte_present() is true. Undefined behaviour if not..
937 */
pte_modify(pte_t pte,pgprot_t newprot)938 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
939 {
940 pte_val(pte) &= _PAGE_CHG_MASK;
941 pte_val(pte) |= pgprot_val(newprot);
942 /*
943 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
944 * invalid bit set, clear it again for readable, young pages
945 */
946 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
947 pte_val(pte) &= ~_PAGE_INVALID;
948 /*
949 * newprot for PAGE_READ and PAGE_WRITE has the page protection
950 * bit set, clear it again for writable, dirty pages
951 */
952 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
953 pte_val(pte) &= ~_PAGE_PROTECT;
954 return pte;
955 }
956
pte_wrprotect(pte_t pte)957 static inline pte_t pte_wrprotect(pte_t pte)
958 {
959 pte_val(pte) &= ~_PAGE_WRITE;
960 pte_val(pte) |= _PAGE_PROTECT;
961 return pte;
962 }
963
pte_mkwrite(pte_t pte)964 static inline pte_t pte_mkwrite(pte_t pte)
965 {
966 pte_val(pte) |= _PAGE_WRITE;
967 if (pte_val(pte) & _PAGE_DIRTY)
968 pte_val(pte) &= ~_PAGE_PROTECT;
969 return pte;
970 }
971
pte_mkclean(pte_t pte)972 static inline pte_t pte_mkclean(pte_t pte)
973 {
974 pte_val(pte) &= ~_PAGE_DIRTY;
975 pte_val(pte) |= _PAGE_PROTECT;
976 return pte;
977 }
978
pte_mkdirty(pte_t pte)979 static inline pte_t pte_mkdirty(pte_t pte)
980 {
981 pte_val(pte) |= _PAGE_DIRTY;
982 if (pte_val(pte) & _PAGE_WRITE)
983 pte_val(pte) &= ~_PAGE_PROTECT;
984 return pte;
985 }
986
pte_mkold(pte_t pte)987 static inline pte_t pte_mkold(pte_t pte)
988 {
989 pte_val(pte) &= ~_PAGE_YOUNG;
990 pte_val(pte) |= _PAGE_INVALID;
991 return pte;
992 }
993
pte_mkyoung(pte_t pte)994 static inline pte_t pte_mkyoung(pte_t pte)
995 {
996 pte_val(pte) |= _PAGE_YOUNG;
997 if (pte_val(pte) & _PAGE_READ)
998 pte_val(pte) &= ~_PAGE_INVALID;
999 return pte;
1000 }
1001
pte_mkspecial(pte_t pte)1002 static inline pte_t pte_mkspecial(pte_t pte)
1003 {
1004 pte_val(pte) |= _PAGE_SPECIAL;
1005 return pte;
1006 }
1007
1008 #ifdef CONFIG_HUGETLB_PAGE
pte_mkhuge(pte_t pte)1009 static inline pte_t pte_mkhuge(pte_t pte)
1010 {
1011 pte_val(pte) |= _PAGE_LARGE;
1012 return pte;
1013 }
1014 #endif
1015
__ptep_ipte(unsigned long address,pte_t * ptep)1016 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1017 {
1018 unsigned long pto = (unsigned long) ptep;
1019
1020 #ifndef CONFIG_64BIT
1021 /* pto in ESA mode must point to the start of the segment table */
1022 pto &= 0x7ffffc00;
1023 #endif
1024 /* Invalidation + global TLB flush for the pte */
1025 asm volatile(
1026 " ipte %2,%3"
1027 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1028 }
1029
__ptep_ipte_local(unsigned long address,pte_t * ptep)1030 static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep)
1031 {
1032 unsigned long pto = (unsigned long) ptep;
1033
1034 #ifndef CONFIG_64BIT
1035 /* pto in ESA mode must point to the start of the segment table */
1036 pto &= 0x7ffffc00;
1037 #endif
1038 /* Invalidation + local TLB flush for the pte */
1039 asm volatile(
1040 " .insn rrf,0xb2210000,%2,%3,0,1"
1041 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1042 }
1043
__ptep_ipte_range(unsigned long address,int nr,pte_t * ptep)1044 static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep)
1045 {
1046 unsigned long pto = (unsigned long) ptep;
1047
1048 #ifndef CONFIG_64BIT
1049 /* pto in ESA mode must point to the start of the segment table */
1050 pto &= 0x7ffffc00;
1051 #endif
1052 /* Invalidate a range of ptes + global TLB flush of the ptes */
1053 do {
1054 asm volatile(
1055 " .insn rrf,0xb2210000,%2,%0,%1,0"
1056 : "+a" (address), "+a" (nr) : "a" (pto) : "memory");
1057 } while (nr != 255);
1058 }
1059
ptep_flush_direct(struct mm_struct * mm,unsigned long address,pte_t * ptep)1060 static inline void ptep_flush_direct(struct mm_struct *mm,
1061 unsigned long address, pte_t *ptep)
1062 {
1063 int active, count;
1064
1065 if (pte_val(*ptep) & _PAGE_INVALID)
1066 return;
1067 active = (mm == current->active_mm) ? 1 : 0;
1068 count = atomic_add_return(0x10000, &mm->context.attach_count);
1069 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1070 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1071 __ptep_ipte_local(address, ptep);
1072 else
1073 __ptep_ipte(address, ptep);
1074 atomic_sub(0x10000, &mm->context.attach_count);
1075 }
1076
ptep_flush_lazy(struct mm_struct * mm,unsigned long address,pte_t * ptep)1077 static inline void ptep_flush_lazy(struct mm_struct *mm,
1078 unsigned long address, pte_t *ptep)
1079 {
1080 int active, count;
1081
1082 if (pte_val(*ptep) & _PAGE_INVALID)
1083 return;
1084 active = (mm == current->active_mm) ? 1 : 0;
1085 count = atomic_add_return(0x10000, &mm->context.attach_count);
1086 if ((count & 0xffff) <= active) {
1087 pte_val(*ptep) |= _PAGE_INVALID;
1088 mm->context.flush_mm = 1;
1089 } else
1090 __ptep_ipte(address, ptep);
1091 atomic_sub(0x10000, &mm->context.attach_count);
1092 }
1093
1094 /*
1095 * Get (and clear) the user dirty bit for a pte.
1096 */
ptep_test_and_clear_user_dirty(struct mm_struct * mm,unsigned long addr,pte_t * ptep)1097 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1098 unsigned long addr,
1099 pte_t *ptep)
1100 {
1101 pgste_t pgste;
1102 pte_t pte;
1103 int dirty;
1104
1105 if (!mm_has_pgste(mm))
1106 return 0;
1107 pgste = pgste_get_lock(ptep);
1108 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
1109 pgste_val(pgste) &= ~PGSTE_UC_BIT;
1110 pte = *ptep;
1111 if (dirty && (pte_val(pte) & _PAGE_PRESENT)) {
1112 pgste = pgste_ipte_notify(mm, addr, ptep, pgste);
1113 __ptep_ipte(addr, ptep);
1114 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE))
1115 pte_val(pte) |= _PAGE_PROTECT;
1116 else
1117 pte_val(pte) |= _PAGE_INVALID;
1118 *ptep = pte;
1119 }
1120 pgste_set_unlock(ptep, pgste);
1121 return dirty;
1122 }
1123
1124 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)1125 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1126 unsigned long addr, pte_t *ptep)
1127 {
1128 pgste_t pgste;
1129 pte_t pte, oldpte;
1130 int young;
1131
1132 if (mm_has_pgste(vma->vm_mm)) {
1133 pgste = pgste_get_lock(ptep);
1134 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste);
1135 }
1136
1137 oldpte = pte = *ptep;
1138 ptep_flush_direct(vma->vm_mm, addr, ptep);
1139 young = pte_young(pte);
1140 pte = pte_mkold(pte);
1141
1142 if (mm_has_pgste(vma->vm_mm)) {
1143 pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm);
1144 pgste = pgste_set_pte(ptep, pgste, pte);
1145 pgste_set_unlock(ptep, pgste);
1146 } else
1147 *ptep = pte;
1148
1149 return young;
1150 }
1151
1152 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)1153 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1154 unsigned long address, pte_t *ptep)
1155 {
1156 return ptep_test_and_clear_young(vma, address, ptep);
1157 }
1158
1159 /*
1160 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1161 * both clear the TLB for the unmapped pte. The reason is that
1162 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1163 * to modify an active pte. The sequence is
1164 * 1) ptep_get_and_clear
1165 * 2) set_pte_at
1166 * 3) flush_tlb_range
1167 * On s390 the tlb needs to get flushed with the modification of the pte
1168 * if the pte is active. The only way how this can be implemented is to
1169 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1170 * is a nop.
1171 */
1172 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)1173 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1174 unsigned long address, pte_t *ptep)
1175 {
1176 pgste_t pgste;
1177 pte_t pte;
1178
1179 if (mm_has_pgste(mm)) {
1180 pgste = pgste_get_lock(ptep);
1181 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1182 }
1183
1184 pte = *ptep;
1185 ptep_flush_lazy(mm, address, ptep);
1186 pte_val(*ptep) = _PAGE_INVALID;
1187
1188 if (mm_has_pgste(mm)) {
1189 pgste = pgste_update_all(&pte, pgste, mm);
1190 pgste_set_unlock(ptep, pgste);
1191 }
1192 return pte;
1193 }
1194
1195 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
ptep_modify_prot_start(struct mm_struct * mm,unsigned long address,pte_t * ptep)1196 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1197 unsigned long address,
1198 pte_t *ptep)
1199 {
1200 pgste_t pgste;
1201 pte_t pte;
1202
1203 if (mm_has_pgste(mm)) {
1204 pgste = pgste_get_lock(ptep);
1205 pgste_ipte_notify(mm, address, ptep, pgste);
1206 }
1207
1208 pte = *ptep;
1209 ptep_flush_lazy(mm, address, ptep);
1210
1211 if (mm_has_pgste(mm)) {
1212 pgste = pgste_update_all(&pte, pgste, mm);
1213 pgste_set(ptep, pgste);
1214 }
1215 return pte;
1216 }
1217
ptep_modify_prot_commit(struct mm_struct * mm,unsigned long address,pte_t * ptep,pte_t pte)1218 static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1219 unsigned long address,
1220 pte_t *ptep, pte_t pte)
1221 {
1222 pgste_t pgste;
1223
1224 if (mm_has_pgste(mm)) {
1225 pgste = pgste_get(ptep);
1226 pgste_set_key(ptep, pgste, pte, mm);
1227 pgste = pgste_set_pte(ptep, pgste, pte);
1228 pgste_set_unlock(ptep, pgste);
1229 } else
1230 *ptep = pte;
1231 }
1232
1233 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
ptep_clear_flush(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)1234 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1235 unsigned long address, pte_t *ptep)
1236 {
1237 pgste_t pgste;
1238 pte_t pte;
1239
1240 if (mm_has_pgste(vma->vm_mm)) {
1241 pgste = pgste_get_lock(ptep);
1242 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1243 }
1244
1245 pte = *ptep;
1246 ptep_flush_direct(vma->vm_mm, address, ptep);
1247 pte_val(*ptep) = _PAGE_INVALID;
1248
1249 if (mm_has_pgste(vma->vm_mm)) {
1250 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) ==
1251 _PGSTE_GPS_USAGE_UNUSED)
1252 pte_val(pte) |= _PAGE_UNUSED;
1253 pgste = pgste_update_all(&pte, pgste, vma->vm_mm);
1254 pgste_set_unlock(ptep, pgste);
1255 }
1256 return pte;
1257 }
1258
1259 /*
1260 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1261 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1262 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1263 * cannot be accessed while the batched unmap is running. In this case
1264 * full==1 and a simple pte_clear is enough. See tlb.h.
1265 */
1266 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
ptep_get_and_clear_full(struct mm_struct * mm,unsigned long address,pte_t * ptep,int full)1267 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1268 unsigned long address,
1269 pte_t *ptep, int full)
1270 {
1271 pgste_t pgste;
1272 pte_t pte;
1273
1274 if (!full && mm_has_pgste(mm)) {
1275 pgste = pgste_get_lock(ptep);
1276 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1277 }
1278
1279 pte = *ptep;
1280 if (!full)
1281 ptep_flush_lazy(mm, address, ptep);
1282 pte_val(*ptep) = _PAGE_INVALID;
1283
1284 if (!full && mm_has_pgste(mm)) {
1285 pgste = pgste_update_all(&pte, pgste, mm);
1286 pgste_set_unlock(ptep, pgste);
1287 }
1288 return pte;
1289 }
1290
1291 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)1292 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1293 unsigned long address, pte_t *ptep)
1294 {
1295 pgste_t pgste;
1296 pte_t pte = *ptep;
1297
1298 if (pte_write(pte)) {
1299 if (mm_has_pgste(mm)) {
1300 pgste = pgste_get_lock(ptep);
1301 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1302 }
1303
1304 ptep_flush_lazy(mm, address, ptep);
1305 pte = pte_wrprotect(pte);
1306
1307 if (mm_has_pgste(mm)) {
1308 pgste = pgste_set_pte(ptep, pgste, pte);
1309 pgste_set_unlock(ptep, pgste);
1310 } else
1311 *ptep = pte;
1312 }
1313 return pte;
1314 }
1315
1316 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
ptep_set_access_flags(struct vm_area_struct * vma,unsigned long address,pte_t * ptep,pte_t entry,int dirty)1317 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1318 unsigned long address, pte_t *ptep,
1319 pte_t entry, int dirty)
1320 {
1321 pgste_t pgste;
1322
1323 if (pte_same(*ptep, entry))
1324 return 0;
1325 if (mm_has_pgste(vma->vm_mm)) {
1326 pgste = pgste_get_lock(ptep);
1327 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1328 }
1329
1330 ptep_flush_direct(vma->vm_mm, address, ptep);
1331
1332 if (mm_has_pgste(vma->vm_mm)) {
1333 pgste_set_key(ptep, pgste, entry, vma->vm_mm);
1334 pgste = pgste_set_pte(ptep, pgste, entry);
1335 pgste_set_unlock(ptep, pgste);
1336 } else
1337 *ptep = entry;
1338 return 1;
1339 }
1340
1341 /*
1342 * Conversion functions: convert a page and protection to a page entry,
1343 * and a page entry and page directory to the page they refer to.
1344 */
mk_pte_phys(unsigned long physpage,pgprot_t pgprot)1345 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1346 {
1347 pte_t __pte;
1348 pte_val(__pte) = physpage + pgprot_val(pgprot);
1349 return pte_mkyoung(__pte);
1350 }
1351
mk_pte(struct page * page,pgprot_t pgprot)1352 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1353 {
1354 unsigned long physpage = page_to_phys(page);
1355 pte_t __pte = mk_pte_phys(physpage, pgprot);
1356
1357 if (pte_write(__pte) && PageDirty(page))
1358 __pte = pte_mkdirty(__pte);
1359 return __pte;
1360 }
1361
1362 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1363 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1364 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1365 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1366
1367 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1368 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1369
1370 #ifndef CONFIG_64BIT
1371
1372 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1373 #define pud_deref(pmd) ({ BUG(); 0UL; })
1374 #define pgd_deref(pmd) ({ BUG(); 0UL; })
1375
1376 #define pud_offset(pgd, address) ((pud_t *) pgd)
1377 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1378
1379 #else /* CONFIG_64BIT */
1380
1381 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1382 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1383 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1384
pud_offset(pgd_t * pgd,unsigned long address)1385 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1386 {
1387 pud_t *pud = (pud_t *) pgd;
1388 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1389 pud = (pud_t *) pgd_deref(*pgd);
1390 return pud + pud_index(address);
1391 }
1392
pmd_offset(pud_t * pud,unsigned long address)1393 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1394 {
1395 pmd_t *pmd = (pmd_t *) pud;
1396 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1397 pmd = (pmd_t *) pud_deref(*pud);
1398 return pmd + pmd_index(address);
1399 }
1400
1401 #endif /* CONFIG_64BIT */
1402
1403 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1404 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1405 #define pte_page(x) pfn_to_page(pte_pfn(x))
1406
1407 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
1408
1409 /* Find an entry in the lowest level page table.. */
1410 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1411 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1412 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1413 #define pte_unmap(pte) do { } while (0)
1414
1415 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
massage_pgprot_pmd(pgprot_t pgprot)1416 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1417 {
1418 /*
1419 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
1420 * Convert to segment table entry format.
1421 */
1422 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1423 return pgprot_val(SEGMENT_NONE);
1424 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1425 return pgprot_val(SEGMENT_READ);
1426 return pgprot_val(SEGMENT_WRITE);
1427 }
1428
pmd_wrprotect(pmd_t pmd)1429 static inline pmd_t pmd_wrprotect(pmd_t pmd)
1430 {
1431 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE;
1432 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1433 return pmd;
1434 }
1435
pmd_mkwrite(pmd_t pmd)1436 static inline pmd_t pmd_mkwrite(pmd_t pmd)
1437 {
1438 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE;
1439 if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1440 return pmd;
1441 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1442 return pmd;
1443 }
1444
pmd_mkclean(pmd_t pmd)1445 static inline pmd_t pmd_mkclean(pmd_t pmd)
1446 {
1447 if (pmd_large(pmd)) {
1448 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY;
1449 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1450 }
1451 return pmd;
1452 }
1453
pmd_mkdirty(pmd_t pmd)1454 static inline pmd_t pmd_mkdirty(pmd_t pmd)
1455 {
1456 if (pmd_large(pmd)) {
1457 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY;
1458 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
1459 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1460 }
1461 return pmd;
1462 }
1463
pmd_mkyoung(pmd_t pmd)1464 static inline pmd_t pmd_mkyoung(pmd_t pmd)
1465 {
1466 if (pmd_large(pmd)) {
1467 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1468 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
1469 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
1470 }
1471 return pmd;
1472 }
1473
pmd_mkold(pmd_t pmd)1474 static inline pmd_t pmd_mkold(pmd_t pmd)
1475 {
1476 if (pmd_large(pmd)) {
1477 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1478 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1479 }
1480 return pmd;
1481 }
1482
pmd_modify(pmd_t pmd,pgprot_t newprot)1483 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1484 {
1485 if (pmd_large(pmd)) {
1486 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE |
1487 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG |
1488 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT;
1489 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1490 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1491 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1492 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
1493 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1494 return pmd;
1495 }
1496 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN;
1497 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1498 return pmd;
1499 }
1500
mk_pmd_phys(unsigned long physpage,pgprot_t pgprot)1501 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1502 {
1503 pmd_t __pmd;
1504 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1505 return __pmd;
1506 }
1507
1508 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1509
__pmdp_csp(pmd_t * pmdp)1510 static inline void __pmdp_csp(pmd_t *pmdp)
1511 {
1512 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1513 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1514 _SEGMENT_ENTRY_INVALID;
1515 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1516
1517 asm volatile(
1518 " csp %1,%3"
1519 : "=m" (*pmdp)
1520 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1521 }
1522
__pmdp_idte(unsigned long address,pmd_t * pmdp)1523 static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp)
1524 {
1525 unsigned long sto;
1526
1527 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1528 asm volatile(
1529 " .insn rrf,0xb98e0000,%2,%3,0,0"
1530 : "=m" (*pmdp)
1531 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1532 : "cc" );
1533 }
1534
__pmdp_idte_local(unsigned long address,pmd_t * pmdp)1535 static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp)
1536 {
1537 unsigned long sto;
1538
1539 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1540 asm volatile(
1541 " .insn rrf,0xb98e0000,%2,%3,0,1"
1542 : "=m" (*pmdp)
1543 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1544 : "cc" );
1545 }
1546
pmdp_flush_direct(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)1547 static inline void pmdp_flush_direct(struct mm_struct *mm,
1548 unsigned long address, pmd_t *pmdp)
1549 {
1550 int active, count;
1551
1552 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1553 return;
1554 if (!MACHINE_HAS_IDTE) {
1555 __pmdp_csp(pmdp);
1556 return;
1557 }
1558 active = (mm == current->active_mm) ? 1 : 0;
1559 count = atomic_add_return(0x10000, &mm->context.attach_count);
1560 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1561 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1562 __pmdp_idte_local(address, pmdp);
1563 else
1564 __pmdp_idte(address, pmdp);
1565 atomic_sub(0x10000, &mm->context.attach_count);
1566 }
1567
pmdp_flush_lazy(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)1568 static inline void pmdp_flush_lazy(struct mm_struct *mm,
1569 unsigned long address, pmd_t *pmdp)
1570 {
1571 int active, count;
1572
1573 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1574 return;
1575 active = (mm == current->active_mm) ? 1 : 0;
1576 count = atomic_add_return(0x10000, &mm->context.attach_count);
1577 if ((count & 0xffff) <= active) {
1578 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
1579 mm->context.flush_mm = 1;
1580 } else if (MACHINE_HAS_IDTE)
1581 __pmdp_idte(address, pmdp);
1582 else
1583 __pmdp_csp(pmdp);
1584 atomic_sub(0x10000, &mm->context.attach_count);
1585 }
1586
1587 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1588
1589 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1590 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1591 pgtable_t pgtable);
1592
1593 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1594 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1595
pmd_trans_splitting(pmd_t pmd)1596 static inline int pmd_trans_splitting(pmd_t pmd)
1597 {
1598 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) &&
1599 (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT);
1600 }
1601
set_pmd_at(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,pmd_t entry)1602 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1603 pmd_t *pmdp, pmd_t entry)
1604 {
1605 *pmdp = entry;
1606 }
1607
pmd_mkhuge(pmd_t pmd)1608 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1609 {
1610 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1611 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1612 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1613 return pmd;
1614 }
1615
1616 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)1617 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1618 unsigned long address, pmd_t *pmdp)
1619 {
1620 pmd_t pmd;
1621
1622 pmd = *pmdp;
1623 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1624 *pmdp = pmd_mkold(pmd);
1625 return pmd_young(pmd);
1626 }
1627
1628 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
pmdp_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)1629 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1630 unsigned long address, pmd_t *pmdp)
1631 {
1632 pmd_t pmd = *pmdp;
1633
1634 pmdp_flush_direct(mm, address, pmdp);
1635 pmd_clear(pmdp);
1636 return pmd;
1637 }
1638
1639 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH
pmdp_clear_flush(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)1640 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1641 unsigned long address, pmd_t *pmdp)
1642 {
1643 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1644 }
1645
1646 #define __HAVE_ARCH_PMDP_INVALIDATE
pmdp_invalidate(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)1647 static inline void pmdp_invalidate(struct vm_area_struct *vma,
1648 unsigned long address, pmd_t *pmdp)
1649 {
1650 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1651 }
1652
1653 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)1654 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1655 unsigned long address, pmd_t *pmdp)
1656 {
1657 pmd_t pmd = *pmdp;
1658
1659 if (pmd_write(pmd)) {
1660 pmdp_flush_direct(mm, address, pmdp);
1661 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1662 }
1663 }
1664
1665 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1666 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1667
pmd_trans_huge(pmd_t pmd)1668 static inline int pmd_trans_huge(pmd_t pmd)
1669 {
1670 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1671 }
1672
has_transparent_hugepage(void)1673 static inline int has_transparent_hugepage(void)
1674 {
1675 return MACHINE_HAS_HPAGE ? 1 : 0;
1676 }
1677 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1678
1679 /*
1680 * 31 bit swap entry format:
1681 * A page-table entry has some bits we have to treat in a special way.
1682 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1683 * exception will occur instead of a page translation exception. The
1684 * specifiation exception has the bad habit not to store necessary
1685 * information in the lowcore.
1686 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1687 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1688 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1689 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1690 * plus 24 for the offset.
1691 * 0| offset |0110|o|type |00|
1692 * 0 0000000001111111111 2222 2 22222 33
1693 * 0 1234567890123456789 0123 4 56789 01
1694 *
1695 * 64 bit swap entry format:
1696 * A page-table entry has some bits we have to treat in a special way.
1697 * Bits 52 and bit 55 have to be zero, otherwise an specification
1698 * exception will occur instead of a page translation exception. The
1699 * specifiation exception has the bad habit not to store necessary
1700 * information in the lowcore.
1701 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1702 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1703 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1704 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1705 * plus 56 for the offset.
1706 * | offset |0110|o|type |00|
1707 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1708 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1709 */
1710 #ifndef CONFIG_64BIT
1711 #define __SWP_OFFSET_MASK (~0UL >> 12)
1712 #else
1713 #define __SWP_OFFSET_MASK (~0UL >> 11)
1714 #endif
mk_swap_pte(unsigned long type,unsigned long offset)1715 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1716 {
1717 pte_t pte;
1718 offset &= __SWP_OFFSET_MASK;
1719 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1720 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1721 return pte;
1722 }
1723
1724 #define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1725 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1726 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1727
1728 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1729 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1730
1731 #ifndef CONFIG_64BIT
1732 # define PTE_FILE_MAX_BITS 26
1733 #else /* CONFIG_64BIT */
1734 # define PTE_FILE_MAX_BITS 59
1735 #endif /* CONFIG_64BIT */
1736
1737 #define pte_to_pgoff(__pte) \
1738 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1739
1740 #define pgoff_to_pte(__off) \
1741 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1742 | _PAGE_INVALID | _PAGE_PROTECT })
1743
1744 #endif /* !__ASSEMBLY__ */
1745
1746 #define kern_addr_valid(addr) (1)
1747
1748 extern int vmem_add_mapping(unsigned long start, unsigned long size);
1749 extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1750 extern int s390_enable_sie(void);
1751 extern void s390_enable_skey(void);
1752
1753 /*
1754 * No page table caches to initialise
1755 */
pgtable_cache_init(void)1756 static inline void pgtable_cache_init(void) { }
check_pgt_cache(void)1757 static inline void check_pgt_cache(void) { }
1758
1759 #include <asm-generic/pgtable.h>
1760
1761 #endif /* _S390_PAGE_H */
1762