1 /*
2 *
3 * Copyright (C) 2013 Texas Instruments Incorporated
4 *
5 * Hwmod common for AM335x and AM43x
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "i2c.h"
21 #include "mmc.h"
22 #include "wd_timer.h"
23 #include "cm33xx.h"
24 #include "prm33xx.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
26 #include "prcm43xx.h"
27 #include "common.h"
28
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
32
33 /*
34 * 'l3' class
35 * instance(s): l3_main, l3_s, l3_instr
36 */
37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
38 .name = "l3",
39 };
40
41 struct omap_hwmod am33xx_l3_main_hwmod = {
42 .name = "l3_main",
43 .class = &am33xx_l3_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l3_gclk",
47 .prcm = {
48 .omap4 = {
49 .modulemode = MODULEMODE_SWCTRL,
50 },
51 },
52 };
53
54 /* l3_s */
55 struct omap_hwmod am33xx_l3_s_hwmod = {
56 .name = "l3_s",
57 .class = &am33xx_l3_hwmod_class,
58 .clkdm_name = "l3s_clkdm",
59 };
60
61 /* l3_instr */
62 struct omap_hwmod am33xx_l3_instr_hwmod = {
63 .name = "l3_instr",
64 .class = &am33xx_l3_hwmod_class,
65 .clkdm_name = "l3_clkdm",
66 .flags = HWMOD_INIT_NO_IDLE,
67 .main_clk = "l3_gclk",
68 .prcm = {
69 .omap4 = {
70 .modulemode = MODULEMODE_SWCTRL,
71 },
72 },
73 };
74
75 /*
76 * 'l4' class
77 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
78 */
79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
80 .name = "l4",
81 };
82
83 /* l4_ls */
84 struct omap_hwmod am33xx_l4_ls_hwmod = {
85 .name = "l4_ls",
86 .class = &am33xx_l4_hwmod_class,
87 .clkdm_name = "l4ls_clkdm",
88 .flags = HWMOD_INIT_NO_IDLE,
89 .main_clk = "l4ls_gclk",
90 .prcm = {
91 .omap4 = {
92 .modulemode = MODULEMODE_SWCTRL,
93 },
94 },
95 };
96
97 /* l4_wkup */
98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
99 .name = "l4_wkup",
100 .class = &am33xx_l4_hwmod_class,
101 .clkdm_name = "l4_wkup_clkdm",
102 .flags = HWMOD_INIT_NO_IDLE,
103 .prcm = {
104 .omap4 = {
105 .modulemode = MODULEMODE_SWCTRL,
106 },
107 },
108 };
109
110 /*
111 * 'mpu' class
112 */
113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
114 .name = "mpu",
115 };
116
117 struct omap_hwmod am33xx_mpu_hwmod = {
118 .name = "mpu",
119 .class = &am33xx_mpu_hwmod_class,
120 .clkdm_name = "mpu_clkdm",
121 .flags = HWMOD_INIT_NO_IDLE,
122 .main_clk = "dpll_mpu_m2_ck",
123 .prcm = {
124 .omap4 = {
125 .modulemode = MODULEMODE_SWCTRL,
126 },
127 },
128 };
129
130 /*
131 * 'wakeup m3' class
132 * Wakeup controller sub-system under wakeup domain
133 */
134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
135 .name = "wkup_m3",
136 };
137
138 /*
139 * 'pru-icss' class
140 * Programmable Real-Time Unit and Industrial Communication Subsystem
141 */
142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
143 .name = "pruss",
144 };
145
146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
147 { .name = "pruss", .rst_shift = 1 },
148 };
149
150 /* pru-icss */
151 /* Pseudo hwmod for reset control purpose only */
152 struct omap_hwmod am33xx_pruss_hwmod = {
153 .name = "pruss",
154 .class = &am33xx_pruss_hwmod_class,
155 .clkdm_name = "pruss_ocp_clkdm",
156 .main_clk = "pruss_ocp_gclk",
157 .prcm = {
158 .omap4 = {
159 .modulemode = MODULEMODE_SWCTRL,
160 },
161 },
162 .rst_lines = am33xx_pruss_resets,
163 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
164 };
165
166 /* gfx */
167 /* Pseudo hwmod for reset control purpose only */
168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
169 .name = "gfx",
170 };
171
172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
173 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
174 };
175
176 struct omap_hwmod am33xx_gfx_hwmod = {
177 .name = "gfx",
178 .class = &am33xx_gfx_hwmod_class,
179 .clkdm_name = "gfx_l3_clkdm",
180 .main_clk = "gfx_fck_div_ck",
181 .prcm = {
182 .omap4 = {
183 .modulemode = MODULEMODE_SWCTRL,
184 },
185 },
186 .rst_lines = am33xx_gfx_resets,
187 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
188 };
189
190 /*
191 * 'prcm' class
192 * power and reset manager (whole prcm infrastructure)
193 */
194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
195 .name = "prcm",
196 };
197
198 /* prcm */
199 struct omap_hwmod am33xx_prcm_hwmod = {
200 .name = "prcm",
201 .class = &am33xx_prcm_hwmod_class,
202 .clkdm_name = "l4_wkup_clkdm",
203 };
204
205 /*
206 * 'aes0' class
207 */
208 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
209 .rev_offs = 0x80,
210 .sysc_offs = 0x84,
211 .syss_offs = 0x88,
212 .sysc_flags = SYSS_HAS_RESET_STATUS,
213 };
214
215 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
216 .name = "aes0",
217 .sysc = &am33xx_aes0_sysc,
218 };
219
220 struct omap_hwmod am33xx_aes0_hwmod = {
221 .name = "aes",
222 .class = &am33xx_aes0_hwmod_class,
223 .clkdm_name = "l3_clkdm",
224 .main_clk = "aes0_fck",
225 .prcm = {
226 .omap4 = {
227 .modulemode = MODULEMODE_SWCTRL,
228 },
229 },
230 };
231
232 /* sha0 HIB2 (the 'P' (public) device) */
233 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
234 .rev_offs = 0x100,
235 .sysc_offs = 0x110,
236 .syss_offs = 0x114,
237 .sysc_flags = SYSS_HAS_RESET_STATUS,
238 };
239
240 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
241 .name = "sha0",
242 .sysc = &am33xx_sha0_sysc,
243 };
244
245 struct omap_hwmod am33xx_sha0_hwmod = {
246 .name = "sham",
247 .class = &am33xx_sha0_hwmod_class,
248 .clkdm_name = "l3_clkdm",
249 .main_clk = "l3_gclk",
250 .prcm = {
251 .omap4 = {
252 .modulemode = MODULEMODE_SWCTRL,
253 },
254 },
255 };
256
257 /* ocmcram */
258 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
259 .name = "ocmcram",
260 };
261
262 struct omap_hwmod am33xx_ocmcram_hwmod = {
263 .name = "ocmcram",
264 .class = &am33xx_ocmcram_hwmod_class,
265 .clkdm_name = "l3_clkdm",
266 .flags = HWMOD_INIT_NO_IDLE,
267 .main_clk = "l3_gclk",
268 .prcm = {
269 .omap4 = {
270 .modulemode = MODULEMODE_SWCTRL,
271 },
272 },
273 };
274
275 /* 'smartreflex' class */
276 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
277 .name = "smartreflex",
278 };
279
280 /* smartreflex0 */
281 struct omap_hwmod am33xx_smartreflex0_hwmod = {
282 .name = "smartreflex0",
283 .class = &am33xx_smartreflex_hwmod_class,
284 .clkdm_name = "l4_wkup_clkdm",
285 .main_clk = "smartreflex0_fck",
286 .prcm = {
287 .omap4 = {
288 .modulemode = MODULEMODE_SWCTRL,
289 },
290 },
291 };
292
293 /* smartreflex1 */
294 struct omap_hwmod am33xx_smartreflex1_hwmod = {
295 .name = "smartreflex1",
296 .class = &am33xx_smartreflex_hwmod_class,
297 .clkdm_name = "l4_wkup_clkdm",
298 .main_clk = "smartreflex1_fck",
299 .prcm = {
300 .omap4 = {
301 .modulemode = MODULEMODE_SWCTRL,
302 },
303 },
304 };
305
306 /*
307 * 'control' module class
308 */
309 struct omap_hwmod_class am33xx_control_hwmod_class = {
310 .name = "control",
311 };
312
313 /*
314 * 'cpgmac' class
315 * cpsw/cpgmac sub system
316 */
317 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
318 .rev_offs = 0x0,
319 .sysc_offs = 0x8,
320 .syss_offs = 0x4,
321 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
322 SYSS_HAS_RESET_STATUS),
323 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
324 MSTANDBY_NO),
325 .sysc_fields = &omap_hwmod_sysc_type3,
326 };
327
328 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
329 .name = "cpgmac0",
330 .sysc = &am33xx_cpgmac_sysc,
331 };
332
333 struct omap_hwmod am33xx_cpgmac0_hwmod = {
334 .name = "cpgmac0",
335 .class = &am33xx_cpgmac0_hwmod_class,
336 .clkdm_name = "cpsw_125mhz_clkdm",
337 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
338 .main_clk = "cpsw_125mhz_gclk",
339 .mpu_rt_idx = 1,
340 .prcm = {
341 .omap4 = {
342 .modulemode = MODULEMODE_SWCTRL,
343 },
344 },
345 };
346
347 /*
348 * mdio class
349 */
350 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
351 .name = "davinci_mdio",
352 };
353
354 struct omap_hwmod am33xx_mdio_hwmod = {
355 .name = "davinci_mdio",
356 .class = &am33xx_mdio_hwmod_class,
357 .clkdm_name = "cpsw_125mhz_clkdm",
358 .main_clk = "cpsw_125mhz_gclk",
359 };
360
361 /*
362 * dcan class
363 */
364 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
365 .name = "d_can",
366 };
367
368 /* dcan0 */
369 struct omap_hwmod am33xx_dcan0_hwmod = {
370 .name = "d_can0",
371 .class = &am33xx_dcan_hwmod_class,
372 .clkdm_name = "l4ls_clkdm",
373 .main_clk = "dcan0_fck",
374 .prcm = {
375 .omap4 = {
376 .modulemode = MODULEMODE_SWCTRL,
377 },
378 },
379 };
380
381 /* dcan1 */
382 struct omap_hwmod am33xx_dcan1_hwmod = {
383 .name = "d_can1",
384 .class = &am33xx_dcan_hwmod_class,
385 .clkdm_name = "l4ls_clkdm",
386 .main_clk = "dcan1_fck",
387 .prcm = {
388 .omap4 = {
389 .modulemode = MODULEMODE_SWCTRL,
390 },
391 },
392 };
393
394 /* elm */
395 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
396 .rev_offs = 0x0000,
397 .sysc_offs = 0x0010,
398 .syss_offs = 0x0014,
399 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
400 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
401 SYSS_HAS_RESET_STATUS),
402 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
403 .sysc_fields = &omap_hwmod_sysc_type1,
404 };
405
406 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
407 .name = "elm",
408 .sysc = &am33xx_elm_sysc,
409 };
410
411 struct omap_hwmod am33xx_elm_hwmod = {
412 .name = "elm",
413 .class = &am33xx_elm_hwmod_class,
414 .clkdm_name = "l4ls_clkdm",
415 .main_clk = "l4ls_gclk",
416 .prcm = {
417 .omap4 = {
418 .modulemode = MODULEMODE_SWCTRL,
419 },
420 },
421 };
422
423 /* pwmss */
424 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
425 .rev_offs = 0x0,
426 .sysc_offs = 0x4,
427 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
429 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
430 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
431 .sysc_fields = &omap_hwmod_sysc_type2,
432 };
433
434 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
435 .name = "epwmss",
436 .sysc = &am33xx_epwmss_sysc,
437 };
438
439 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
440 .name = "ecap",
441 };
442
443 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
444 .name = "eqep",
445 };
446
447 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
448 .name = "ehrpwm",
449 };
450
451 /* epwmss0 */
452 struct omap_hwmod am33xx_epwmss0_hwmod = {
453 .name = "epwmss0",
454 .class = &am33xx_epwmss_hwmod_class,
455 .clkdm_name = "l4ls_clkdm",
456 .main_clk = "l4ls_gclk",
457 .prcm = {
458 .omap4 = {
459 .modulemode = MODULEMODE_SWCTRL,
460 },
461 },
462 };
463
464 /* ecap0 */
465 struct omap_hwmod am33xx_ecap0_hwmod = {
466 .name = "ecap0",
467 .class = &am33xx_ecap_hwmod_class,
468 .clkdm_name = "l4ls_clkdm",
469 .main_clk = "l4ls_gclk",
470 };
471
472 /* eqep0 */
473 struct omap_hwmod am33xx_eqep0_hwmod = {
474 .name = "eqep0",
475 .class = &am33xx_eqep_hwmod_class,
476 .clkdm_name = "l4ls_clkdm",
477 .main_clk = "l4ls_gclk",
478 };
479
480 /* ehrpwm0 */
481 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
482 .name = "ehrpwm0",
483 .class = &am33xx_ehrpwm_hwmod_class,
484 .clkdm_name = "l4ls_clkdm",
485 .main_clk = "l4ls_gclk",
486 };
487
488 /* epwmss1 */
489 struct omap_hwmod am33xx_epwmss1_hwmod = {
490 .name = "epwmss1",
491 .class = &am33xx_epwmss_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
494 .prcm = {
495 .omap4 = {
496 .modulemode = MODULEMODE_SWCTRL,
497 },
498 },
499 };
500
501 /* ecap1 */
502 struct omap_hwmod am33xx_ecap1_hwmod = {
503 .name = "ecap1",
504 .class = &am33xx_ecap_hwmod_class,
505 .clkdm_name = "l4ls_clkdm",
506 .main_clk = "l4ls_gclk",
507 };
508
509 /* eqep1 */
510 struct omap_hwmod am33xx_eqep1_hwmod = {
511 .name = "eqep1",
512 .class = &am33xx_eqep_hwmod_class,
513 .clkdm_name = "l4ls_clkdm",
514 .main_clk = "l4ls_gclk",
515 };
516
517 /* ehrpwm1 */
518 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
519 .name = "ehrpwm1",
520 .class = &am33xx_ehrpwm_hwmod_class,
521 .clkdm_name = "l4ls_clkdm",
522 .main_clk = "l4ls_gclk",
523 };
524
525 /* epwmss2 */
526 struct omap_hwmod am33xx_epwmss2_hwmod = {
527 .name = "epwmss2",
528 .class = &am33xx_epwmss_hwmod_class,
529 .clkdm_name = "l4ls_clkdm",
530 .main_clk = "l4ls_gclk",
531 .prcm = {
532 .omap4 = {
533 .modulemode = MODULEMODE_SWCTRL,
534 },
535 },
536 };
537
538 /* ecap2 */
539 struct omap_hwmod am33xx_ecap2_hwmod = {
540 .name = "ecap2",
541 .class = &am33xx_ecap_hwmod_class,
542 .clkdm_name = "l4ls_clkdm",
543 .main_clk = "l4ls_gclk",
544 };
545
546 /* eqep2 */
547 struct omap_hwmod am33xx_eqep2_hwmod = {
548 .name = "eqep2",
549 .class = &am33xx_eqep_hwmod_class,
550 .clkdm_name = "l4ls_clkdm",
551 .main_clk = "l4ls_gclk",
552 };
553
554 /* ehrpwm2 */
555 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
556 .name = "ehrpwm2",
557 .class = &am33xx_ehrpwm_hwmod_class,
558 .clkdm_name = "l4ls_clkdm",
559 .main_clk = "l4ls_gclk",
560 };
561
562 /*
563 * 'gpio' class: for gpio 0,1,2,3
564 */
565 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
566 .rev_offs = 0x0000,
567 .sysc_offs = 0x0010,
568 .syss_offs = 0x0114,
569 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
570 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
571 SYSS_HAS_RESET_STATUS),
572 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
573 SIDLE_SMART_WKUP),
574 .sysc_fields = &omap_hwmod_sysc_type1,
575 };
576
577 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
578 .name = "gpio",
579 .sysc = &am33xx_gpio_sysc,
580 .rev = 2,
581 };
582
583 struct omap_gpio_dev_attr gpio_dev_attr = {
584 .bank_width = 32,
585 .dbck_flag = true,
586 };
587
588 /* gpio1 */
589 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
590 { .role = "dbclk", .clk = "gpio1_dbclk" },
591 };
592
593 struct omap_hwmod am33xx_gpio1_hwmod = {
594 .name = "gpio2",
595 .class = &am33xx_gpio_hwmod_class,
596 .clkdm_name = "l4ls_clkdm",
597 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
598 .main_clk = "l4ls_gclk",
599 .prcm = {
600 .omap4 = {
601 .modulemode = MODULEMODE_SWCTRL,
602 },
603 },
604 .opt_clks = gpio1_opt_clks,
605 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
606 .dev_attr = &gpio_dev_attr,
607 };
608
609 /* gpio2 */
610 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
611 { .role = "dbclk", .clk = "gpio2_dbclk" },
612 };
613
614 struct omap_hwmod am33xx_gpio2_hwmod = {
615 .name = "gpio3",
616 .class = &am33xx_gpio_hwmod_class,
617 .clkdm_name = "l4ls_clkdm",
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .main_clk = "l4ls_gclk",
620 .prcm = {
621 .omap4 = {
622 .modulemode = MODULEMODE_SWCTRL,
623 },
624 },
625 .opt_clks = gpio2_opt_clks,
626 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
627 .dev_attr = &gpio_dev_attr,
628 };
629
630 /* gpio3 */
631 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
632 { .role = "dbclk", .clk = "gpio3_dbclk" },
633 };
634
635 struct omap_hwmod am33xx_gpio3_hwmod = {
636 .name = "gpio4",
637 .class = &am33xx_gpio_hwmod_class,
638 .clkdm_name = "l4ls_clkdm",
639 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
640 .main_clk = "l4ls_gclk",
641 .prcm = {
642 .omap4 = {
643 .modulemode = MODULEMODE_SWCTRL,
644 },
645 },
646 .opt_clks = gpio3_opt_clks,
647 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
648 .dev_attr = &gpio_dev_attr,
649 };
650
651 /* gpmc */
652 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
653 .rev_offs = 0x0,
654 .sysc_offs = 0x10,
655 .syss_offs = 0x14,
656 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
657 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
659 .sysc_fields = &omap_hwmod_sysc_type1,
660 };
661
662 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
663 .name = "gpmc",
664 .sysc = &gpmc_sysc,
665 };
666
667 struct omap_hwmod am33xx_gpmc_hwmod = {
668 .name = "gpmc",
669 .class = &am33xx_gpmc_hwmod_class,
670 .clkdm_name = "l3s_clkdm",
671 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
672 .main_clk = "l3s_gclk",
673 .prcm = {
674 .omap4 = {
675 .modulemode = MODULEMODE_SWCTRL,
676 },
677 },
678 };
679
680 /* 'i2c' class */
681 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
682 .sysc_offs = 0x0010,
683 .syss_offs = 0x0090,
684 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
685 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
686 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
687 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
688 SIDLE_SMART_WKUP),
689 .sysc_fields = &omap_hwmod_sysc_type1,
690 };
691
692 static struct omap_hwmod_class i2c_class = {
693 .name = "i2c",
694 .sysc = &am33xx_i2c_sysc,
695 .rev = OMAP_I2C_IP_VERSION_2,
696 .reset = &omap_i2c_reset,
697 };
698
699 static struct omap_i2c_dev_attr i2c_dev_attr = {
700 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
701 };
702
703 /* i2c1 */
704 struct omap_hwmod am33xx_i2c1_hwmod = {
705 .name = "i2c1",
706 .class = &i2c_class,
707 .clkdm_name = "l4_wkup_clkdm",
708 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
709 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
710 .prcm = {
711 .omap4 = {
712 .modulemode = MODULEMODE_SWCTRL,
713 },
714 },
715 .dev_attr = &i2c_dev_attr,
716 };
717
718 /* i2c1 */
719 struct omap_hwmod am33xx_i2c2_hwmod = {
720 .name = "i2c2",
721 .class = &i2c_class,
722 .clkdm_name = "l4ls_clkdm",
723 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
724 .main_clk = "dpll_per_m2_div4_ck",
725 .prcm = {
726 .omap4 = {
727 .modulemode = MODULEMODE_SWCTRL,
728 },
729 },
730 .dev_attr = &i2c_dev_attr,
731 };
732
733 /* i2c3 */
734 struct omap_hwmod am33xx_i2c3_hwmod = {
735 .name = "i2c3",
736 .class = &i2c_class,
737 .clkdm_name = "l4ls_clkdm",
738 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
739 .main_clk = "dpll_per_m2_div4_ck",
740 .prcm = {
741 .omap4 = {
742 .modulemode = MODULEMODE_SWCTRL,
743 },
744 },
745 .dev_attr = &i2c_dev_attr,
746 };
747
748 /*
749 * 'mailbox' class
750 * mailbox module allowing communication between the on-chip processors using a
751 * queued mailbox-interrupt mechanism.
752 */
753 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
754 .rev_offs = 0x0000,
755 .sysc_offs = 0x0010,
756 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
757 SYSC_HAS_SOFTRESET),
758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
759 .sysc_fields = &omap_hwmod_sysc_type2,
760 };
761
762 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
763 .name = "mailbox",
764 .sysc = &am33xx_mailbox_sysc,
765 };
766
767 struct omap_hwmod am33xx_mailbox_hwmod = {
768 .name = "mailbox",
769 .class = &am33xx_mailbox_hwmod_class,
770 .clkdm_name = "l4ls_clkdm",
771 .main_clk = "l4ls_gclk",
772 .prcm = {
773 .omap4 = {
774 .modulemode = MODULEMODE_SWCTRL,
775 },
776 },
777 };
778
779 /*
780 * 'mcasp' class
781 */
782 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
783 .rev_offs = 0x0,
784 .sysc_offs = 0x4,
785 .sysc_flags = SYSC_HAS_SIDLEMODE,
786 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
787 .sysc_fields = &omap_hwmod_sysc_type3,
788 };
789
790 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
791 .name = "mcasp",
792 .sysc = &am33xx_mcasp_sysc,
793 };
794
795 /* mcasp0 */
796 struct omap_hwmod am33xx_mcasp0_hwmod = {
797 .name = "mcasp0",
798 .class = &am33xx_mcasp_hwmod_class,
799 .clkdm_name = "l3s_clkdm",
800 .main_clk = "mcasp0_fck",
801 .prcm = {
802 .omap4 = {
803 .modulemode = MODULEMODE_SWCTRL,
804 },
805 },
806 };
807
808 /* mcasp1 */
809 struct omap_hwmod am33xx_mcasp1_hwmod = {
810 .name = "mcasp1",
811 .class = &am33xx_mcasp_hwmod_class,
812 .clkdm_name = "l3s_clkdm",
813 .main_clk = "mcasp1_fck",
814 .prcm = {
815 .omap4 = {
816 .modulemode = MODULEMODE_SWCTRL,
817 },
818 },
819 };
820
821 /* 'mmc' class */
822 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
823 .rev_offs = 0x1fc,
824 .sysc_offs = 0x10,
825 .syss_offs = 0x14,
826 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
827 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
828 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
829 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
830 .sysc_fields = &omap_hwmod_sysc_type1,
831 };
832
833 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
834 .name = "mmc",
835 .sysc = &am33xx_mmc_sysc,
836 };
837
838 /* mmc0 */
839 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
840 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
841 };
842
843 struct omap_hwmod am33xx_mmc0_hwmod = {
844 .name = "mmc1",
845 .class = &am33xx_mmc_hwmod_class,
846 .clkdm_name = "l4ls_clkdm",
847 .main_clk = "mmc_clk",
848 .prcm = {
849 .omap4 = {
850 .modulemode = MODULEMODE_SWCTRL,
851 },
852 },
853 .dev_attr = &am33xx_mmc0_dev_attr,
854 };
855
856 /* mmc1 */
857 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
858 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
859 };
860
861 struct omap_hwmod am33xx_mmc1_hwmod = {
862 .name = "mmc2",
863 .class = &am33xx_mmc_hwmod_class,
864 .clkdm_name = "l4ls_clkdm",
865 .main_clk = "mmc_clk",
866 .prcm = {
867 .omap4 = {
868 .modulemode = MODULEMODE_SWCTRL,
869 },
870 },
871 .dev_attr = &am33xx_mmc1_dev_attr,
872 };
873
874 /* mmc2 */
875 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
876 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
877 };
878 struct omap_hwmod am33xx_mmc2_hwmod = {
879 .name = "mmc3",
880 .class = &am33xx_mmc_hwmod_class,
881 .clkdm_name = "l3s_clkdm",
882 .main_clk = "mmc_clk",
883 .prcm = {
884 .omap4 = {
885 .modulemode = MODULEMODE_SWCTRL,
886 },
887 },
888 .dev_attr = &am33xx_mmc2_dev_attr,
889 };
890
891 /*
892 * 'rtc' class
893 * rtc subsystem
894 */
895 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
896 .rev_offs = 0x0074,
897 .sysc_offs = 0x0078,
898 .sysc_flags = SYSC_HAS_SIDLEMODE,
899 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
900 SIDLE_SMART | SIDLE_SMART_WKUP),
901 .sysc_fields = &omap_hwmod_sysc_type3,
902 };
903
904 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
905 .name = "rtc",
906 .sysc = &am33xx_rtc_sysc,
907 };
908
909 struct omap_hwmod am33xx_rtc_hwmod = {
910 .name = "rtc",
911 .class = &am33xx_rtc_hwmod_class,
912 .clkdm_name = "l4_rtc_clkdm",
913 .main_clk = "clk_32768_ck",
914 .prcm = {
915 .omap4 = {
916 .modulemode = MODULEMODE_SWCTRL,
917 },
918 },
919 };
920
921 /* 'spi' class */
922 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
923 .rev_offs = 0x0000,
924 .sysc_offs = 0x0110,
925 .syss_offs = 0x0114,
926 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
927 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
928 SYSS_HAS_RESET_STATUS),
929 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
930 .sysc_fields = &omap_hwmod_sysc_type1,
931 };
932
933 struct omap_hwmod_class am33xx_spi_hwmod_class = {
934 .name = "mcspi",
935 .sysc = &am33xx_mcspi_sysc,
936 .rev = OMAP4_MCSPI_REV,
937 };
938
939 /* spi0 */
940 struct omap2_mcspi_dev_attr mcspi_attrib = {
941 .num_chipselect = 2,
942 };
943 struct omap_hwmod am33xx_spi0_hwmod = {
944 .name = "spi0",
945 .class = &am33xx_spi_hwmod_class,
946 .clkdm_name = "l4ls_clkdm",
947 .main_clk = "dpll_per_m2_div4_ck",
948 .prcm = {
949 .omap4 = {
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 .dev_attr = &mcspi_attrib,
954 };
955
956 /* spi1 */
957 struct omap_hwmod am33xx_spi1_hwmod = {
958 .name = "spi1",
959 .class = &am33xx_spi_hwmod_class,
960 .clkdm_name = "l4ls_clkdm",
961 .main_clk = "dpll_per_m2_div4_ck",
962 .prcm = {
963 .omap4 = {
964 .modulemode = MODULEMODE_SWCTRL,
965 },
966 },
967 .dev_attr = &mcspi_attrib,
968 };
969
970 /*
971 * 'spinlock' class
972 * spinlock provides hardware assistance for synchronizing the
973 * processes running on multiple processors
974 */
975
976 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
977 .rev_offs = 0x0000,
978 .sysc_offs = 0x0010,
979 .syss_offs = 0x0014,
980 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
981 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
982 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
984 .sysc_fields = &omap_hwmod_sysc_type1,
985 };
986
987 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
988 .name = "spinlock",
989 .sysc = &am33xx_spinlock_sysc,
990 };
991
992 struct omap_hwmod am33xx_spinlock_hwmod = {
993 .name = "spinlock",
994 .class = &am33xx_spinlock_hwmod_class,
995 .clkdm_name = "l4ls_clkdm",
996 .main_clk = "l4ls_gclk",
997 .prcm = {
998 .omap4 = {
999 .modulemode = MODULEMODE_SWCTRL,
1000 },
1001 },
1002 };
1003
1004 /* 'timer 2-7' class */
1005 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1006 .rev_offs = 0x0000,
1007 .sysc_offs = 0x0010,
1008 .syss_offs = 0x0014,
1009 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1011 SIDLE_SMART_WKUP),
1012 .sysc_fields = &omap_hwmod_sysc_type2,
1013 };
1014
1015 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1016 .name = "timer",
1017 .sysc = &am33xx_timer_sysc,
1018 };
1019
1020 /* timer1 1ms */
1021 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1022 .rev_offs = 0x0000,
1023 .sysc_offs = 0x0010,
1024 .syss_offs = 0x0014,
1025 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1026 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1027 SYSS_HAS_RESET_STATUS),
1028 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1029 .sysc_fields = &omap_hwmod_sysc_type1,
1030 };
1031
1032 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1033 .name = "timer",
1034 .sysc = &am33xx_timer1ms_sysc,
1035 };
1036
1037 struct omap_hwmod am33xx_timer1_hwmod = {
1038 .name = "timer1",
1039 .class = &am33xx_timer1ms_hwmod_class,
1040 .clkdm_name = "l4_wkup_clkdm",
1041 .main_clk = "timer1_fck",
1042 .prcm = {
1043 .omap4 = {
1044 .modulemode = MODULEMODE_SWCTRL,
1045 },
1046 },
1047 };
1048
1049 struct omap_hwmod am33xx_timer2_hwmod = {
1050 .name = "timer2",
1051 .class = &am33xx_timer_hwmod_class,
1052 .clkdm_name = "l4ls_clkdm",
1053 .main_clk = "timer2_fck",
1054 .prcm = {
1055 .omap4 = {
1056 .modulemode = MODULEMODE_SWCTRL,
1057 },
1058 },
1059 };
1060
1061 struct omap_hwmod am33xx_timer3_hwmod = {
1062 .name = "timer3",
1063 .class = &am33xx_timer_hwmod_class,
1064 .clkdm_name = "l4ls_clkdm",
1065 .main_clk = "timer3_fck",
1066 .prcm = {
1067 .omap4 = {
1068 .modulemode = MODULEMODE_SWCTRL,
1069 },
1070 },
1071 };
1072
1073 struct omap_hwmod am33xx_timer4_hwmod = {
1074 .name = "timer4",
1075 .class = &am33xx_timer_hwmod_class,
1076 .clkdm_name = "l4ls_clkdm",
1077 .main_clk = "timer4_fck",
1078 .prcm = {
1079 .omap4 = {
1080 .modulemode = MODULEMODE_SWCTRL,
1081 },
1082 },
1083 };
1084
1085 struct omap_hwmod am33xx_timer5_hwmod = {
1086 .name = "timer5",
1087 .class = &am33xx_timer_hwmod_class,
1088 .clkdm_name = "l4ls_clkdm",
1089 .main_clk = "timer5_fck",
1090 .prcm = {
1091 .omap4 = {
1092 .modulemode = MODULEMODE_SWCTRL,
1093 },
1094 },
1095 };
1096
1097 struct omap_hwmod am33xx_timer6_hwmod = {
1098 .name = "timer6",
1099 .class = &am33xx_timer_hwmod_class,
1100 .clkdm_name = "l4ls_clkdm",
1101 .main_clk = "timer6_fck",
1102 .prcm = {
1103 .omap4 = {
1104 .modulemode = MODULEMODE_SWCTRL,
1105 },
1106 },
1107 };
1108
1109 struct omap_hwmod am33xx_timer7_hwmod = {
1110 .name = "timer7",
1111 .class = &am33xx_timer_hwmod_class,
1112 .clkdm_name = "l4ls_clkdm",
1113 .main_clk = "timer7_fck",
1114 .prcm = {
1115 .omap4 = {
1116 .modulemode = MODULEMODE_SWCTRL,
1117 },
1118 },
1119 };
1120
1121 /* tpcc */
1122 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1123 .name = "tpcc",
1124 };
1125
1126 struct omap_hwmod am33xx_tpcc_hwmod = {
1127 .name = "tpcc",
1128 .class = &am33xx_tpcc_hwmod_class,
1129 .clkdm_name = "l3_clkdm",
1130 .main_clk = "l3_gclk",
1131 .prcm = {
1132 .omap4 = {
1133 .modulemode = MODULEMODE_SWCTRL,
1134 },
1135 },
1136 };
1137
1138 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1139 .rev_offs = 0x0,
1140 .sysc_offs = 0x10,
1141 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1142 SYSC_HAS_MIDLEMODE),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1144 .sysc_fields = &omap_hwmod_sysc_type2,
1145 };
1146
1147 /* 'tptc' class */
1148 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1149 .name = "tptc",
1150 .sysc = &am33xx_tptc_sysc,
1151 };
1152
1153 /* tptc0 */
1154 struct omap_hwmod am33xx_tptc0_hwmod = {
1155 .name = "tptc0",
1156 .class = &am33xx_tptc_hwmod_class,
1157 .clkdm_name = "l3_clkdm",
1158 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1159 .main_clk = "l3_gclk",
1160 .prcm = {
1161 .omap4 = {
1162 .modulemode = MODULEMODE_SWCTRL,
1163 },
1164 },
1165 };
1166
1167 /* tptc1 */
1168 struct omap_hwmod am33xx_tptc1_hwmod = {
1169 .name = "tptc1",
1170 .class = &am33xx_tptc_hwmod_class,
1171 .clkdm_name = "l3_clkdm",
1172 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1173 .main_clk = "l3_gclk",
1174 .prcm = {
1175 .omap4 = {
1176 .modulemode = MODULEMODE_SWCTRL,
1177 },
1178 },
1179 };
1180
1181 /* tptc2 */
1182 struct omap_hwmod am33xx_tptc2_hwmod = {
1183 .name = "tptc2",
1184 .class = &am33xx_tptc_hwmod_class,
1185 .clkdm_name = "l3_clkdm",
1186 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1187 .main_clk = "l3_gclk",
1188 .prcm = {
1189 .omap4 = {
1190 .modulemode = MODULEMODE_SWCTRL,
1191 },
1192 },
1193 };
1194
1195 /* 'uart' class */
1196 static struct omap_hwmod_class_sysconfig uart_sysc = {
1197 .rev_offs = 0x50,
1198 .sysc_offs = 0x54,
1199 .syss_offs = 0x58,
1200 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1201 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1202 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1203 SIDLE_SMART_WKUP),
1204 .sysc_fields = &omap_hwmod_sysc_type1,
1205 };
1206
1207 static struct omap_hwmod_class uart_class = {
1208 .name = "uart",
1209 .sysc = &uart_sysc,
1210 };
1211
1212 struct omap_hwmod am33xx_uart1_hwmod = {
1213 .name = "uart1",
1214 .class = &uart_class,
1215 .clkdm_name = "l4_wkup_clkdm",
1216 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1217 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1218 .prcm = {
1219 .omap4 = {
1220 .modulemode = MODULEMODE_SWCTRL,
1221 },
1222 },
1223 };
1224
1225 struct omap_hwmod am33xx_uart2_hwmod = {
1226 .name = "uart2",
1227 .class = &uart_class,
1228 .clkdm_name = "l4ls_clkdm",
1229 .flags = HWMOD_SWSUP_SIDLE_ACT,
1230 .main_clk = "dpll_per_m2_div4_ck",
1231 .prcm = {
1232 .omap4 = {
1233 .modulemode = MODULEMODE_SWCTRL,
1234 },
1235 },
1236 };
1237
1238 /* uart3 */
1239 struct omap_hwmod am33xx_uart3_hwmod = {
1240 .name = "uart3",
1241 .class = &uart_class,
1242 .clkdm_name = "l4ls_clkdm",
1243 .flags = HWMOD_SWSUP_SIDLE_ACT,
1244 .main_clk = "dpll_per_m2_div4_ck",
1245 .prcm = {
1246 .omap4 = {
1247 .modulemode = MODULEMODE_SWCTRL,
1248 },
1249 },
1250 };
1251
1252 struct omap_hwmod am33xx_uart4_hwmod = {
1253 .name = "uart4",
1254 .class = &uart_class,
1255 .clkdm_name = "l4ls_clkdm",
1256 .flags = HWMOD_SWSUP_SIDLE_ACT,
1257 .main_clk = "dpll_per_m2_div4_ck",
1258 .prcm = {
1259 .omap4 = {
1260 .modulemode = MODULEMODE_SWCTRL,
1261 },
1262 },
1263 };
1264
1265 struct omap_hwmod am33xx_uart5_hwmod = {
1266 .name = "uart5",
1267 .class = &uart_class,
1268 .clkdm_name = "l4ls_clkdm",
1269 .flags = HWMOD_SWSUP_SIDLE_ACT,
1270 .main_clk = "dpll_per_m2_div4_ck",
1271 .prcm = {
1272 .omap4 = {
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 };
1277
1278 struct omap_hwmod am33xx_uart6_hwmod = {
1279 .name = "uart6",
1280 .class = &uart_class,
1281 .clkdm_name = "l4ls_clkdm",
1282 .flags = HWMOD_SWSUP_SIDLE_ACT,
1283 .main_clk = "dpll_per_m2_div4_ck",
1284 .prcm = {
1285 .omap4 = {
1286 .modulemode = MODULEMODE_SWCTRL,
1287 },
1288 },
1289 };
1290
1291 /* 'wd_timer' class */
1292 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1293 .rev_offs = 0x0,
1294 .sysc_offs = 0x10,
1295 .syss_offs = 0x14,
1296 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1297 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1298 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1299 SIDLE_SMART_WKUP),
1300 .sysc_fields = &omap_hwmod_sysc_type1,
1301 };
1302
1303 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1304 .name = "wd_timer",
1305 .sysc = &wdt_sysc,
1306 .pre_shutdown = &omap2_wd_timer_disable,
1307 };
1308
1309 /*
1310 * XXX: device.c file uses hardcoded name for watchdog timer
1311 * driver "wd_timer2, so we are also using same name as of now...
1312 */
1313 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1314 .name = "wd_timer2",
1315 .class = &am33xx_wd_timer_hwmod_class,
1316 .clkdm_name = "l4_wkup_clkdm",
1317 .flags = HWMOD_SWSUP_SIDLE,
1318 .main_clk = "wdt1_fck",
1319 .prcm = {
1320 .omap4 = {
1321 .modulemode = MODULEMODE_SWCTRL,
1322 },
1323 },
1324 };
1325
omap_hwmod_am33xx_clkctrl(void)1326 static void omap_hwmod_am33xx_clkctrl(void)
1327 {
1328 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1329 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1330 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1331 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1332 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1333 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1334 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1335 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1336 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1337 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1338 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1339 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1340 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1341 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1342 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1343 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_smartreflex0_hwmod,
1359 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_smartreflex1_hwmod,
1361 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1384 }
1385
omap_hwmod_am33xx_rst(void)1386 static void omap_hwmod_am33xx_rst(void)
1387 {
1388 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1389 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1390 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1391 }
1392
omap_hwmod_am33xx_reg(void)1393 void omap_hwmod_am33xx_reg(void)
1394 {
1395 omap_hwmod_am33xx_clkctrl();
1396 omap_hwmod_am33xx_rst();
1397 }
1398
omap_hwmod_am43xx_clkctrl(void)1399 static void omap_hwmod_am43xx_clkctrl(void)
1400 {
1401 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1402 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1403 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1404 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1405 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1406 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1407 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1408 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1409 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1410 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1411 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1412 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1413 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1414 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1415 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1416 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1417 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1418 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1420 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1421 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1422 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1423 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1424 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1425 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1426 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1427 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1428 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1429 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1430 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1431 CLKCTRL(am33xx_smartreflex0_hwmod,
1432 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1433 CLKCTRL(am33xx_smartreflex1_hwmod,
1434 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1435 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1436 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1437 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1438 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1439 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1440 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1441 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1442 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1443 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1444 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1445 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1446 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1447 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1448 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1449 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1450 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1451 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1452 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1453 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1454 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1455 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1456 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1457 }
1458
omap_hwmod_am43xx_rst(void)1459 static void omap_hwmod_am43xx_rst(void)
1460 {
1461 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1462 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1463 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1464 }
1465
omap_hwmod_am43xx_reg(void)1466 void omap_hwmod_am43xx_reg(void)
1467 {
1468 omap_hwmod_am43xx_clkctrl();
1469 omap_hwmod_am43xx_rst();
1470 }
1471