1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/apic.h>
48 #include <asm/io_apic.h>
49 #include <asm/desc.h>
50 #include <asm/hpet.h>
51 #include <asm/idle.h>
52 #include <asm/mtrr.h>
53 #include <asm/time.h>
54 #include <asm/smp.h>
55 #include <asm/mce.h>
56 #include <asm/tsc.h>
57 #include <asm/hypervisor.h>
58
59 unsigned int num_processors;
60
61 unsigned disabled_cpus;
62
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid = -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
66
67 /*
68 * The highest APIC ID seen during enumeration.
69 */
70 static unsigned int max_physical_apicid;
71
72 /*
73 * Bitmask of physically existing CPUs:
74 */
75 physid_mask_t phys_cpu_present_map;
76
77 /*
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
81 */
82 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
83
84 /*
85 * Map cpu index to physical APIC ID
86 */
87 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
88 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
89 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
90 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
91
92 #ifdef CONFIG_X86_32
93
94 /*
95 * On x86_32, the mapping between cpu and logical apicid may vary
96 * depending on apic in use. The following early percpu variable is
97 * used for the mapping. This is where the behaviors of x86_64 and 32
98 * actually diverge. Let's keep it ugly for now.
99 */
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
101
102 /* Local APIC was disabled by the BIOS and enabled by the kernel */
103 static int enabled_via_apicbase;
104
105 /*
106 * Handle interrupt mode configuration register (IMCR).
107 * This register controls whether the interrupt signals
108 * that reach the BSP come from the master PIC or from the
109 * local APIC. Before entering Symmetric I/O Mode, either
110 * the BIOS or the operating system must switch out of
111 * PIC Mode by changing the IMCR.
112 */
imcr_pic_to_apic(void)113 static inline void imcr_pic_to_apic(void)
114 {
115 /* select IMCR register */
116 outb(0x70, 0x22);
117 /* NMI and 8259 INTR go through APIC */
118 outb(0x01, 0x23);
119 }
120
imcr_apic_to_pic(void)121 static inline void imcr_apic_to_pic(void)
122 {
123 /* select IMCR register */
124 outb(0x70, 0x22);
125 /* NMI and 8259 INTR go directly to BSP */
126 outb(0x00, 0x23);
127 }
128 #endif
129
130 /*
131 * Knob to control our willingness to enable the local APIC.
132 *
133 * +1=force-enable
134 */
135 static int force_enable_local_apic __initdata;
136
137 /* Control whether x2APIC mode is enabled or not */
138 static bool nox2apic __initdata;
139
140 /*
141 * APIC command line parameters
142 */
parse_lapic(char * arg)143 static int __init parse_lapic(char *arg)
144 {
145 if (config_enabled(CONFIG_X86_32) && !arg)
146 force_enable_local_apic = 1;
147 else if (arg && !strncmp(arg, "notscdeadline", 13))
148 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
149 return 0;
150 }
151 early_param("lapic", parse_lapic);
152
153 #ifdef CONFIG_X86_64
154 static int apic_calibrate_pmtmr __initdata;
setup_apicpmtimer(char * s)155 static __init int setup_apicpmtimer(char *s)
156 {
157 apic_calibrate_pmtmr = 1;
158 notsc_setup(NULL);
159 return 0;
160 }
161 __setup("apicpmtimer", setup_apicpmtimer);
162 #endif
163
164 int x2apic_mode;
165 #ifdef CONFIG_X86_X2APIC
166 /* x2apic enabled before OS handover */
167 int x2apic_preenabled;
168 static int x2apic_disabled;
setup_nox2apic(char * str)169 static int __init setup_nox2apic(char *str)
170 {
171 if (x2apic_enabled()) {
172 int apicid = native_apic_msr_read(APIC_ID);
173
174 if (apicid >= 255) {
175 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
176 apicid);
177 return 0;
178 }
179
180 pr_warning("x2apic already enabled. will disable it\n");
181 } else
182 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
183
184 nox2apic = true;
185
186 return 0;
187 }
188 early_param("nox2apic", setup_nox2apic);
189 #endif
190
191 unsigned long mp_lapic_addr;
192 int disable_apic;
193 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
194 static int disable_apic_timer __initdata;
195 /* Local APIC timer works in C2 */
196 int local_apic_timer_c2_ok;
197 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
198
199 int first_system_vector = 0xfe;
200
201 /*
202 * Debug level, exported for io_apic.c
203 */
204 unsigned int apic_verbosity;
205
206 int pic_mode;
207
208 /* Have we found an MP table */
209 int smp_found_config;
210
211 static struct resource lapic_resource = {
212 .name = "Local APIC",
213 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
214 };
215
216 unsigned int lapic_timer_frequency = 0;
217
218 static void apic_pm_activate(void);
219
220 static unsigned long apic_phys;
221
222 /*
223 * Get the LAPIC version
224 */
lapic_get_version(void)225 static inline int lapic_get_version(void)
226 {
227 return GET_APIC_VERSION(apic_read(APIC_LVR));
228 }
229
230 /*
231 * Check, if the APIC is integrated or a separate chip
232 */
lapic_is_integrated(void)233 static inline int lapic_is_integrated(void)
234 {
235 #ifdef CONFIG_X86_64
236 return 1;
237 #else
238 return APIC_INTEGRATED(lapic_get_version());
239 #endif
240 }
241
242 /*
243 * Check, whether this is a modern or a first generation APIC
244 */
modern_apic(void)245 static int modern_apic(void)
246 {
247 /* AMD systems use old APIC versions, so check the CPU */
248 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
249 boot_cpu_data.x86 >= 0xf)
250 return 1;
251 return lapic_get_version() >= 0x14;
252 }
253
254 /*
255 * right after this call apic become NOOP driven
256 * so apic->write/read doesn't do anything
257 */
apic_disable(void)258 static void __init apic_disable(void)
259 {
260 pr_info("APIC: switched to apic NOOP\n");
261 apic = &apic_noop;
262 }
263
native_apic_wait_icr_idle(void)264 void native_apic_wait_icr_idle(void)
265 {
266 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
267 cpu_relax();
268 }
269
native_safe_apic_wait_icr_idle(void)270 u32 native_safe_apic_wait_icr_idle(void)
271 {
272 u32 send_status;
273 int timeout;
274
275 timeout = 0;
276 do {
277 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
278 if (!send_status)
279 break;
280 inc_irq_stat(icr_read_retry_count);
281 udelay(100);
282 } while (timeout++ < 1000);
283
284 return send_status;
285 }
286
native_apic_icr_write(u32 low,u32 id)287 void native_apic_icr_write(u32 low, u32 id)
288 {
289 unsigned long flags;
290
291 local_irq_save(flags);
292 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
293 apic_write(APIC_ICR, low);
294 local_irq_restore(flags);
295 }
296
native_apic_icr_read(void)297 u64 native_apic_icr_read(void)
298 {
299 u32 icr1, icr2;
300
301 icr2 = apic_read(APIC_ICR2);
302 icr1 = apic_read(APIC_ICR);
303
304 return icr1 | ((u64)icr2 << 32);
305 }
306
307 #ifdef CONFIG_X86_32
308 /**
309 * get_physical_broadcast - Get number of physical broadcast IDs
310 */
get_physical_broadcast(void)311 int get_physical_broadcast(void)
312 {
313 return modern_apic() ? 0xff : 0xf;
314 }
315 #endif
316
317 /**
318 * lapic_get_maxlvt - get the maximum number of local vector table entries
319 */
lapic_get_maxlvt(void)320 int lapic_get_maxlvt(void)
321 {
322 unsigned int v;
323
324 v = apic_read(APIC_LVR);
325 /*
326 * - we always have APIC integrated on 64bit mode
327 * - 82489DXs do not report # of LVT entries
328 */
329 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
330 }
331
332 /*
333 * Local APIC timer
334 */
335
336 /* Clock divisor */
337 #define APIC_DIVISOR 16
338 #define TSC_DIVISOR 32
339
340 /*
341 * This function sets up the local APIC timer, with a timeout of
342 * 'clocks' APIC bus clock. During calibration we actually call
343 * this function twice on the boot CPU, once with a bogus timeout
344 * value, second time for real. The other (noncalibrating) CPUs
345 * call this function only once, with the real, calibrated value.
346 *
347 * We do reads before writes even if unnecessary, to get around the
348 * P5 APIC double write bug.
349 */
__setup_APIC_LVTT(unsigned int clocks,int oneshot,int irqen)350 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
351 {
352 unsigned int lvtt_value, tmp_value;
353
354 lvtt_value = LOCAL_TIMER_VECTOR;
355 if (!oneshot)
356 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
357 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
358 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
359
360 if (!lapic_is_integrated())
361 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
362
363 if (!irqen)
364 lvtt_value |= APIC_LVT_MASKED;
365
366 apic_write(APIC_LVTT, lvtt_value);
367
368 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
369 /*
370 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
371 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
372 * According to Intel, MFENCE can do the serialization here.
373 */
374 asm volatile("mfence" : : : "memory");
375
376 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
377 return;
378 }
379
380 /*
381 * Divide PICLK by 16
382 */
383 tmp_value = apic_read(APIC_TDCR);
384 apic_write(APIC_TDCR,
385 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
386 APIC_TDR_DIV_16);
387
388 if (!oneshot)
389 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
390 }
391
392 /*
393 * Setup extended LVT, AMD specific
394 *
395 * Software should use the LVT offsets the BIOS provides. The offsets
396 * are determined by the subsystems using it like those for MCE
397 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
398 * are supported. Beginning with family 10h at least 4 offsets are
399 * available.
400 *
401 * Since the offsets must be consistent for all cores, we keep track
402 * of the LVT offsets in software and reserve the offset for the same
403 * vector also to be used on other cores. An offset is freed by
404 * setting the entry to APIC_EILVT_MASKED.
405 *
406 * If the BIOS is right, there should be no conflicts. Otherwise a
407 * "[Firmware Bug]: ..." error message is generated. However, if
408 * software does not properly determines the offsets, it is not
409 * necessarily a BIOS bug.
410 */
411
412 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
413
eilvt_entry_is_changeable(unsigned int old,unsigned int new)414 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
415 {
416 return (old & APIC_EILVT_MASKED)
417 || (new == APIC_EILVT_MASKED)
418 || ((new & ~APIC_EILVT_MASKED) == old);
419 }
420
reserve_eilvt_offset(int offset,unsigned int new)421 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
422 {
423 unsigned int rsvd, vector;
424
425 if (offset >= APIC_EILVT_NR_MAX)
426 return ~0;
427
428 rsvd = atomic_read(&eilvt_offsets[offset]);
429 do {
430 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
431 if (vector && !eilvt_entry_is_changeable(vector, new))
432 /* may not change if vectors are different */
433 return rsvd;
434 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
435 } while (rsvd != new);
436
437 rsvd &= ~APIC_EILVT_MASKED;
438 if (rsvd && rsvd != vector)
439 pr_info("LVT offset %d assigned for vector 0x%02x\n",
440 offset, rsvd);
441
442 return new;
443 }
444
445 /*
446 * If mask=1, the LVT entry does not generate interrupts while mask=0
447 * enables the vector. See also the BKDGs. Must be called with
448 * preemption disabled.
449 */
450
setup_APIC_eilvt(u8 offset,u8 vector,u8 msg_type,u8 mask)451 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
452 {
453 unsigned long reg = APIC_EILVTn(offset);
454 unsigned int new, old, reserved;
455
456 new = (mask << 16) | (msg_type << 8) | vector;
457 old = apic_read(reg);
458 reserved = reserve_eilvt_offset(offset, new);
459
460 if (reserved != new) {
461 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
462 "vector 0x%x, but the register is already in use for "
463 "vector 0x%x on another cpu\n",
464 smp_processor_id(), reg, offset, new, reserved);
465 return -EINVAL;
466 }
467
468 if (!eilvt_entry_is_changeable(old, new)) {
469 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
470 "vector 0x%x, but the register is already in use for "
471 "vector 0x%x on this cpu\n",
472 smp_processor_id(), reg, offset, new, old);
473 return -EBUSY;
474 }
475
476 apic_write(reg, new);
477
478 return 0;
479 }
480 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
481
482 /*
483 * Program the next event, relative to now
484 */
lapic_next_event(unsigned long delta,struct clock_event_device * evt)485 static int lapic_next_event(unsigned long delta,
486 struct clock_event_device *evt)
487 {
488 apic_write(APIC_TMICT, delta);
489 return 0;
490 }
491
lapic_next_deadline(unsigned long delta,struct clock_event_device * evt)492 static int lapic_next_deadline(unsigned long delta,
493 struct clock_event_device *evt)
494 {
495 u64 tsc;
496
497 rdtscll(tsc);
498 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
499 return 0;
500 }
501
502 /*
503 * Setup the lapic timer in periodic or oneshot mode
504 */
lapic_timer_setup(enum clock_event_mode mode,struct clock_event_device * evt)505 static void lapic_timer_setup(enum clock_event_mode mode,
506 struct clock_event_device *evt)
507 {
508 unsigned long flags;
509 unsigned int v;
510
511 /* Lapic used as dummy for broadcast ? */
512 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
513 return;
514
515 local_irq_save(flags);
516
517 switch (mode) {
518 case CLOCK_EVT_MODE_PERIODIC:
519 case CLOCK_EVT_MODE_ONESHOT:
520 __setup_APIC_LVTT(lapic_timer_frequency,
521 mode != CLOCK_EVT_MODE_PERIODIC, 1);
522 break;
523 case CLOCK_EVT_MODE_UNUSED:
524 case CLOCK_EVT_MODE_SHUTDOWN:
525 v = apic_read(APIC_LVTT);
526 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
527 apic_write(APIC_LVTT, v);
528 apic_write(APIC_TMICT, 0);
529 break;
530 case CLOCK_EVT_MODE_RESUME:
531 /* Nothing to do here */
532 break;
533 }
534
535 local_irq_restore(flags);
536 }
537
538 /*
539 * Local APIC timer broadcast function
540 */
lapic_timer_broadcast(const struct cpumask * mask)541 static void lapic_timer_broadcast(const struct cpumask *mask)
542 {
543 #ifdef CONFIG_SMP
544 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
545 #endif
546 }
547
548
549 /*
550 * The local apic timer can be used for any function which is CPU local.
551 */
552 static struct clock_event_device lapic_clockevent = {
553 .name = "lapic",
554 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
555 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
556 .shift = 32,
557 .set_mode = lapic_timer_setup,
558 .set_next_event = lapic_next_event,
559 .broadcast = lapic_timer_broadcast,
560 .rating = 100,
561 .irq = -1,
562 };
563 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
564
565 /*
566 * Setup the local APIC timer for this CPU. Copy the initialized values
567 * of the boot CPU and register the clock event in the framework.
568 */
setup_APIC_timer(void)569 static void setup_APIC_timer(void)
570 {
571 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
572
573 if (this_cpu_has(X86_FEATURE_ARAT)) {
574 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
575 /* Make LAPIC timer preferrable over percpu HPET */
576 lapic_clockevent.rating = 150;
577 }
578
579 memcpy(levt, &lapic_clockevent, sizeof(*levt));
580 levt->cpumask = cpumask_of(smp_processor_id());
581
582 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
583 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
584 CLOCK_EVT_FEAT_DUMMY);
585 levt->set_next_event = lapic_next_deadline;
586 clockevents_config_and_register(levt,
587 (tsc_khz / TSC_DIVISOR) * 1000,
588 0xF, ~0UL);
589 } else
590 clockevents_register_device(levt);
591 }
592
593 /*
594 * In this functions we calibrate APIC bus clocks to the external timer.
595 *
596 * We want to do the calibration only once since we want to have local timer
597 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
598 * frequency.
599 *
600 * This was previously done by reading the PIT/HPET and waiting for a wrap
601 * around to find out, that a tick has elapsed. I have a box, where the PIT
602 * readout is broken, so it never gets out of the wait loop again. This was
603 * also reported by others.
604 *
605 * Monitoring the jiffies value is inaccurate and the clockevents
606 * infrastructure allows us to do a simple substitution of the interrupt
607 * handler.
608 *
609 * The calibration routine also uses the pm_timer when possible, as the PIT
610 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
611 * back to normal later in the boot process).
612 */
613
614 #define LAPIC_CAL_LOOPS (HZ/10)
615
616 static __initdata int lapic_cal_loops = -1;
617 static __initdata long lapic_cal_t1, lapic_cal_t2;
618 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
619 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
620 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
621
622 /*
623 * Temporary interrupt handler.
624 */
lapic_cal_handler(struct clock_event_device * dev)625 static void __init lapic_cal_handler(struct clock_event_device *dev)
626 {
627 unsigned long long tsc = 0;
628 long tapic = apic_read(APIC_TMCCT);
629 unsigned long pm = acpi_pm_read_early();
630
631 if (cpu_has_tsc)
632 rdtscll(tsc);
633
634 switch (lapic_cal_loops++) {
635 case 0:
636 lapic_cal_t1 = tapic;
637 lapic_cal_tsc1 = tsc;
638 lapic_cal_pm1 = pm;
639 lapic_cal_j1 = jiffies;
640 break;
641
642 case LAPIC_CAL_LOOPS:
643 lapic_cal_t2 = tapic;
644 lapic_cal_tsc2 = tsc;
645 if (pm < lapic_cal_pm1)
646 pm += ACPI_PM_OVRRUN;
647 lapic_cal_pm2 = pm;
648 lapic_cal_j2 = jiffies;
649 break;
650 }
651 }
652
653 static int __init
calibrate_by_pmtimer(long deltapm,long * delta,long * deltatsc)654 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
655 {
656 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
657 const long pm_thresh = pm_100ms / 100;
658 unsigned long mult;
659 u64 res;
660
661 #ifndef CONFIG_X86_PM_TIMER
662 return -1;
663 #endif
664
665 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
666
667 /* Check, if the PM timer is available */
668 if (!deltapm)
669 return -1;
670
671 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
672
673 if (deltapm > (pm_100ms - pm_thresh) &&
674 deltapm < (pm_100ms + pm_thresh)) {
675 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
676 return 0;
677 }
678
679 res = (((u64)deltapm) * mult) >> 22;
680 do_div(res, 1000000);
681 pr_warning("APIC calibration not consistent "
682 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
683
684 /* Correct the lapic counter value */
685 res = (((u64)(*delta)) * pm_100ms);
686 do_div(res, deltapm);
687 pr_info("APIC delta adjusted to PM-Timer: "
688 "%lu (%ld)\n", (unsigned long)res, *delta);
689 *delta = (long)res;
690
691 /* Correct the tsc counter value */
692 if (cpu_has_tsc) {
693 res = (((u64)(*deltatsc)) * pm_100ms);
694 do_div(res, deltapm);
695 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
696 "PM-Timer: %lu (%ld)\n",
697 (unsigned long)res, *deltatsc);
698 *deltatsc = (long)res;
699 }
700
701 return 0;
702 }
703
calibrate_APIC_clock(void)704 static int __init calibrate_APIC_clock(void)
705 {
706 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
707 void (*real_handler)(struct clock_event_device *dev);
708 unsigned long deltaj;
709 long delta, deltatsc;
710 int pm_referenced = 0;
711
712 /**
713 * check if lapic timer has already been calibrated by platform
714 * specific routine, such as tsc calibration code. if so, we just fill
715 * in the clockevent structure and return.
716 */
717
718 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
719 return 0;
720 } else if (lapic_timer_frequency) {
721 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
722 lapic_timer_frequency);
723 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
724 TICK_NSEC, lapic_clockevent.shift);
725 lapic_clockevent.max_delta_ns =
726 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
727 lapic_clockevent.min_delta_ns =
728 clockevent_delta2ns(0xF, &lapic_clockevent);
729 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
730 return 0;
731 }
732
733 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
734 "calibrating APIC timer ...\n");
735
736 local_irq_disable();
737
738 /* Replace the global interrupt handler */
739 real_handler = global_clock_event->event_handler;
740 global_clock_event->event_handler = lapic_cal_handler;
741
742 /*
743 * Setup the APIC counter to maximum. There is no way the lapic
744 * can underflow in the 100ms detection time frame
745 */
746 __setup_APIC_LVTT(0xffffffff, 0, 0);
747
748 /* Let the interrupts run */
749 local_irq_enable();
750
751 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
752 cpu_relax();
753
754 local_irq_disable();
755
756 /* Restore the real event handler */
757 global_clock_event->event_handler = real_handler;
758
759 /* Build delta t1-t2 as apic timer counts down */
760 delta = lapic_cal_t1 - lapic_cal_t2;
761 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
762
763 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
764
765 /* we trust the PM based calibration if possible */
766 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
767 &delta, &deltatsc);
768
769 /* Calculate the scaled math multiplication factor */
770 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
771 lapic_clockevent.shift);
772 lapic_clockevent.max_delta_ns =
773 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
774 lapic_clockevent.min_delta_ns =
775 clockevent_delta2ns(0xF, &lapic_clockevent);
776
777 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
778
779 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
780 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
781 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
782 lapic_timer_frequency);
783
784 if (cpu_has_tsc) {
785 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
786 "%ld.%04ld MHz.\n",
787 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
788 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
789 }
790
791 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
792 "%u.%04u MHz.\n",
793 lapic_timer_frequency / (1000000 / HZ),
794 lapic_timer_frequency % (1000000 / HZ));
795
796 /*
797 * Do a sanity check on the APIC calibration result
798 */
799 if (lapic_timer_frequency < (1000000 / HZ)) {
800 local_irq_enable();
801 pr_warning("APIC frequency too slow, disabling apic timer\n");
802 return -1;
803 }
804
805 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
806
807 /*
808 * PM timer calibration failed or not turned on
809 * so lets try APIC timer based calibration
810 */
811 if (!pm_referenced) {
812 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
813
814 /*
815 * Setup the apic timer manually
816 */
817 levt->event_handler = lapic_cal_handler;
818 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
819 lapic_cal_loops = -1;
820
821 /* Let the interrupts run */
822 local_irq_enable();
823
824 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
825 cpu_relax();
826
827 /* Stop the lapic timer */
828 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
829
830 /* Jiffies delta */
831 deltaj = lapic_cal_j2 - lapic_cal_j1;
832 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
833
834 /* Check, if the jiffies result is consistent */
835 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
836 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
837 else
838 levt->features |= CLOCK_EVT_FEAT_DUMMY;
839 } else
840 local_irq_enable();
841
842 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
843 pr_warning("APIC timer disabled due to verification failure\n");
844 return -1;
845 }
846
847 return 0;
848 }
849
850 /*
851 * Setup the boot APIC
852 *
853 * Calibrate and verify the result.
854 */
setup_boot_APIC_clock(void)855 void __init setup_boot_APIC_clock(void)
856 {
857 /*
858 * The local apic timer can be disabled via the kernel
859 * commandline or from the CPU detection code. Register the lapic
860 * timer as a dummy clock event source on SMP systems, so the
861 * broadcast mechanism is used. On UP systems simply ignore it.
862 */
863 if (disable_apic_timer) {
864 pr_info("Disabling APIC timer\n");
865 /* No broadcast on UP ! */
866 if (num_possible_cpus() > 1) {
867 lapic_clockevent.mult = 1;
868 setup_APIC_timer();
869 }
870 return;
871 }
872
873 if (calibrate_APIC_clock()) {
874 /* No broadcast on UP ! */
875 if (num_possible_cpus() > 1)
876 setup_APIC_timer();
877 return;
878 }
879
880 /*
881 * If nmi_watchdog is set to IO_APIC, we need the
882 * PIT/HPET going. Otherwise register lapic as a dummy
883 * device.
884 */
885 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
886
887 /* Setup the lapic or request the broadcast */
888 setup_APIC_timer();
889 }
890
setup_secondary_APIC_clock(void)891 void setup_secondary_APIC_clock(void)
892 {
893 setup_APIC_timer();
894 }
895
896 /*
897 * The guts of the apic timer interrupt
898 */
local_apic_timer_interrupt(void)899 static void local_apic_timer_interrupt(void)
900 {
901 int cpu = smp_processor_id();
902 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
903
904 /*
905 * Normally we should not be here till LAPIC has been initialized but
906 * in some cases like kdump, its possible that there is a pending LAPIC
907 * timer interrupt from previous kernel's context and is delivered in
908 * new kernel the moment interrupts are enabled.
909 *
910 * Interrupts are enabled early and LAPIC is setup much later, hence
911 * its possible that when we get here evt->event_handler is NULL.
912 * Check for event_handler being NULL and discard the interrupt as
913 * spurious.
914 */
915 if (!evt->event_handler) {
916 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
917 /* Switch it off */
918 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
919 return;
920 }
921
922 /*
923 * the NMI deadlock-detector uses this.
924 */
925 inc_irq_stat(apic_timer_irqs);
926
927 evt->event_handler(evt);
928 }
929
930 /*
931 * Local APIC timer interrupt. This is the most natural way for doing
932 * local interrupts, but local timer interrupts can be emulated by
933 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
934 *
935 * [ if a single-CPU system runs an SMP kernel then we call the local
936 * interrupt as well. Thus we cannot inline the local irq ... ]
937 */
smp_apic_timer_interrupt(struct pt_regs * regs)938 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
939 {
940 struct pt_regs *old_regs = set_irq_regs(regs);
941
942 /*
943 * NOTE! We'd better ACK the irq immediately,
944 * because timer handling can be slow.
945 *
946 * update_process_times() expects us to have done irq_enter().
947 * Besides, if we don't timer interrupts ignore the global
948 * interrupt lock, which is the WrongThing (tm) to do.
949 */
950 entering_ack_irq();
951 local_apic_timer_interrupt();
952 exiting_irq();
953
954 set_irq_regs(old_regs);
955 }
956
smp_trace_apic_timer_interrupt(struct pt_regs * regs)957 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
958 {
959 struct pt_regs *old_regs = set_irq_regs(regs);
960
961 /*
962 * NOTE! We'd better ACK the irq immediately,
963 * because timer handling can be slow.
964 *
965 * update_process_times() expects us to have done irq_enter().
966 * Besides, if we don't timer interrupts ignore the global
967 * interrupt lock, which is the WrongThing (tm) to do.
968 */
969 entering_ack_irq();
970 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
971 local_apic_timer_interrupt();
972 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
973 exiting_irq();
974
975 set_irq_regs(old_regs);
976 }
977
setup_profiling_timer(unsigned int multiplier)978 int setup_profiling_timer(unsigned int multiplier)
979 {
980 return -EINVAL;
981 }
982
983 /*
984 * Local APIC start and shutdown
985 */
986
987 /**
988 * clear_local_APIC - shutdown the local APIC
989 *
990 * This is called, when a CPU is disabled and before rebooting, so the state of
991 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
992 * leftovers during boot.
993 */
clear_local_APIC(void)994 void clear_local_APIC(void)
995 {
996 int maxlvt;
997 u32 v;
998
999 /* APIC hasn't been mapped yet */
1000 if (!x2apic_mode && !apic_phys)
1001 return;
1002
1003 maxlvt = lapic_get_maxlvt();
1004 /*
1005 * Masking an LVT entry can trigger a local APIC error
1006 * if the vector is zero. Mask LVTERR first to prevent this.
1007 */
1008 if (maxlvt >= 3) {
1009 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1010 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1011 }
1012 /*
1013 * Careful: we have to set masks only first to deassert
1014 * any level-triggered sources.
1015 */
1016 v = apic_read(APIC_LVTT);
1017 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1018 v = apic_read(APIC_LVT0);
1019 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1020 v = apic_read(APIC_LVT1);
1021 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1022 if (maxlvt >= 4) {
1023 v = apic_read(APIC_LVTPC);
1024 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1025 }
1026
1027 /* lets not touch this if we didn't frob it */
1028 #ifdef CONFIG_X86_THERMAL_VECTOR
1029 if (maxlvt >= 5) {
1030 v = apic_read(APIC_LVTTHMR);
1031 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1032 }
1033 #endif
1034 #ifdef CONFIG_X86_MCE_INTEL
1035 if (maxlvt >= 6) {
1036 v = apic_read(APIC_LVTCMCI);
1037 if (!(v & APIC_LVT_MASKED))
1038 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1039 }
1040 #endif
1041
1042 /*
1043 * Clean APIC state for other OSs:
1044 */
1045 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1046 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1047 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1048 if (maxlvt >= 3)
1049 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1050 if (maxlvt >= 4)
1051 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1052
1053 /* Integrated APIC (!82489DX) ? */
1054 if (lapic_is_integrated()) {
1055 if (maxlvt > 3)
1056 /* Clear ESR due to Pentium errata 3AP and 11AP */
1057 apic_write(APIC_ESR, 0);
1058 apic_read(APIC_ESR);
1059 }
1060 }
1061
1062 /**
1063 * disable_local_APIC - clear and disable the local APIC
1064 */
disable_local_APIC(void)1065 void disable_local_APIC(void)
1066 {
1067 unsigned int value;
1068
1069 /* APIC hasn't been mapped yet */
1070 if (!x2apic_mode && !apic_phys)
1071 return;
1072
1073 clear_local_APIC();
1074
1075 /*
1076 * Disable APIC (implies clearing of registers
1077 * for 82489DX!).
1078 */
1079 value = apic_read(APIC_SPIV);
1080 value &= ~APIC_SPIV_APIC_ENABLED;
1081 apic_write(APIC_SPIV, value);
1082
1083 #ifdef CONFIG_X86_32
1084 /*
1085 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1086 * restore the disabled state.
1087 */
1088 if (enabled_via_apicbase) {
1089 unsigned int l, h;
1090
1091 rdmsr(MSR_IA32_APICBASE, l, h);
1092 l &= ~MSR_IA32_APICBASE_ENABLE;
1093 wrmsr(MSR_IA32_APICBASE, l, h);
1094 }
1095 #endif
1096 }
1097
1098 /*
1099 * If Linux enabled the LAPIC against the BIOS default disable it down before
1100 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1101 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1102 * for the case where Linux didn't enable the LAPIC.
1103 */
lapic_shutdown(void)1104 void lapic_shutdown(void)
1105 {
1106 unsigned long flags;
1107
1108 if (!cpu_has_apic && !apic_from_smp_config())
1109 return;
1110
1111 local_irq_save(flags);
1112
1113 #ifdef CONFIG_X86_32
1114 if (!enabled_via_apicbase)
1115 clear_local_APIC();
1116 else
1117 #endif
1118 disable_local_APIC();
1119
1120
1121 local_irq_restore(flags);
1122 }
1123
1124 /*
1125 * This is to verify that we're looking at a real local APIC.
1126 * Check these against your board if the CPUs aren't getting
1127 * started for no apparent reason.
1128 */
verify_local_APIC(void)1129 int __init verify_local_APIC(void)
1130 {
1131 unsigned int reg0, reg1;
1132
1133 /*
1134 * The version register is read-only in a real APIC.
1135 */
1136 reg0 = apic_read(APIC_LVR);
1137 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1138 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1139 reg1 = apic_read(APIC_LVR);
1140 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1141
1142 /*
1143 * The two version reads above should print the same
1144 * numbers. If the second one is different, then we
1145 * poke at a non-APIC.
1146 */
1147 if (reg1 != reg0)
1148 return 0;
1149
1150 /*
1151 * Check if the version looks reasonably.
1152 */
1153 reg1 = GET_APIC_VERSION(reg0);
1154 if (reg1 == 0x00 || reg1 == 0xff)
1155 return 0;
1156 reg1 = lapic_get_maxlvt();
1157 if (reg1 < 0x02 || reg1 == 0xff)
1158 return 0;
1159
1160 /*
1161 * The ID register is read/write in a real APIC.
1162 */
1163 reg0 = apic_read(APIC_ID);
1164 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1165 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1166 reg1 = apic_read(APIC_ID);
1167 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1168 apic_write(APIC_ID, reg0);
1169 if (reg1 != (reg0 ^ apic->apic_id_mask))
1170 return 0;
1171
1172 /*
1173 * The next two are just to see if we have sane values.
1174 * They're only really relevant if we're in Virtual Wire
1175 * compatibility mode, but most boxes are anymore.
1176 */
1177 reg0 = apic_read(APIC_LVT0);
1178 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1179 reg1 = apic_read(APIC_LVT1);
1180 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1181
1182 return 1;
1183 }
1184
1185 /**
1186 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1187 */
sync_Arb_IDs(void)1188 void __init sync_Arb_IDs(void)
1189 {
1190 /*
1191 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1192 * needed on AMD.
1193 */
1194 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1195 return;
1196
1197 /*
1198 * Wait for idle.
1199 */
1200 apic_wait_icr_idle();
1201
1202 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1203 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1204 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1205 }
1206
1207 /*
1208 * An initial setup of the virtual wire mode.
1209 */
init_bsp_APIC(void)1210 void __init init_bsp_APIC(void)
1211 {
1212 unsigned int value;
1213
1214 /*
1215 * Don't do the setup now if we have a SMP BIOS as the
1216 * through-I/O-APIC virtual wire mode might be active.
1217 */
1218 if (smp_found_config || !cpu_has_apic)
1219 return;
1220
1221 /*
1222 * Do not trust the local APIC being empty at bootup.
1223 */
1224 clear_local_APIC();
1225
1226 /*
1227 * Enable APIC.
1228 */
1229 value = apic_read(APIC_SPIV);
1230 value &= ~APIC_VECTOR_MASK;
1231 value |= APIC_SPIV_APIC_ENABLED;
1232
1233 #ifdef CONFIG_X86_32
1234 /* This bit is reserved on P4/Xeon and should be cleared */
1235 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1236 (boot_cpu_data.x86 == 15))
1237 value &= ~APIC_SPIV_FOCUS_DISABLED;
1238 else
1239 #endif
1240 value |= APIC_SPIV_FOCUS_DISABLED;
1241 value |= SPURIOUS_APIC_VECTOR;
1242 apic_write(APIC_SPIV, value);
1243
1244 /*
1245 * Set up the virtual wire mode.
1246 */
1247 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1248 value = APIC_DM_NMI;
1249 if (!lapic_is_integrated()) /* 82489DX */
1250 value |= APIC_LVT_LEVEL_TRIGGER;
1251 apic_write(APIC_LVT1, value);
1252 }
1253
lapic_setup_esr(void)1254 static void lapic_setup_esr(void)
1255 {
1256 unsigned int oldvalue, value, maxlvt;
1257
1258 if (!lapic_is_integrated()) {
1259 pr_info("No ESR for 82489DX.\n");
1260 return;
1261 }
1262
1263 if (apic->disable_esr) {
1264 /*
1265 * Something untraceable is creating bad interrupts on
1266 * secondary quads ... for the moment, just leave the
1267 * ESR disabled - we can't do anything useful with the
1268 * errors anyway - mbligh
1269 */
1270 pr_info("Leaving ESR disabled.\n");
1271 return;
1272 }
1273
1274 maxlvt = lapic_get_maxlvt();
1275 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1276 apic_write(APIC_ESR, 0);
1277 oldvalue = apic_read(APIC_ESR);
1278
1279 /* enables sending errors */
1280 value = ERROR_APIC_VECTOR;
1281 apic_write(APIC_LVTERR, value);
1282
1283 /*
1284 * spec says clear errors after enabling vector.
1285 */
1286 if (maxlvt > 3)
1287 apic_write(APIC_ESR, 0);
1288 value = apic_read(APIC_ESR);
1289 if (value != oldvalue)
1290 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1291 "vector: 0x%08x after: 0x%08x\n",
1292 oldvalue, value);
1293 }
1294
1295 /**
1296 * setup_local_APIC - setup the local APIC
1297 *
1298 * Used to setup local APIC while initializing BSP or bringin up APs.
1299 * Always called with preemption disabled.
1300 */
setup_local_APIC(void)1301 void setup_local_APIC(void)
1302 {
1303 int cpu = smp_processor_id();
1304 unsigned int value, queued;
1305 int i, j, acked = 0;
1306 unsigned long long tsc = 0, ntsc;
1307 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1308
1309 if (cpu_has_tsc)
1310 rdtscll(tsc);
1311
1312 if (disable_apic) {
1313 disable_ioapic_support();
1314 return;
1315 }
1316
1317 #ifdef CONFIG_X86_32
1318 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1319 if (lapic_is_integrated() && apic->disable_esr) {
1320 apic_write(APIC_ESR, 0);
1321 apic_write(APIC_ESR, 0);
1322 apic_write(APIC_ESR, 0);
1323 apic_write(APIC_ESR, 0);
1324 }
1325 #endif
1326 perf_events_lapic_init();
1327
1328 /*
1329 * Double-check whether this APIC is really registered.
1330 * This is meaningless in clustered apic mode, so we skip it.
1331 */
1332 BUG_ON(!apic->apic_id_registered());
1333
1334 /*
1335 * Intel recommends to set DFR, LDR and TPR before enabling
1336 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1337 * document number 292116). So here it goes...
1338 */
1339 apic->init_apic_ldr();
1340
1341 #ifdef CONFIG_X86_32
1342 /*
1343 * APIC LDR is initialized. If logical_apicid mapping was
1344 * initialized during get_smp_config(), make sure it matches the
1345 * actual value.
1346 */
1347 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1348 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1349 /* always use the value from LDR */
1350 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1351 logical_smp_processor_id();
1352 #endif
1353
1354 /*
1355 * Set Task Priority to 'accept all'. We never change this
1356 * later on.
1357 */
1358 value = apic_read(APIC_TASKPRI);
1359 value &= ~APIC_TPRI_MASK;
1360 apic_write(APIC_TASKPRI, value);
1361
1362 /*
1363 * After a crash, we no longer service the interrupts and a pending
1364 * interrupt from previous kernel might still have ISR bit set.
1365 *
1366 * Most probably by now CPU has serviced that pending interrupt and
1367 * it might not have done the ack_APIC_irq() because it thought,
1368 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1369 * does not clear the ISR bit and cpu thinks it has already serivced
1370 * the interrupt. Hence a vector might get locked. It was noticed
1371 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1372 */
1373 do {
1374 queued = 0;
1375 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1376 queued |= apic_read(APIC_IRR + i*0x10);
1377
1378 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1379 value = apic_read(APIC_ISR + i*0x10);
1380 for (j = 31; j >= 0; j--) {
1381 if (value & (1<<j)) {
1382 ack_APIC_irq();
1383 acked++;
1384 }
1385 }
1386 }
1387 if (acked > 256) {
1388 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1389 acked);
1390 break;
1391 }
1392 if (queued) {
1393 if (cpu_has_tsc && cpu_khz) {
1394 rdtscll(ntsc);
1395 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1396 } else
1397 max_loops--;
1398 }
1399 } while (queued && max_loops > 0);
1400 WARN_ON(max_loops <= 0);
1401
1402 /*
1403 * Now that we are all set up, enable the APIC
1404 */
1405 value = apic_read(APIC_SPIV);
1406 value &= ~APIC_VECTOR_MASK;
1407 /*
1408 * Enable APIC
1409 */
1410 value |= APIC_SPIV_APIC_ENABLED;
1411
1412 #ifdef CONFIG_X86_32
1413 /*
1414 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1415 * certain networking cards. If high frequency interrupts are
1416 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1417 * entry is masked/unmasked at a high rate as well then sooner or
1418 * later IOAPIC line gets 'stuck', no more interrupts are received
1419 * from the device. If focus CPU is disabled then the hang goes
1420 * away, oh well :-(
1421 *
1422 * [ This bug can be reproduced easily with a level-triggered
1423 * PCI Ne2000 networking cards and PII/PIII processors, dual
1424 * BX chipset. ]
1425 */
1426 /*
1427 * Actually disabling the focus CPU check just makes the hang less
1428 * frequent as it makes the interrupt distributon model be more
1429 * like LRU than MRU (the short-term load is more even across CPUs).
1430 * See also the comment in end_level_ioapic_irq(). --macro
1431 */
1432
1433 /*
1434 * - enable focus processor (bit==0)
1435 * - 64bit mode always use processor focus
1436 * so no need to set it
1437 */
1438 value &= ~APIC_SPIV_FOCUS_DISABLED;
1439 #endif
1440
1441 /*
1442 * Set spurious IRQ vector
1443 */
1444 value |= SPURIOUS_APIC_VECTOR;
1445 apic_write(APIC_SPIV, value);
1446
1447 /*
1448 * Set up LVT0, LVT1:
1449 *
1450 * set up through-local-APIC on the BP's LINT0. This is not
1451 * strictly necessary in pure symmetric-IO mode, but sometimes
1452 * we delegate interrupts to the 8259A.
1453 */
1454 /*
1455 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1456 */
1457 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1458 if (!cpu && (pic_mode || !value)) {
1459 value = APIC_DM_EXTINT;
1460 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1461 } else {
1462 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1463 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1464 }
1465 apic_write(APIC_LVT0, value);
1466
1467 /*
1468 * only the BP should see the LINT1 NMI signal, obviously.
1469 */
1470 if (!cpu)
1471 value = APIC_DM_NMI;
1472 else
1473 value = APIC_DM_NMI | APIC_LVT_MASKED;
1474 if (!lapic_is_integrated()) /* 82489DX */
1475 value |= APIC_LVT_LEVEL_TRIGGER;
1476 apic_write(APIC_LVT1, value);
1477
1478 #ifdef CONFIG_X86_MCE_INTEL
1479 /* Recheck CMCI information after local APIC is up on CPU #0 */
1480 if (!cpu)
1481 cmci_recheck();
1482 #endif
1483 }
1484
end_local_APIC_setup(void)1485 void end_local_APIC_setup(void)
1486 {
1487 lapic_setup_esr();
1488
1489 #ifdef CONFIG_X86_32
1490 {
1491 unsigned int value;
1492 /* Disable the local apic timer */
1493 value = apic_read(APIC_LVTT);
1494 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1495 apic_write(APIC_LVTT, value);
1496 }
1497 #endif
1498
1499 apic_pm_activate();
1500 }
1501
bsp_end_local_APIC_setup(void)1502 void __init bsp_end_local_APIC_setup(void)
1503 {
1504 end_local_APIC_setup();
1505
1506 /*
1507 * Now that local APIC setup is completed for BP, configure the fault
1508 * handling for interrupt remapping.
1509 */
1510 irq_remap_enable_fault_handling();
1511
1512 }
1513
1514 #ifdef CONFIG_X86_X2APIC
1515 /*
1516 * Need to disable xapic and x2apic at the same time and then enable xapic mode
1517 */
__disable_x2apic(u64 msr)1518 static inline void __disable_x2apic(u64 msr)
1519 {
1520 wrmsrl(MSR_IA32_APICBASE,
1521 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1522 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1523 }
1524
disable_x2apic(void)1525 static __init void disable_x2apic(void)
1526 {
1527 u64 msr;
1528
1529 if (!cpu_has_x2apic)
1530 return;
1531
1532 rdmsrl(MSR_IA32_APICBASE, msr);
1533 if (msr & X2APIC_ENABLE) {
1534 u32 x2apic_id = read_apic_id();
1535
1536 if (x2apic_id >= 255)
1537 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1538
1539 pr_info("Disabling x2apic\n");
1540 __disable_x2apic(msr);
1541
1542 if (nox2apic) {
1543 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1544 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1545 }
1546
1547 x2apic_disabled = 1;
1548 x2apic_mode = 0;
1549
1550 register_lapic_address(mp_lapic_addr);
1551 }
1552 }
1553
check_x2apic(void)1554 void check_x2apic(void)
1555 {
1556 if (x2apic_enabled()) {
1557 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1558 x2apic_preenabled = x2apic_mode = 1;
1559 }
1560 }
1561
enable_x2apic(void)1562 void enable_x2apic(void)
1563 {
1564 u64 msr;
1565
1566 rdmsrl(MSR_IA32_APICBASE, msr);
1567 if (x2apic_disabled) {
1568 __disable_x2apic(msr);
1569 return;
1570 }
1571
1572 if (!x2apic_mode)
1573 return;
1574
1575 if (!(msr & X2APIC_ENABLE)) {
1576 printk_once(KERN_INFO "Enabling x2apic\n");
1577 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1578 }
1579 }
1580 #endif /* CONFIG_X86_X2APIC */
1581
enable_IR(void)1582 int __init enable_IR(void)
1583 {
1584 #ifdef CONFIG_IRQ_REMAP
1585 if (!irq_remapping_supported()) {
1586 pr_debug("intr-remapping not supported\n");
1587 return -1;
1588 }
1589
1590 if (!x2apic_preenabled && skip_ioapic_setup) {
1591 pr_info("Skipped enabling intr-remap because of skipping "
1592 "io-apic setup\n");
1593 return -1;
1594 }
1595
1596 return irq_remapping_enable();
1597 #endif
1598 return -1;
1599 }
1600
enable_IR_x2apic(void)1601 void __init enable_IR_x2apic(void)
1602 {
1603 unsigned long flags;
1604 int ret, x2apic_enabled = 0;
1605 int hardware_init_ret;
1606
1607 /* Make sure irq_remap_ops are initialized */
1608 setup_irq_remapping_ops();
1609
1610 hardware_init_ret = irq_remapping_prepare();
1611 if (hardware_init_ret && !x2apic_supported())
1612 return;
1613
1614 ret = save_ioapic_entries();
1615 if (ret) {
1616 pr_info("Saving IO-APIC state failed: %d\n", ret);
1617 return;
1618 }
1619
1620 local_irq_save(flags);
1621 legacy_pic->mask_all();
1622 mask_ioapic_entries();
1623
1624 if (x2apic_preenabled && nox2apic)
1625 disable_x2apic();
1626
1627 if (hardware_init_ret)
1628 ret = -1;
1629 else
1630 ret = enable_IR();
1631
1632 if (!x2apic_supported())
1633 goto skip_x2apic;
1634
1635 if (ret < 0) {
1636 /* IR is required if there is APIC ID > 255 even when running
1637 * under KVM
1638 */
1639 if (max_physical_apicid > 255 ||
1640 !hypervisor_x2apic_available()) {
1641 if (x2apic_preenabled)
1642 disable_x2apic();
1643 goto skip_x2apic;
1644 }
1645 /*
1646 * without IR all CPUs can be addressed by IOAPIC/MSI
1647 * only in physical mode
1648 */
1649 x2apic_force_phys();
1650 }
1651
1652 if (ret == IRQ_REMAP_XAPIC_MODE) {
1653 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1654 goto skip_x2apic;
1655 }
1656
1657 x2apic_enabled = 1;
1658
1659 if (x2apic_supported() && !x2apic_mode) {
1660 x2apic_mode = 1;
1661 enable_x2apic();
1662 pr_info("Enabled x2apic\n");
1663 }
1664
1665 skip_x2apic:
1666 if (ret < 0) /* IR enabling failed */
1667 restore_ioapic_entries();
1668 legacy_pic->restore_mask();
1669 local_irq_restore(flags);
1670 }
1671
1672 #ifdef CONFIG_X86_64
1673 /*
1674 * Detect and enable local APICs on non-SMP boards.
1675 * Original code written by Keir Fraser.
1676 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1677 * not correctly set up (usually the APIC timer won't work etc.)
1678 */
detect_init_APIC(void)1679 static int __init detect_init_APIC(void)
1680 {
1681 if (!cpu_has_apic) {
1682 pr_info("No local APIC present\n");
1683 return -1;
1684 }
1685
1686 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1687 return 0;
1688 }
1689 #else
1690
apic_verify(void)1691 static int __init apic_verify(void)
1692 {
1693 u32 features, h, l;
1694
1695 /*
1696 * The APIC feature bit should now be enabled
1697 * in `cpuid'
1698 */
1699 features = cpuid_edx(1);
1700 if (!(features & (1 << X86_FEATURE_APIC))) {
1701 pr_warning("Could not enable APIC!\n");
1702 return -1;
1703 }
1704 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1705 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1706
1707 /* The BIOS may have set up the APIC at some other address */
1708 if (boot_cpu_data.x86 >= 6) {
1709 rdmsr(MSR_IA32_APICBASE, l, h);
1710 if (l & MSR_IA32_APICBASE_ENABLE)
1711 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1712 }
1713
1714 pr_info("Found and enabled local APIC!\n");
1715 return 0;
1716 }
1717
apic_force_enable(unsigned long addr)1718 int __init apic_force_enable(unsigned long addr)
1719 {
1720 u32 h, l;
1721
1722 if (disable_apic)
1723 return -1;
1724
1725 /*
1726 * Some BIOSes disable the local APIC in the APIC_BASE
1727 * MSR. This can only be done in software for Intel P6 or later
1728 * and AMD K7 (Model > 1) or later.
1729 */
1730 if (boot_cpu_data.x86 >= 6) {
1731 rdmsr(MSR_IA32_APICBASE, l, h);
1732 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1733 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1734 l &= ~MSR_IA32_APICBASE_BASE;
1735 l |= MSR_IA32_APICBASE_ENABLE | addr;
1736 wrmsr(MSR_IA32_APICBASE, l, h);
1737 enabled_via_apicbase = 1;
1738 }
1739 }
1740 return apic_verify();
1741 }
1742
1743 /*
1744 * Detect and initialize APIC
1745 */
detect_init_APIC(void)1746 static int __init detect_init_APIC(void)
1747 {
1748 /* Disabled by kernel option? */
1749 if (disable_apic)
1750 return -1;
1751
1752 switch (boot_cpu_data.x86_vendor) {
1753 case X86_VENDOR_AMD:
1754 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1755 (boot_cpu_data.x86 >= 15))
1756 break;
1757 goto no_apic;
1758 case X86_VENDOR_INTEL:
1759 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1760 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1761 break;
1762 goto no_apic;
1763 default:
1764 goto no_apic;
1765 }
1766
1767 if (!cpu_has_apic) {
1768 /*
1769 * Over-ride BIOS and try to enable the local APIC only if
1770 * "lapic" specified.
1771 */
1772 if (!force_enable_local_apic) {
1773 pr_info("Local APIC disabled by BIOS -- "
1774 "you can enable it with \"lapic\"\n");
1775 return -1;
1776 }
1777 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1778 return -1;
1779 } else {
1780 if (apic_verify())
1781 return -1;
1782 }
1783
1784 apic_pm_activate();
1785
1786 return 0;
1787
1788 no_apic:
1789 pr_info("No local APIC present or hardware disabled\n");
1790 return -1;
1791 }
1792 #endif
1793
1794 /**
1795 * init_apic_mappings - initialize APIC mappings
1796 */
init_apic_mappings(void)1797 void __init init_apic_mappings(void)
1798 {
1799 unsigned int new_apicid;
1800
1801 if (x2apic_mode) {
1802 boot_cpu_physical_apicid = read_apic_id();
1803 return;
1804 }
1805
1806 /* If no local APIC can be found return early */
1807 if (!smp_found_config && detect_init_APIC()) {
1808 /* lets NOP'ify apic operations */
1809 pr_info("APIC: disable apic facility\n");
1810 apic_disable();
1811 } else {
1812 apic_phys = mp_lapic_addr;
1813
1814 /*
1815 * acpi lapic path already maps that address in
1816 * acpi_register_lapic_address()
1817 */
1818 if (!acpi_lapic && !smp_found_config)
1819 register_lapic_address(apic_phys);
1820 }
1821
1822 /*
1823 * Fetch the APIC ID of the BSP in case we have a
1824 * default configuration (or the MP table is broken).
1825 */
1826 new_apicid = read_apic_id();
1827 if (boot_cpu_physical_apicid != new_apicid) {
1828 boot_cpu_physical_apicid = new_apicid;
1829 /*
1830 * yeah -- we lie about apic_version
1831 * in case if apic was disabled via boot option
1832 * but it's not a problem for SMP compiled kernel
1833 * since smp_sanity_check is prepared for such a case
1834 * and disable smp mode
1835 */
1836 apic_version[new_apicid] =
1837 GET_APIC_VERSION(apic_read(APIC_LVR));
1838 }
1839 }
1840
register_lapic_address(unsigned long address)1841 void __init register_lapic_address(unsigned long address)
1842 {
1843 mp_lapic_addr = address;
1844
1845 if (!x2apic_mode) {
1846 set_fixmap_nocache(FIX_APIC_BASE, address);
1847 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1848 APIC_BASE, mp_lapic_addr);
1849 }
1850 if (boot_cpu_physical_apicid == -1U) {
1851 boot_cpu_physical_apicid = read_apic_id();
1852 apic_version[boot_cpu_physical_apicid] =
1853 GET_APIC_VERSION(apic_read(APIC_LVR));
1854 }
1855 }
1856
1857 /*
1858 * This initializes the IO-APIC and APIC hardware if this is
1859 * a UP kernel.
1860 */
1861 int apic_version[MAX_LOCAL_APIC];
1862
APIC_init_uniprocessor(void)1863 int __init APIC_init_uniprocessor(void)
1864 {
1865 if (disable_apic) {
1866 pr_info("Apic disabled\n");
1867 return -1;
1868 }
1869 #ifdef CONFIG_X86_64
1870 if (!cpu_has_apic) {
1871 disable_apic = 1;
1872 pr_info("Apic disabled by BIOS\n");
1873 return -1;
1874 }
1875 #else
1876 if (!smp_found_config && !cpu_has_apic)
1877 return -1;
1878
1879 /*
1880 * Complain if the BIOS pretends there is one.
1881 */
1882 if (!cpu_has_apic &&
1883 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1884 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1885 boot_cpu_physical_apicid);
1886 return -1;
1887 }
1888 #endif
1889
1890 default_setup_apic_routing();
1891
1892 verify_local_APIC();
1893 connect_bsp_APIC();
1894
1895 #ifdef CONFIG_X86_64
1896 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1897 #else
1898 /*
1899 * Hack: In case of kdump, after a crash, kernel might be booting
1900 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1901 * might be zero if read from MP tables. Get it from LAPIC.
1902 */
1903 # ifdef CONFIG_CRASH_DUMP
1904 boot_cpu_physical_apicid = read_apic_id();
1905 # endif
1906 #endif
1907 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1908 setup_local_APIC();
1909
1910 #ifdef CONFIG_X86_IO_APIC
1911 /*
1912 * Now enable IO-APICs, actually call clear_IO_APIC
1913 * We need clear_IO_APIC before enabling error vector
1914 */
1915 if (!skip_ioapic_setup && nr_ioapics)
1916 enable_IO_APIC();
1917 #endif
1918
1919 bsp_end_local_APIC_setup();
1920
1921 #ifdef CONFIG_X86_IO_APIC
1922 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1923 setup_IO_APIC();
1924 else {
1925 nr_ioapics = 0;
1926 }
1927 #endif
1928
1929 x86_init.timers.setup_percpu_clockev();
1930 return 0;
1931 }
1932
1933 /*
1934 * Local APIC interrupts
1935 */
1936
1937 /*
1938 * This interrupt should _never_ happen with our APIC/SMP architecture
1939 */
__smp_spurious_interrupt(void)1940 static inline void __smp_spurious_interrupt(void)
1941 {
1942 u32 v;
1943
1944 /*
1945 * Check if this really is a spurious interrupt and ACK it
1946 * if it is a vectored one. Just in case...
1947 * Spurious interrupts should not be ACKed.
1948 */
1949 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1950 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1951 ack_APIC_irq();
1952
1953 inc_irq_stat(irq_spurious_count);
1954
1955 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1956 pr_info("spurious APIC interrupt on CPU#%d, "
1957 "should never happen.\n", smp_processor_id());
1958 }
1959
smp_spurious_interrupt(struct pt_regs * regs)1960 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1961 {
1962 entering_irq();
1963 __smp_spurious_interrupt();
1964 exiting_irq();
1965 }
1966
smp_trace_spurious_interrupt(struct pt_regs * regs)1967 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1968 {
1969 entering_irq();
1970 trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR);
1971 __smp_spurious_interrupt();
1972 trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR);
1973 exiting_irq();
1974 }
1975
1976 /*
1977 * This interrupt should never happen with our APIC/SMP architecture
1978 */
__smp_error_interrupt(struct pt_regs * regs)1979 static inline void __smp_error_interrupt(struct pt_regs *regs)
1980 {
1981 u32 v;
1982 u32 i = 0;
1983 static const char * const error_interrupt_reason[] = {
1984 "Send CS error", /* APIC Error Bit 0 */
1985 "Receive CS error", /* APIC Error Bit 1 */
1986 "Send accept error", /* APIC Error Bit 2 */
1987 "Receive accept error", /* APIC Error Bit 3 */
1988 "Redirectable IPI", /* APIC Error Bit 4 */
1989 "Send illegal vector", /* APIC Error Bit 5 */
1990 "Received illegal vector", /* APIC Error Bit 6 */
1991 "Illegal register address", /* APIC Error Bit 7 */
1992 };
1993
1994 /* First tickle the hardware, only then report what went on. -- REW */
1995 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1996 apic_write(APIC_ESR, 0);
1997 v = apic_read(APIC_ESR);
1998 ack_APIC_irq();
1999 atomic_inc(&irq_err_count);
2000
2001 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2002 smp_processor_id(), v);
2003
2004 v &= 0xff;
2005 while (v) {
2006 if (v & 0x1)
2007 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2008 i++;
2009 v >>= 1;
2010 }
2011
2012 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2013
2014 }
2015
smp_error_interrupt(struct pt_regs * regs)2016 __visible void smp_error_interrupt(struct pt_regs *regs)
2017 {
2018 entering_irq();
2019 __smp_error_interrupt(regs);
2020 exiting_irq();
2021 }
2022
smp_trace_error_interrupt(struct pt_regs * regs)2023 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
2024 {
2025 entering_irq();
2026 trace_error_apic_entry(ERROR_APIC_VECTOR);
2027 __smp_error_interrupt(regs);
2028 trace_error_apic_exit(ERROR_APIC_VECTOR);
2029 exiting_irq();
2030 }
2031
2032 /**
2033 * connect_bsp_APIC - attach the APIC to the interrupt system
2034 */
connect_bsp_APIC(void)2035 void __init connect_bsp_APIC(void)
2036 {
2037 #ifdef CONFIG_X86_32
2038 if (pic_mode) {
2039 /*
2040 * Do not trust the local APIC being empty at bootup.
2041 */
2042 clear_local_APIC();
2043 /*
2044 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2045 * local APIC to INT and NMI lines.
2046 */
2047 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2048 "enabling APIC mode.\n");
2049 imcr_pic_to_apic();
2050 }
2051 #endif
2052 }
2053
2054 /**
2055 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2056 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2057 *
2058 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2059 * APIC is disabled.
2060 */
disconnect_bsp_APIC(int virt_wire_setup)2061 void disconnect_bsp_APIC(int virt_wire_setup)
2062 {
2063 unsigned int value;
2064
2065 #ifdef CONFIG_X86_32
2066 if (pic_mode) {
2067 /*
2068 * Put the board back into PIC mode (has an effect only on
2069 * certain older boards). Note that APIC interrupts, including
2070 * IPIs, won't work beyond this point! The only exception are
2071 * INIT IPIs.
2072 */
2073 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2074 "entering PIC mode.\n");
2075 imcr_apic_to_pic();
2076 return;
2077 }
2078 #endif
2079
2080 /* Go back to Virtual Wire compatibility mode */
2081
2082 /* For the spurious interrupt use vector F, and enable it */
2083 value = apic_read(APIC_SPIV);
2084 value &= ~APIC_VECTOR_MASK;
2085 value |= APIC_SPIV_APIC_ENABLED;
2086 value |= 0xf;
2087 apic_write(APIC_SPIV, value);
2088
2089 if (!virt_wire_setup) {
2090 /*
2091 * For LVT0 make it edge triggered, active high,
2092 * external and enabled
2093 */
2094 value = apic_read(APIC_LVT0);
2095 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2096 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2097 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2098 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2099 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2100 apic_write(APIC_LVT0, value);
2101 } else {
2102 /* Disable LVT0 */
2103 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2104 }
2105
2106 /*
2107 * For LVT1 make it edge triggered, active high,
2108 * nmi and enabled
2109 */
2110 value = apic_read(APIC_LVT1);
2111 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2112 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2113 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2114 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2115 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2116 apic_write(APIC_LVT1, value);
2117 }
2118
generic_processor_info(int apicid,int version)2119 int generic_processor_info(int apicid, int version)
2120 {
2121 int cpu, max = nr_cpu_ids;
2122 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2123 phys_cpu_present_map);
2124
2125 /*
2126 * boot_cpu_physical_apicid is designed to have the apicid
2127 * returned by read_apic_id(), i.e, the apicid of the
2128 * currently booting-up processor. However, on some platforms,
2129 * it is temporarily modified by the apicid reported as BSP
2130 * through MP table. Concretely:
2131 *
2132 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2133 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2134 *
2135 * This function is executed with the modified
2136 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2137 * parameter doesn't work to disable APs on kdump 2nd kernel.
2138 *
2139 * Since fixing handling of boot_cpu_physical_apicid requires
2140 * another discussion and tests on each platform, we leave it
2141 * for now and here we use read_apic_id() directly in this
2142 * function, generic_processor_info().
2143 */
2144 if (disabled_cpu_apicid != BAD_APICID &&
2145 disabled_cpu_apicid != read_apic_id() &&
2146 disabled_cpu_apicid == apicid) {
2147 int thiscpu = num_processors + disabled_cpus;
2148
2149 pr_warning("APIC: Disabling requested cpu."
2150 " Processor %d/0x%x ignored.\n",
2151 thiscpu, apicid);
2152
2153 disabled_cpus++;
2154 return -ENODEV;
2155 }
2156
2157 /*
2158 * If boot cpu has not been detected yet, then only allow upto
2159 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2160 */
2161 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2162 apicid != boot_cpu_physical_apicid) {
2163 int thiscpu = max + disabled_cpus - 1;
2164
2165 pr_warning(
2166 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2167 " reached. Keeping one slot for boot cpu."
2168 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2169
2170 disabled_cpus++;
2171 return -ENODEV;
2172 }
2173
2174 if (num_processors >= nr_cpu_ids) {
2175 int thiscpu = max + disabled_cpus;
2176
2177 pr_warning(
2178 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2179 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2180
2181 disabled_cpus++;
2182 return -EINVAL;
2183 }
2184
2185 num_processors++;
2186 if (apicid == boot_cpu_physical_apicid) {
2187 /*
2188 * x86_bios_cpu_apicid is required to have processors listed
2189 * in same order as logical cpu numbers. Hence the first
2190 * entry is BSP, and so on.
2191 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2192 * for BSP.
2193 */
2194 cpu = 0;
2195 } else
2196 cpu = cpumask_next_zero(-1, cpu_present_mask);
2197
2198 /*
2199 * Validate version
2200 */
2201 if (version == 0x0) {
2202 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2203 cpu, apicid);
2204 version = 0x10;
2205 }
2206 apic_version[apicid] = version;
2207
2208 if (version != apic_version[boot_cpu_physical_apicid]) {
2209 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2210 apic_version[boot_cpu_physical_apicid], cpu, version);
2211 }
2212
2213 physid_set(apicid, phys_cpu_present_map);
2214 if (apicid > max_physical_apicid)
2215 max_physical_apicid = apicid;
2216
2217 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2218 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2219 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2220 #endif
2221 #ifdef CONFIG_X86_32
2222 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2223 apic->x86_32_early_logical_apicid(cpu);
2224 #endif
2225 set_cpu_possible(cpu, true);
2226 set_cpu_present(cpu, true);
2227
2228 return cpu;
2229 }
2230
hard_smp_processor_id(void)2231 int hard_smp_processor_id(void)
2232 {
2233 return read_apic_id();
2234 }
2235
default_init_apic_ldr(void)2236 void default_init_apic_ldr(void)
2237 {
2238 unsigned long val;
2239
2240 apic_write(APIC_DFR, APIC_DFR_VALUE);
2241 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2242 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2243 apic_write(APIC_LDR, val);
2244 }
2245
default_cpu_mask_to_apicid_and(const struct cpumask * cpumask,const struct cpumask * andmask,unsigned int * apicid)2246 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2247 const struct cpumask *andmask,
2248 unsigned int *apicid)
2249 {
2250 unsigned int cpu;
2251
2252 for_each_cpu_and(cpu, cpumask, andmask) {
2253 if (cpumask_test_cpu(cpu, cpu_online_mask))
2254 break;
2255 }
2256
2257 if (likely(cpu < nr_cpu_ids)) {
2258 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2259 return 0;
2260 }
2261
2262 return -EINVAL;
2263 }
2264
2265 /*
2266 * Override the generic EOI implementation with an optimized version.
2267 * Only called during early boot when only one CPU is active and with
2268 * interrupts disabled, so we know this does not race with actual APIC driver
2269 * use.
2270 */
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))2271 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2272 {
2273 struct apic **drv;
2274
2275 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2276 /* Should happen once for each apic */
2277 WARN_ON((*drv)->eoi_write == eoi_write);
2278 (*drv)->eoi_write = eoi_write;
2279 }
2280 }
2281
2282 /*
2283 * Power management
2284 */
2285 #ifdef CONFIG_PM
2286
2287 static struct {
2288 /*
2289 * 'active' is true if the local APIC was enabled by us and
2290 * not the BIOS; this signifies that we are also responsible
2291 * for disabling it before entering apm/acpi suspend
2292 */
2293 int active;
2294 /* r/w apic fields */
2295 unsigned int apic_id;
2296 unsigned int apic_taskpri;
2297 unsigned int apic_ldr;
2298 unsigned int apic_dfr;
2299 unsigned int apic_spiv;
2300 unsigned int apic_lvtt;
2301 unsigned int apic_lvtpc;
2302 unsigned int apic_lvt0;
2303 unsigned int apic_lvt1;
2304 unsigned int apic_lvterr;
2305 unsigned int apic_tmict;
2306 unsigned int apic_tdcr;
2307 unsigned int apic_thmr;
2308 } apic_pm_state;
2309
lapic_suspend(void)2310 static int lapic_suspend(void)
2311 {
2312 unsigned long flags;
2313 int maxlvt;
2314
2315 if (!apic_pm_state.active)
2316 return 0;
2317
2318 maxlvt = lapic_get_maxlvt();
2319
2320 apic_pm_state.apic_id = apic_read(APIC_ID);
2321 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2322 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2323 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2324 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2325 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2326 if (maxlvt >= 4)
2327 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2328 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2329 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2330 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2331 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2332 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2333 #ifdef CONFIG_X86_THERMAL_VECTOR
2334 if (maxlvt >= 5)
2335 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2336 #endif
2337
2338 local_irq_save(flags);
2339 disable_local_APIC();
2340
2341 irq_remapping_disable();
2342
2343 local_irq_restore(flags);
2344 return 0;
2345 }
2346
lapic_resume(void)2347 static void lapic_resume(void)
2348 {
2349 unsigned int l, h;
2350 unsigned long flags;
2351 int maxlvt;
2352
2353 if (!apic_pm_state.active)
2354 return;
2355
2356 local_irq_save(flags);
2357
2358 /*
2359 * IO-APIC and PIC have their own resume routines.
2360 * We just mask them here to make sure the interrupt
2361 * subsystem is completely quiet while we enable x2apic
2362 * and interrupt-remapping.
2363 */
2364 mask_ioapic_entries();
2365 legacy_pic->mask_all();
2366
2367 if (x2apic_mode)
2368 enable_x2apic();
2369 else {
2370 /*
2371 * Make sure the APICBASE points to the right address
2372 *
2373 * FIXME! This will be wrong if we ever support suspend on
2374 * SMP! We'll need to do this as part of the CPU restore!
2375 */
2376 if (boot_cpu_data.x86 >= 6) {
2377 rdmsr(MSR_IA32_APICBASE, l, h);
2378 l &= ~MSR_IA32_APICBASE_BASE;
2379 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2380 wrmsr(MSR_IA32_APICBASE, l, h);
2381 }
2382 }
2383
2384 maxlvt = lapic_get_maxlvt();
2385 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2386 apic_write(APIC_ID, apic_pm_state.apic_id);
2387 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2388 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2389 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2390 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2391 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2392 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2393 #if defined(CONFIG_X86_MCE_INTEL)
2394 if (maxlvt >= 5)
2395 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2396 #endif
2397 if (maxlvt >= 4)
2398 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2399 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2400 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2401 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2402 apic_write(APIC_ESR, 0);
2403 apic_read(APIC_ESR);
2404 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2405 apic_write(APIC_ESR, 0);
2406 apic_read(APIC_ESR);
2407
2408 irq_remapping_reenable(x2apic_mode);
2409
2410 local_irq_restore(flags);
2411 }
2412
2413 /*
2414 * This device has no shutdown method - fully functioning local APICs
2415 * are needed on every CPU up until machine_halt/restart/poweroff.
2416 */
2417
2418 static struct syscore_ops lapic_syscore_ops = {
2419 .resume = lapic_resume,
2420 .suspend = lapic_suspend,
2421 };
2422
apic_pm_activate(void)2423 static void apic_pm_activate(void)
2424 {
2425 apic_pm_state.active = 1;
2426 }
2427
init_lapic_sysfs(void)2428 static int __init init_lapic_sysfs(void)
2429 {
2430 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2431 if (cpu_has_apic)
2432 register_syscore_ops(&lapic_syscore_ops);
2433
2434 return 0;
2435 }
2436
2437 /* local apic needs to resume before other devices access its registers. */
2438 core_initcall(init_lapic_sysfs);
2439
2440 #else /* CONFIG_PM */
2441
apic_pm_activate(void)2442 static void apic_pm_activate(void) { }
2443
2444 #endif /* CONFIG_PM */
2445
2446 #ifdef CONFIG_X86_64
2447
2448 static int multi_checked;
2449 static int multi;
2450
set_multi(const struct dmi_system_id * d)2451 static int set_multi(const struct dmi_system_id *d)
2452 {
2453 if (multi)
2454 return 0;
2455 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2456 multi = 1;
2457 return 0;
2458 }
2459
2460 static const struct dmi_system_id multi_dmi_table[] = {
2461 {
2462 .callback = set_multi,
2463 .ident = "IBM System Summit2",
2464 .matches = {
2465 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2466 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2467 },
2468 },
2469 {}
2470 };
2471
dmi_check_multi(void)2472 static void dmi_check_multi(void)
2473 {
2474 if (multi_checked)
2475 return;
2476
2477 dmi_check_system(multi_dmi_table);
2478 multi_checked = 1;
2479 }
2480
2481 /*
2482 * apic_is_clustered_box() -- Check if we can expect good TSC
2483 *
2484 * Thus far, the major user of this is IBM's Summit2 series:
2485 * Clustered boxes may have unsynced TSC problems if they are
2486 * multi-chassis.
2487 * Use DMI to check them
2488 */
apic_is_clustered_box(void)2489 int apic_is_clustered_box(void)
2490 {
2491 dmi_check_multi();
2492 return multi;
2493 }
2494 #endif
2495
2496 /*
2497 * APIC command line parameters
2498 */
setup_disableapic(char * arg)2499 static int __init setup_disableapic(char *arg)
2500 {
2501 disable_apic = 1;
2502 setup_clear_cpu_cap(X86_FEATURE_APIC);
2503 return 0;
2504 }
2505 early_param("disableapic", setup_disableapic);
2506
2507 /* same as disableapic, for compatibility */
setup_nolapic(char * arg)2508 static int __init setup_nolapic(char *arg)
2509 {
2510 return setup_disableapic(arg);
2511 }
2512 early_param("nolapic", setup_nolapic);
2513
parse_lapic_timer_c2_ok(char * arg)2514 static int __init parse_lapic_timer_c2_ok(char *arg)
2515 {
2516 local_apic_timer_c2_ok = 1;
2517 return 0;
2518 }
2519 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2520
parse_disable_apic_timer(char * arg)2521 static int __init parse_disable_apic_timer(char *arg)
2522 {
2523 disable_apic_timer = 1;
2524 return 0;
2525 }
2526 early_param("noapictimer", parse_disable_apic_timer);
2527
parse_nolapic_timer(char * arg)2528 static int __init parse_nolapic_timer(char *arg)
2529 {
2530 disable_apic_timer = 1;
2531 return 0;
2532 }
2533 early_param("nolapic_timer", parse_nolapic_timer);
2534
apic_set_verbosity(char * arg)2535 static int __init apic_set_verbosity(char *arg)
2536 {
2537 if (!arg) {
2538 #ifdef CONFIG_X86_64
2539 skip_ioapic_setup = 0;
2540 return 0;
2541 #endif
2542 return -EINVAL;
2543 }
2544
2545 if (strcmp("debug", arg) == 0)
2546 apic_verbosity = APIC_DEBUG;
2547 else if (strcmp("verbose", arg) == 0)
2548 apic_verbosity = APIC_VERBOSE;
2549 else {
2550 pr_warning("APIC Verbosity level %s not recognised"
2551 " use apic=verbose or apic=debug\n", arg);
2552 return -EINVAL;
2553 }
2554
2555 return 0;
2556 }
2557 early_param("apic", apic_set_verbosity);
2558
lapic_insert_resource(void)2559 static int __init lapic_insert_resource(void)
2560 {
2561 if (!apic_phys)
2562 return -1;
2563
2564 /* Put local APIC into the resource map. */
2565 lapic_resource.start = apic_phys;
2566 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2567 insert_resource(&iomem_resource, &lapic_resource);
2568
2569 return 0;
2570 }
2571
2572 /*
2573 * need call insert after e820_reserve_resources()
2574 * that is using request_resource
2575 */
2576 late_initcall(lapic_insert_resource);
2577
apic_set_disabled_cpu_apicid(char * arg)2578 static int __init apic_set_disabled_cpu_apicid(char *arg)
2579 {
2580 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2581 return -EINVAL;
2582
2583 return 0;
2584 }
2585 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2586