1 /*
2 * linux/arch/arm/mach-at91/irq.c
3 *
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/mm.h>
26 #include <linux/bitmap.h>
27 #include <linux/types.h>
28 #include <linux/irq.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/irqdomain.h>
33 #include <linux/err.h>
34 #include <linux/slab.h>
35
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/setup.h>
39
40 #include <asm/exception.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/map.h>
44
45 #include "at91_aic.h"
46
47 void __iomem *at91_aic_base;
48 static struct irq_domain *at91_aic_domain;
49 static struct device_node *at91_aic_np;
50 static unsigned int n_irqs = NR_AIC_IRQS;
51
52 #ifdef CONFIG_PM
53
54 static unsigned long *wakeups;
55 static unsigned long *backups;
56
57 #define set_backup(bit) set_bit(bit, backups)
58 #define clear_backup(bit) clear_bit(bit, backups)
59
at91_aic_pm_init(void)60 static int at91_aic_pm_init(void)
61 {
62 backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
63 if (!backups)
64 return -ENOMEM;
65
66 wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
67 if (!wakeups) {
68 kfree(backups);
69 return -ENOMEM;
70 }
71
72 return 0;
73 }
74
at91_aic_set_wake(struct irq_data * d,unsigned value)75 static int at91_aic_set_wake(struct irq_data *d, unsigned value)
76 {
77 if (unlikely(d->hwirq >= n_irqs))
78 return -EINVAL;
79
80 if (value)
81 set_bit(d->hwirq, wakeups);
82 else
83 clear_bit(d->hwirq, wakeups);
84
85 return 0;
86 }
87
at91_irq_suspend(void)88 void at91_irq_suspend(void)
89 {
90 at91_aic_write(AT91_AIC_IDCR, *backups);
91 at91_aic_write(AT91_AIC_IECR, *wakeups);
92 }
93
at91_irq_resume(void)94 void at91_irq_resume(void)
95 {
96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
97 at91_aic_write(AT91_AIC_IECR, *backups);
98 }
99
100 #else
at91_aic_pm_init(void)101 static inline int at91_aic_pm_init(void)
102 {
103 return 0;
104 }
105
106 #define set_backup(bit)
107 #define clear_backup(bit)
108 #define at91_aic_set_wake NULL
109
110 #endif /* CONFIG_PM */
111
112 asmlinkage void __exception_irq_entry
at91_aic_handle_irq(struct pt_regs * regs)113 at91_aic_handle_irq(struct pt_regs *regs)
114 {
115 u32 irqnr;
116 u32 irqstat;
117
118 irqnr = at91_aic_read(AT91_AIC_IVR);
119 irqstat = at91_aic_read(AT91_AIC_ISR);
120
121 /*
122 * ISR value is 0 when there is no current interrupt or when there is
123 * a spurious interrupt
124 */
125 if (!irqstat)
126 at91_aic_write(AT91_AIC_EOICR, 0);
127 else
128 handle_IRQ(irqnr, regs);
129 }
130
at91_aic_mask_irq(struct irq_data * d)131 static void at91_aic_mask_irq(struct irq_data *d)
132 {
133 /* Disable interrupt on AIC */
134 at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
135 /* Update ISR cache */
136 clear_backup(d->hwirq);
137 }
138
at91_aic_unmask_irq(struct irq_data * d)139 static void at91_aic_unmask_irq(struct irq_data *d)
140 {
141 /* Enable interrupt on AIC */
142 at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
143 /* Update ISR cache */
144 set_backup(d->hwirq);
145 }
146
at91_aic_eoi(struct irq_data * d)147 static void at91_aic_eoi(struct irq_data *d)
148 {
149 /*
150 * Mark end-of-interrupt on AIC, the controller doesn't care about
151 * the value written. Moreover it's a write-only register.
152 */
153 at91_aic_write(AT91_AIC_EOICR, 0);
154 }
155
156 static unsigned long *at91_extern_irq;
157
at91_get_extern_irq(void)158 u32 at91_get_extern_irq(void)
159 {
160 if (!at91_extern_irq)
161 return 0;
162 return *at91_extern_irq;
163 }
164
165 #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
166
at91_aic_compute_srctype(struct irq_data * d,unsigned type)167 static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
168 {
169 int srctype;
170
171 switch (type) {
172 case IRQ_TYPE_LEVEL_HIGH:
173 srctype = AT91_AIC_SRCTYPE_HIGH;
174 break;
175 case IRQ_TYPE_EDGE_RISING:
176 srctype = AT91_AIC_SRCTYPE_RISING;
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
180 srctype = AT91_AIC_SRCTYPE_LOW;
181 else
182 srctype = -EINVAL;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
186 srctype = AT91_AIC_SRCTYPE_FALLING;
187 else
188 srctype = -EINVAL;
189 break;
190 default:
191 srctype = -EINVAL;
192 }
193
194 return srctype;
195 }
196
at91_aic_set_type(struct irq_data * d,unsigned type)197 static int at91_aic_set_type(struct irq_data *d, unsigned type)
198 {
199 unsigned int smr;
200 int srctype;
201
202 srctype = at91_aic_compute_srctype(d, type);
203 if (srctype < 0)
204 return srctype;
205
206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
208
209 return 0;
210 }
211
212 static struct irq_chip at91_aic_chip = {
213 .name = "AIC",
214 .irq_mask = at91_aic_mask_irq,
215 .irq_unmask = at91_aic_unmask_irq,
216 .irq_set_type = at91_aic_set_type,
217 .irq_set_wake = at91_aic_set_wake,
218 .irq_eoi = at91_aic_eoi,
219 };
220
at91_aic_hw_init(unsigned int spu_vector)221 static void __init at91_aic_hw_init(unsigned int spu_vector)
222 {
223 int i;
224
225 /*
226 * Perform 8 End Of Interrupt Command to make sure AIC
227 * will not Lock out nIRQ
228 */
229 for (i = 0; i < 8; i++)
230 at91_aic_write(AT91_AIC_EOICR, 0);
231
232 /*
233 * Spurious Interrupt ID in Spurious Vector Register.
234 * When there is no current interrupt, the IRQ Vector Register
235 * reads the value stored in AIC_SPU
236 */
237 at91_aic_write(AT91_AIC_SPU, spu_vector);
238
239 /* No debugging in AIC: Debug (Protect) Control Register */
240 at91_aic_write(AT91_AIC_DCR, 0);
241
242 /* Disable and clear all interrupts initially */
243 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
245 }
246
247 /*
248 * Initialize the AIC interrupt controller.
249 */
at91_aic_init(unsigned int * priority,unsigned int ext_irq_mask)250 void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
251 {
252 unsigned int i;
253 int irq_base;
254
255 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
256 * sizeof(*at91_extern_irq), GFP_KERNEL);
257
258 if (at91_aic_pm_init() || at91_extern_irq == NULL)
259 panic("Unable to allocate bit maps\n");
260
261 *at91_extern_irq = ext_irq_mask;
262
263 at91_aic_base = ioremap(AT91_AIC, 512);
264 if (!at91_aic_base)
265 panic("Unable to ioremap AIC registers\n");
266
267 /* Add irq domain for AIC */
268 irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
269 if (irq_base < 0) {
270 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
271 irq_base = 0;
272 }
273 at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
274 irq_base, 0,
275 &irq_domain_simple_ops, NULL);
276
277 if (!at91_aic_domain)
278 panic("Unable to add AIC irq domain\n");
279
280 irq_set_default_host(at91_aic_domain);
281
282 /*
283 * The IVR is used by macro get_irqnr_and_base to read and verify.
284 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
285 */
286 for (i = 0; i < n_irqs; i++) {
287 /* Put hardware irq number in Source Vector Register: */
288 at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
289 /* Active Low interrupt, with the specified priority */
290 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
291 irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
292 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
293 }
294
295 at91_aic_hw_init(n_irqs);
296 }
297