1 /*
2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * Under GPLv2
6 */
7
8 #define pr_fmt(fmt) "AT91: " fmt
9
10 #include <linux/module.h>
11 #include <linux/io.h>
12 #include <linux/mm.h>
13 #include <linux/pm.h>
14 #include <linux/of_address.h>
15 #include <linux/pinctrl/machine.h>
16 #include <linux/clk/at91_pmc.h>
17
18 #include <asm/system_misc.h>
19 #include <asm/mach/map.h>
20
21 #include <mach/hardware.h>
22 #include <mach/cpu.h>
23 #include <mach/at91_dbgu.h>
24
25 #include "soc.h"
26 #include "generic.h"
27 #include "pm.h"
28
29 struct at91_init_soc __initdata at91_boot_soc;
30
31 struct at91_socinfo at91_soc_initdata;
32 EXPORT_SYMBOL(at91_soc_initdata);
33
at91rm9200_set_type(int type)34 void __init at91rm9200_set_type(int type)
35 {
36 if (type == ARCH_REVISON_9200_PQFP)
37 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
38 else
39 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
40
41 pr_info("filled in soc subtype: %s\n",
42 at91_get_soc_subtype(&at91_soc_initdata));
43 }
44
at91_init_irq_default(void)45 void __init at91_init_irq_default(void)
46 {
47 at91_init_interrupts(at91_boot_soc.default_irq_priority);
48 }
49
at91_init_interrupts(unsigned int * priority)50 void __init at91_init_interrupts(unsigned int *priority)
51 {
52 /* Initialize the AIC interrupt controller */
53 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
55
56 /* Enable GPIO interrupts */
57 at91_gpio_irq_setup();
58 }
59
60 void __iomem *at91_ramc_base[2];
61 EXPORT_SYMBOL_GPL(at91_ramc_base);
62
at91_ioremap_ramc(int id,u32 addr,u32 size)63 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
64 {
65 if (id < 0 || id > 1) {
66 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
67 BUG();
68 }
69 at91_ramc_base[id] = ioremap(addr, size);
70 if (!at91_ramc_base[id])
71 panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
72 }
73
74 static struct map_desc sram_desc[2] __initdata;
75
at91_init_sram(int bank,unsigned long base,unsigned int length)76 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
77 {
78 struct map_desc *desc = &sram_desc[bank];
79
80 desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
81 if (bank > 0)
82 desc->virtual -= sram_desc[bank - 1].length;
83
84 desc->pfn = __phys_to_pfn(base);
85 desc->length = length;
86 desc->type = MT_MEMORY_RWX_NONCACHED;
87
88 pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
89 base, length, desc->virtual);
90
91 iotable_init(desc, 1);
92 }
93
94 static struct map_desc at91_io_desc __initdata __maybe_unused = {
95 .virtual = (unsigned long)AT91_VA_BASE_SYS,
96 .pfn = __phys_to_pfn(AT91_BASE_SYS),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 };
100
101 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
102 .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
103 .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
104 .length = 24 * SZ_1K,
105 .type = MT_DEVICE,
106 };
107
soc_detect(u32 dbgu_base)108 static void __init soc_detect(u32 dbgu_base)
109 {
110 u32 cidr, socid;
111
112 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
113 socid = cidr & ~AT91_CIDR_VERSION;
114
115 switch (socid) {
116 case ARCH_ID_AT91RM9200:
117 at91_soc_initdata.type = AT91_SOC_RM9200;
118 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
119 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
120 at91_boot_soc = at91rm9200_soc;
121 break;
122
123 case ARCH_ID_AT91SAM9260:
124 at91_soc_initdata.type = AT91_SOC_SAM9260;
125 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
126 at91_boot_soc = at91sam9260_soc;
127 break;
128
129 case ARCH_ID_AT91SAM9261:
130 at91_soc_initdata.type = AT91_SOC_SAM9261;
131 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
132 at91_boot_soc = at91sam9261_soc;
133 break;
134
135 case ARCH_ID_AT91SAM9263:
136 at91_soc_initdata.type = AT91_SOC_SAM9263;
137 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
138 at91_boot_soc = at91sam9263_soc;
139 break;
140
141 case ARCH_ID_AT91SAM9G20:
142 at91_soc_initdata.type = AT91_SOC_SAM9G20;
143 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
144 at91_boot_soc = at91sam9260_soc;
145 break;
146
147 case ARCH_ID_AT91SAM9G45:
148 at91_soc_initdata.type = AT91_SOC_SAM9G45;
149 if (cidr == ARCH_ID_AT91SAM9G45ES)
150 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
151 at91_boot_soc = at91sam9g45_soc;
152 break;
153
154 case ARCH_ID_AT91SAM9RL64:
155 at91_soc_initdata.type = AT91_SOC_SAM9RL;
156 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
157 at91_boot_soc = at91sam9rl_soc;
158 break;
159
160 case ARCH_ID_AT91SAM9X5:
161 at91_soc_initdata.type = AT91_SOC_SAM9X5;
162 at91_boot_soc = at91sam9x5_soc;
163 break;
164
165 case ARCH_ID_AT91SAM9N12:
166 at91_soc_initdata.type = AT91_SOC_SAM9N12;
167 at91_boot_soc = at91sam9n12_soc;
168 break;
169
170 case ARCH_ID_SAMA5:
171 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
172 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
173 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
174 at91_boot_soc = sama5d3_soc;
175 }
176 break;
177 }
178
179 /* at91sam9g10 */
180 if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
181 at91_soc_initdata.type = AT91_SOC_SAM9G10;
182 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
183 at91_boot_soc = at91sam9261_soc;
184 }
185 /* at91sam9xe */
186 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
187 at91_soc_initdata.type = AT91_SOC_SAM9260;
188 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
189 at91_boot_soc = at91sam9260_soc;
190 }
191
192 if (!at91_soc_is_detected())
193 return;
194
195 at91_soc_initdata.cidr = cidr;
196
197 /* sub version of soc */
198 if (!at91_soc_initdata.exid)
199 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
200
201 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
202 switch (at91_soc_initdata.exid) {
203 case ARCH_EXID_AT91SAM9M10:
204 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
205 break;
206 case ARCH_EXID_AT91SAM9G46:
207 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
208 break;
209 case ARCH_EXID_AT91SAM9M11:
210 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
211 break;
212 }
213 }
214
215 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
216 switch (at91_soc_initdata.exid) {
217 case ARCH_EXID_AT91SAM9G15:
218 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
219 break;
220 case ARCH_EXID_AT91SAM9G35:
221 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
222 break;
223 case ARCH_EXID_AT91SAM9X35:
224 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
225 break;
226 case ARCH_EXID_AT91SAM9G25:
227 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
228 break;
229 case ARCH_EXID_AT91SAM9X25:
230 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
231 break;
232 }
233 }
234
235 if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
236 switch (at91_soc_initdata.exid) {
237 case ARCH_EXID_SAMA5D31:
238 at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
239 break;
240 case ARCH_EXID_SAMA5D33:
241 at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
242 break;
243 case ARCH_EXID_SAMA5D34:
244 at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
245 break;
246 case ARCH_EXID_SAMA5D35:
247 at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
248 break;
249 case ARCH_EXID_SAMA5D36:
250 at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
251 break;
252 }
253 }
254 }
255
alt_soc_detect(u32 dbgu_base)256 static void __init alt_soc_detect(u32 dbgu_base)
257 {
258 u32 cidr, socid;
259
260 /* SoC ID */
261 cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
262 socid = cidr & ~AT91_CIDR_VERSION;
263
264 switch (socid) {
265 case ARCH_ID_SAMA5:
266 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
267 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
268 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
269 at91_boot_soc = sama5d3_soc;
270 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
271 at91_soc_initdata.type = AT91_SOC_SAMA5D4;
272 at91_boot_soc = sama5d4_soc;
273 }
274 break;
275 }
276
277 if (!at91_soc_is_detected())
278 return;
279
280 at91_soc_initdata.cidr = cidr;
281
282 /* sub version of soc */
283 if (!at91_soc_initdata.exid)
284 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
285
286 if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
287 switch (at91_soc_initdata.exid) {
288 case ARCH_EXID_SAMA5D41:
289 at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
290 break;
291 case ARCH_EXID_SAMA5D42:
292 at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
293 break;
294 case ARCH_EXID_SAMA5D43:
295 at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
296 break;
297 case ARCH_EXID_SAMA5D44:
298 at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
299 break;
300 }
301 }
302 }
303
304 static const char *soc_name[] = {
305 [AT91_SOC_RM9200] = "at91rm9200",
306 [AT91_SOC_SAM9260] = "at91sam9260",
307 [AT91_SOC_SAM9261] = "at91sam9261",
308 [AT91_SOC_SAM9263] = "at91sam9263",
309 [AT91_SOC_SAM9G10] = "at91sam9g10",
310 [AT91_SOC_SAM9G20] = "at91sam9g20",
311 [AT91_SOC_SAM9G45] = "at91sam9g45",
312 [AT91_SOC_SAM9RL] = "at91sam9rl",
313 [AT91_SOC_SAM9X5] = "at91sam9x5",
314 [AT91_SOC_SAM9N12] = "at91sam9n12",
315 [AT91_SOC_SAMA5D3] = "sama5d3",
316 [AT91_SOC_SAMA5D4] = "sama5d4",
317 [AT91_SOC_UNKNOWN] = "Unknown",
318 };
319
at91_get_soc_type(struct at91_socinfo * c)320 const char *at91_get_soc_type(struct at91_socinfo *c)
321 {
322 return soc_name[c->type];
323 }
324 EXPORT_SYMBOL(at91_get_soc_type);
325
326 static const char *soc_subtype_name[] = {
327 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
328 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
329 [AT91_SOC_SAM9XE] = "at91sam9xe",
330 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
331 [AT91_SOC_SAM9M10] = "at91sam9m10",
332 [AT91_SOC_SAM9G46] = "at91sam9g46",
333 [AT91_SOC_SAM9M11] = "at91sam9m11",
334 [AT91_SOC_SAM9G15] = "at91sam9g15",
335 [AT91_SOC_SAM9G35] = "at91sam9g35",
336 [AT91_SOC_SAM9X35] = "at91sam9x35",
337 [AT91_SOC_SAM9G25] = "at91sam9g25",
338 [AT91_SOC_SAM9X25] = "at91sam9x25",
339 [AT91_SOC_SAMA5D31] = "sama5d31",
340 [AT91_SOC_SAMA5D33] = "sama5d33",
341 [AT91_SOC_SAMA5D34] = "sama5d34",
342 [AT91_SOC_SAMA5D35] = "sama5d35",
343 [AT91_SOC_SAMA5D36] = "sama5d36",
344 [AT91_SOC_SAMA5D41] = "sama5d41",
345 [AT91_SOC_SAMA5D42] = "sama5d42",
346 [AT91_SOC_SAMA5D43] = "sama5d43",
347 [AT91_SOC_SAMA5D44] = "sama5d44",
348 [AT91_SOC_SUBTYPE_NONE] = "None",
349 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
350 };
351
at91_get_soc_subtype(struct at91_socinfo * c)352 const char *at91_get_soc_subtype(struct at91_socinfo *c)
353 {
354 return soc_subtype_name[c->subtype];
355 }
356 EXPORT_SYMBOL(at91_get_soc_subtype);
357
at91_map_io(void)358 void __init at91_map_io(void)
359 {
360 /* Map peripherals */
361 iotable_init(&at91_io_desc, 1);
362
363 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
364 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
365
366 soc_detect(AT91_BASE_DBGU0);
367 if (!at91_soc_is_detected())
368 soc_detect(AT91_BASE_DBGU1);
369
370 if (!at91_soc_is_detected())
371 panic(pr_fmt("Impossible to detect the SOC type"));
372
373 pr_info("Detected soc type: %s\n",
374 at91_get_soc_type(&at91_soc_initdata));
375 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
376 pr_info("Detected soc subtype: %s\n",
377 at91_get_soc_subtype(&at91_soc_initdata));
378
379 if (!at91_soc_is_enabled())
380 panic(pr_fmt("Soc not enabled"));
381
382 if (at91_boot_soc.map_io)
383 at91_boot_soc.map_io();
384 }
385
at91_alt_map_io(void)386 void __init at91_alt_map_io(void)
387 {
388 /* Map peripherals */
389 iotable_init(&at91_alt_io_desc, 1);
390
391 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
392 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
393
394 alt_soc_detect(AT91_BASE_DBGU2);
395 if (!at91_soc_is_detected())
396 panic("AT91: Impossible to detect the SOC type");
397
398 pr_info("AT91: Detected soc type: %s\n",
399 at91_get_soc_type(&at91_soc_initdata));
400 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
401 pr_info("AT91: Detected soc subtype: %s\n",
402 at91_get_soc_subtype(&at91_soc_initdata));
403
404 if (!at91_soc_is_enabled())
405 panic("AT91: Soc not enabled");
406
407 if (at91_boot_soc.map_io)
408 at91_boot_soc.map_io();
409 }
410
411 void __iomem *at91_matrix_base;
412 EXPORT_SYMBOL_GPL(at91_matrix_base);
413
at91_ioremap_matrix(u32 base_addr)414 void __init at91_ioremap_matrix(u32 base_addr)
415 {
416 at91_matrix_base = ioremap(base_addr, 512);
417 if (!at91_matrix_base)
418 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
419 }
420
421 #if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
422 static struct of_device_id ramc_ids[] = {
423 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
424 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
425 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
426 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
427 { /*sentinel*/ }
428 };
429
at91_dt_ramc(void)430 static void at91_dt_ramc(void)
431 {
432 struct device_node *np;
433 const struct of_device_id *of_id;
434 int idx = 0;
435 const void *standby = NULL;
436
437 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
438 at91_ramc_base[idx] = of_iomap(np, 0);
439 if (!at91_ramc_base[idx])
440 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
441
442 if (!standby)
443 standby = of_id->data;
444
445 idx++;
446 }
447
448 if (!idx)
449 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
450
451 if (!standby) {
452 pr_warn("ramc no standby function available\n");
453 return;
454 }
455
456 at91_pm_set_standby(standby);
457 }
458
at91rm9200_dt_initialize(void)459 void __init at91rm9200_dt_initialize(void)
460 {
461 at91_dt_ramc();
462
463 /* Init clock subsystem */
464 at91_dt_clock_init();
465
466 /* Register the processor-specific clocks */
467 if (at91_boot_soc.register_clocks)
468 at91_boot_soc.register_clocks();
469
470 at91_boot_soc.init();
471 }
472
at91_dt_initialize(void)473 void __init at91_dt_initialize(void)
474 {
475 at91_dt_ramc();
476
477 /* Init clock subsystem */
478 at91_dt_clock_init();
479
480 /* Register the processor-specific clocks */
481 if (at91_boot_soc.register_clocks)
482 at91_boot_soc.register_clocks();
483
484 if (at91_boot_soc.init)
485 at91_boot_soc.init();
486 }
487 #endif
488
at91_initialize(unsigned long main_clock)489 void __init at91_initialize(unsigned long main_clock)
490 {
491 at91_boot_soc.ioremap_registers();
492
493 /* Init clock subsystem */
494 at91_clock_init(main_clock);
495
496 /* Register the processor-specific clocks */
497 at91_boot_soc.register_clocks();
498
499 at91_boot_soc.init();
500
501 pinctrl_provide_dummies();
502 }
503
at91_register_devices(void)504 void __init at91_register_devices(void)
505 {
506 at91_boot_soc.register_devices();
507 }
508
at91_init_time(void)509 void __init at91_init_time(void)
510 {
511 at91_boot_soc.init_time();
512 }
513