1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
ath9k_parse_mpdudensity(u8 mpdudensity)22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq)57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58 {
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth) {
64 pending = true;
65 goto out;
66 }
67
68 if (txq->mac80211_qnum >= 0) {
69 struct list_head *list;
70
71 list = &sc->cur_chan->acq[txq->mac80211_qnum];
72 if (!list_empty(list))
73 pending = true;
74 }
75 out:
76 spin_unlock_bh(&txq->axq_lock);
77 return pending;
78 }
79
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)80 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
81 {
82 unsigned long flags;
83 bool ret;
84
85 spin_lock_irqsave(&sc->sc_pm_lock, flags);
86 ret = ath9k_hw_setpower(sc->sc_ah, mode);
87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
88
89 return ret;
90 }
91
ath_ps_full_sleep(unsigned long data)92 void ath_ps_full_sleep(unsigned long data)
93 {
94 struct ath_softc *sc = (struct ath_softc *) data;
95 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
96 bool reset;
97
98 spin_lock(&common->cc_lock);
99 ath_hw_cycle_counters_update(common);
100 spin_unlock(&common->cc_lock);
101
102 ath9k_hw_setrxabort(sc->sc_ah, 1);
103 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
104
105 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
106 }
107
ath9k_ps_wakeup(struct ath_softc * sc)108 void ath9k_ps_wakeup(struct ath_softc *sc)
109 {
110 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
111 unsigned long flags;
112 enum ath9k_power_mode power_mode;
113
114 spin_lock_irqsave(&sc->sc_pm_lock, flags);
115 if (++sc->ps_usecount != 1)
116 goto unlock;
117
118 del_timer_sync(&sc->sleep_timer);
119 power_mode = sc->sc_ah->power_mode;
120 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
121
122 /*
123 * While the hardware is asleep, the cycle counters contain no
124 * useful data. Better clear them now so that they don't mess up
125 * survey data results.
126 */
127 if (power_mode != ATH9K_PM_AWAKE) {
128 spin_lock(&common->cc_lock);
129 ath_hw_cycle_counters_update(common);
130 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
131 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
132 spin_unlock(&common->cc_lock);
133 }
134
135 unlock:
136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
137 }
138
ath9k_ps_restore(struct ath_softc * sc)139 void ath9k_ps_restore(struct ath_softc *sc)
140 {
141 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
142 enum ath9k_power_mode mode;
143 unsigned long flags;
144
145 spin_lock_irqsave(&sc->sc_pm_lock, flags);
146 if (--sc->ps_usecount != 0)
147 goto unlock;
148
149 if (sc->ps_idle) {
150 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
151 goto unlock;
152 }
153
154 if (sc->ps_enabled &&
155 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
156 PS_WAIT_FOR_CAB |
157 PS_WAIT_FOR_PSPOLL_DATA |
158 PS_WAIT_FOR_TX_ACK |
159 PS_WAIT_FOR_ANI))) {
160 mode = ATH9K_PM_NETWORK_SLEEP;
161 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
162 ath9k_btcoex_stop_gen_timer(sc);
163 } else {
164 goto unlock;
165 }
166
167 spin_lock(&common->cc_lock);
168 ath_hw_cycle_counters_update(common);
169 spin_unlock(&common->cc_lock);
170
171 ath9k_hw_setpower(sc->sc_ah, mode);
172
173 unlock:
174 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
175 }
176
__ath_cancel_work(struct ath_softc * sc)177 static void __ath_cancel_work(struct ath_softc *sc)
178 {
179 cancel_work_sync(&sc->paprd_work);
180 cancel_delayed_work_sync(&sc->tx_complete_work);
181 cancel_delayed_work_sync(&sc->hw_pll_work);
182
183 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
184 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
185 cancel_work_sync(&sc->mci_work);
186 #endif
187 }
188
ath_cancel_work(struct ath_softc * sc)189 void ath_cancel_work(struct ath_softc *sc)
190 {
191 __ath_cancel_work(sc);
192 cancel_work_sync(&sc->hw_reset_work);
193 }
194
ath_restart_work(struct ath_softc * sc)195 void ath_restart_work(struct ath_softc *sc)
196 {
197 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
198
199 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
200 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
201 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
202
203 ath_start_ani(sc);
204 }
205
ath_prepare_reset(struct ath_softc * sc)206 static bool ath_prepare_reset(struct ath_softc *sc)
207 {
208 struct ath_hw *ah = sc->sc_ah;
209 bool ret = true;
210
211 ieee80211_stop_queues(sc->hw);
212 ath_stop_ani(sc);
213 ath9k_hw_disable_interrupts(ah);
214
215 if (AR_SREV_9300_20_OR_LATER(ah)) {
216 ret &= ath_stoprecv(sc);
217 ret &= ath_drain_all_txq(sc);
218 } else {
219 ret &= ath_drain_all_txq(sc);
220 ret &= ath_stoprecv(sc);
221 }
222
223 return ret;
224 }
225
ath_complete_reset(struct ath_softc * sc,bool start)226 static bool ath_complete_reset(struct ath_softc *sc, bool start)
227 {
228 struct ath_hw *ah = sc->sc_ah;
229 struct ath_common *common = ath9k_hw_common(ah);
230 unsigned long flags;
231
232 ath9k_calculate_summary_state(sc, sc->cur_chan);
233 ath_startrecv(sc);
234 ath9k_cmn_update_txpow(ah, sc->curtxpow,
235 sc->cur_chan->txpower, &sc->curtxpow);
236 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
237
238 if (!sc->cur_chan->offchannel && start) {
239 /* restore per chanctx TSF timer */
240 if (sc->cur_chan->tsf_val) {
241 u32 offset;
242
243 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
244 NULL);
245 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
246 }
247
248
249 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
250 goto work;
251
252 if (ah->opmode == NL80211_IFTYPE_STATION &&
253 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
254 spin_lock_irqsave(&sc->sc_pm_lock, flags);
255 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
256 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
257 } else {
258 ath9k_set_beacon(sc);
259 }
260 work:
261 ath_restart_work(sc);
262 ath_txq_schedule_all(sc);
263 }
264
265 sc->gtt_cnt = 0;
266
267 ath9k_hw_set_interrupts(ah);
268 ath9k_hw_enable_interrupts(ah);
269 ieee80211_wake_queues(sc->hw);
270 ath9k_p2p_ps_timer(sc);
271
272 return true;
273 }
274
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)275 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
276 {
277 struct ath_hw *ah = sc->sc_ah;
278 struct ath_common *common = ath9k_hw_common(ah);
279 struct ath9k_hw_cal_data *caldata = NULL;
280 bool fastcc = true;
281 int r;
282
283 __ath_cancel_work(sc);
284
285 tasklet_disable(&sc->intr_tq);
286 spin_lock_bh(&sc->sc_pcu_lock);
287
288 if (!sc->cur_chan->offchannel) {
289 fastcc = false;
290 caldata = &sc->cur_chan->caldata;
291 }
292
293 if (!hchan) {
294 fastcc = false;
295 hchan = ah->curchan;
296 }
297
298 if (!ath_prepare_reset(sc))
299 fastcc = false;
300
301 if (ath9k_is_chanctx_enabled())
302 fastcc = false;
303
304 spin_lock_bh(&sc->chan_lock);
305 sc->cur_chandef = sc->cur_chan->chandef;
306 spin_unlock_bh(&sc->chan_lock);
307
308 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
309 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
310
311 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
312 if (r) {
313 ath_err(common,
314 "Unable to reset channel, reset status %d\n", r);
315
316 ath9k_hw_enable_interrupts(ah);
317 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
318
319 goto out;
320 }
321
322 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
323 sc->cur_chan->offchannel)
324 ath9k_mci_set_txpower(sc, true, false);
325
326 if (!ath_complete_reset(sc, true))
327 r = -EIO;
328
329 out:
330 spin_unlock_bh(&sc->sc_pcu_lock);
331 tasklet_enable(&sc->intr_tq);
332
333 return r;
334 }
335
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)336 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
337 struct ieee80211_vif *vif)
338 {
339 struct ath_node *an;
340 an = (struct ath_node *)sta->drv_priv;
341
342 an->sc = sc;
343 an->sta = sta;
344 an->vif = vif;
345 memset(&an->key_idx, 0, sizeof(an->key_idx));
346
347 ath_tx_node_init(sc, an);
348
349 ath_dynack_node_init(sc->sc_ah, an);
350 }
351
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)352 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
353 {
354 struct ath_node *an = (struct ath_node *)sta->drv_priv;
355 ath_tx_node_cleanup(sc, an);
356
357 ath_dynack_node_deinit(sc->sc_ah, an);
358 }
359
ath9k_tasklet(unsigned long data)360 void ath9k_tasklet(unsigned long data)
361 {
362 struct ath_softc *sc = (struct ath_softc *)data;
363 struct ath_hw *ah = sc->sc_ah;
364 struct ath_common *common = ath9k_hw_common(ah);
365 enum ath_reset_type type;
366 unsigned long flags;
367 u32 status = sc->intrstatus;
368 u32 rxmask;
369
370 ath9k_ps_wakeup(sc);
371 spin_lock(&sc->sc_pcu_lock);
372
373 if (status & ATH9K_INT_FATAL) {
374 type = RESET_TYPE_FATAL_INT;
375 ath9k_queue_reset(sc, type);
376
377 /*
378 * Increment the ref. counter here so that
379 * interrupts are enabled in the reset routine.
380 */
381 atomic_inc(&ah->intr_ref_cnt);
382 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
383 goto out;
384 }
385
386 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
387 (status & ATH9K_INT_BB_WATCHDOG)) {
388 spin_lock(&common->cc_lock);
389 ath_hw_cycle_counters_update(common);
390 ar9003_hw_bb_watchdog_dbg_info(ah);
391 spin_unlock(&common->cc_lock);
392
393 if (ar9003_hw_bb_watchdog_check(ah)) {
394 type = RESET_TYPE_BB_WATCHDOG;
395 ath9k_queue_reset(sc, type);
396
397 /*
398 * Increment the ref. counter here so that
399 * interrupts are enabled in the reset routine.
400 */
401 atomic_inc(&ah->intr_ref_cnt);
402 ath_dbg(common, RESET,
403 "BB_WATCHDOG: Skipping interrupts\n");
404 goto out;
405 }
406 }
407
408 if (status & ATH9K_INT_GTT) {
409 sc->gtt_cnt++;
410
411 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
412 type = RESET_TYPE_TX_GTT;
413 ath9k_queue_reset(sc, type);
414 atomic_inc(&ah->intr_ref_cnt);
415 ath_dbg(common, RESET,
416 "GTT: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 spin_lock_irqsave(&sc->sc_pm_lock, flags);
422 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
423 /*
424 * TSF sync does not look correct; remain awake to sync with
425 * the next Beacon.
426 */
427 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
428 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
429 }
430 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
431
432 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
433 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
434 ATH9K_INT_RXORN);
435 else
436 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
437
438 if (status & rxmask) {
439 /* Check for high priority Rx first */
440 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
441 (status & ATH9K_INT_RXHP))
442 ath_rx_tasklet(sc, 0, true);
443
444 ath_rx_tasklet(sc, 0, false);
445 }
446
447 if (status & ATH9K_INT_TX) {
448 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
449 /*
450 * For EDMA chips, TX completion is enabled for the
451 * beacon queue, so if a beacon has been transmitted
452 * successfully after a GTT interrupt, the GTT counter
453 * gets reset to zero here.
454 */
455 sc->gtt_cnt = 0;
456
457 ath_tx_edma_tasklet(sc);
458 } else {
459 ath_tx_tasklet(sc);
460 }
461
462 wake_up(&sc->tx_wait);
463 }
464
465 if (status & ATH9K_INT_GENTIMER)
466 ath_gen_timer_isr(sc->sc_ah);
467
468 ath9k_btcoex_handle_interrupt(sc, status);
469
470 /* re-enable hardware interrupt */
471 ath9k_hw_enable_interrupts(ah);
472 out:
473 spin_unlock(&sc->sc_pcu_lock);
474 ath9k_ps_restore(sc);
475 }
476
ath_isr(int irq,void * dev)477 irqreturn_t ath_isr(int irq, void *dev)
478 {
479 #define SCHED_INTR ( \
480 ATH9K_INT_FATAL | \
481 ATH9K_INT_BB_WATCHDOG | \
482 ATH9K_INT_RXORN | \
483 ATH9K_INT_RXEOL | \
484 ATH9K_INT_RX | \
485 ATH9K_INT_RXLP | \
486 ATH9K_INT_RXHP | \
487 ATH9K_INT_TX | \
488 ATH9K_INT_BMISS | \
489 ATH9K_INT_CST | \
490 ATH9K_INT_GTT | \
491 ATH9K_INT_TSFOOR | \
492 ATH9K_INT_GENTIMER | \
493 ATH9K_INT_MCI)
494
495 struct ath_softc *sc = dev;
496 struct ath_hw *ah = sc->sc_ah;
497 struct ath_common *common = ath9k_hw_common(ah);
498 enum ath9k_int status;
499 u32 sync_cause = 0;
500 bool sched = false;
501
502 /*
503 * The hardware is not ready/present, don't
504 * touch anything. Note this can happen early
505 * on if the IRQ is shared.
506 */
507 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
508 return IRQ_NONE;
509
510 /* shared irq, not for us */
511
512 if (!ath9k_hw_intrpend(ah))
513 return IRQ_NONE;
514
515 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
516 ath9k_hw_kill_interrupts(ah);
517 return IRQ_HANDLED;
518 }
519
520 /*
521 * Figure out the reason(s) for the interrupt. Note
522 * that the hal returns a pseudo-ISR that may include
523 * bits we haven't explicitly enabled so we mask the
524 * value to insure we only process bits we requested.
525 */
526 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
527 ath9k_debug_sync_cause(sc, sync_cause);
528 status &= ah->imask; /* discard unasked-for bits */
529
530 /*
531 * If there are no status bits set, then this interrupt was not
532 * for me (should have been caught above).
533 */
534 if (!status)
535 return IRQ_NONE;
536
537 /* Cache the status */
538 sc->intrstatus = status;
539
540 if (status & SCHED_INTR)
541 sched = true;
542
543 /*
544 * If a FATAL or RXORN interrupt is received, we have to reset the
545 * chip immediately.
546 */
547 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
548 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
549 goto chip_reset;
550
551 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
552 (status & ATH9K_INT_BB_WATCHDOG))
553 goto chip_reset;
554
555 #ifdef CONFIG_ATH9K_WOW
556 if (status & ATH9K_INT_BMISS) {
557 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
558 atomic_inc(&sc->wow_got_bmiss_intr);
559 atomic_dec(&sc->wow_sleep_proc_intr);
560 }
561 }
562 #endif
563
564 if (status & ATH9K_INT_SWBA)
565 tasklet_schedule(&sc->bcon_tasklet);
566
567 if (status & ATH9K_INT_TXURN)
568 ath9k_hw_updatetxtriglevel(ah, true);
569
570 if (status & ATH9K_INT_RXEOL) {
571 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
572 ath9k_hw_set_interrupts(ah);
573 }
574
575 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
576 if (status & ATH9K_INT_TIM_TIMER) {
577 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
578 goto chip_reset;
579 /* Clear RxAbort bit so that we can
580 * receive frames */
581 ath9k_setpower(sc, ATH9K_PM_AWAKE);
582 spin_lock(&sc->sc_pm_lock);
583 ath9k_hw_setrxabort(sc->sc_ah, 0);
584 sc->ps_flags |= PS_WAIT_FOR_BEACON;
585 spin_unlock(&sc->sc_pm_lock);
586 }
587
588 chip_reset:
589
590 ath_debug_stat_interrupt(sc, status);
591
592 if (sched) {
593 /* turn off every interrupt */
594 ath9k_hw_disable_interrupts(ah);
595 tasklet_schedule(&sc->intr_tq);
596 }
597
598 return IRQ_HANDLED;
599
600 #undef SCHED_INTR
601 }
602
ath_reset(struct ath_softc * sc)603 int ath_reset(struct ath_softc *sc)
604 {
605 int r;
606
607 ath9k_ps_wakeup(sc);
608 r = ath_reset_internal(sc, NULL);
609 ath9k_ps_restore(sc);
610
611 return r;
612 }
613
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)614 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
615 {
616 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
617 #ifdef CONFIG_ATH9K_DEBUGFS
618 RESET_STAT_INC(sc, type);
619 #endif
620 set_bit(ATH_OP_HW_RESET, &common->op_flags);
621 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
622 }
623
ath_reset_work(struct work_struct * work)624 void ath_reset_work(struct work_struct *work)
625 {
626 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
627
628 ath_reset(sc);
629 }
630
631 /**********************/
632 /* mac80211 callbacks */
633 /**********************/
634
ath9k_start(struct ieee80211_hw * hw)635 static int ath9k_start(struct ieee80211_hw *hw)
636 {
637 struct ath_softc *sc = hw->priv;
638 struct ath_hw *ah = sc->sc_ah;
639 struct ath_common *common = ath9k_hw_common(ah);
640 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
641 struct ath_chanctx *ctx = sc->cur_chan;
642 struct ath9k_channel *init_channel;
643 int r;
644
645 ath_dbg(common, CONFIG,
646 "Starting driver with initial channel: %d MHz\n",
647 curchan->center_freq);
648
649 ath9k_ps_wakeup(sc);
650 mutex_lock(&sc->mutex);
651
652 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
653 sc->cur_chandef = hw->conf.chandef;
654
655 /* Reset SERDES registers */
656 ath9k_hw_configpcipowersave(ah, false);
657
658 /*
659 * The basic interface to setting the hardware in a good
660 * state is ``reset''. On return the hardware is known to
661 * be powered up and with interrupts disabled. This must
662 * be followed by initialization of the appropriate bits
663 * and then setup of the interrupt mask.
664 */
665 spin_lock_bh(&sc->sc_pcu_lock);
666
667 atomic_set(&ah->intr_ref_cnt, -1);
668
669 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
670 if (r) {
671 ath_err(common,
672 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
673 r, curchan->center_freq);
674 ah->reset_power_on = false;
675 }
676
677 /* Setup our intr mask. */
678 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
679 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
680 ATH9K_INT_GLOBAL;
681
682 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
683 ah->imask |= ATH9K_INT_RXHP |
684 ATH9K_INT_RXLP;
685 else
686 ah->imask |= ATH9K_INT_RX;
687
688 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
689 ah->imask |= ATH9K_INT_BB_WATCHDOG;
690
691 /*
692 * Enable GTT interrupts only for AR9003/AR9004 chips
693 * for now.
694 */
695 if (AR_SREV_9300_20_OR_LATER(ah))
696 ah->imask |= ATH9K_INT_GTT;
697
698 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
699 ah->imask |= ATH9K_INT_CST;
700
701 ath_mci_enable(sc);
702
703 clear_bit(ATH_OP_INVALID, &common->op_flags);
704 sc->sc_ah->is_monitoring = false;
705
706 if (!ath_complete_reset(sc, false))
707 ah->reset_power_on = false;
708
709 if (ah->led_pin >= 0) {
710 ath9k_hw_cfg_output(ah, ah->led_pin,
711 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
712 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
713 }
714
715 /*
716 * Reset key cache to sane defaults (all entries cleared) instead of
717 * semi-random values after suspend/resume.
718 */
719 ath9k_cmn_init_crypto(sc->sc_ah);
720
721 ath9k_hw_reset_tsf(ah);
722
723 spin_unlock_bh(&sc->sc_pcu_lock);
724
725 mutex_unlock(&sc->mutex);
726
727 ath9k_ps_restore(sc);
728
729 return 0;
730 }
731
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)732 static void ath9k_tx(struct ieee80211_hw *hw,
733 struct ieee80211_tx_control *control,
734 struct sk_buff *skb)
735 {
736 struct ath_softc *sc = hw->priv;
737 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
738 struct ath_tx_control txctl;
739 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
740 unsigned long flags;
741
742 if (sc->ps_enabled) {
743 /*
744 * mac80211 does not set PM field for normal data frames, so we
745 * need to update that based on the current PS mode.
746 */
747 if (ieee80211_is_data(hdr->frame_control) &&
748 !ieee80211_is_nullfunc(hdr->frame_control) &&
749 !ieee80211_has_pm(hdr->frame_control)) {
750 ath_dbg(common, PS,
751 "Add PM=1 for a TX frame while in PS mode\n");
752 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
753 }
754 }
755
756 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
757 /*
758 * We are using PS-Poll and mac80211 can request TX while in
759 * power save mode. Need to wake up hardware for the TX to be
760 * completed and if needed, also for RX of buffered frames.
761 */
762 ath9k_ps_wakeup(sc);
763 spin_lock_irqsave(&sc->sc_pm_lock, flags);
764 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
765 ath9k_hw_setrxabort(sc->sc_ah, 0);
766 if (ieee80211_is_pspoll(hdr->frame_control)) {
767 ath_dbg(common, PS,
768 "Sending PS-Poll to pick a buffered frame\n");
769 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
770 } else {
771 ath_dbg(common, PS, "Wake up to complete TX\n");
772 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
773 }
774 /*
775 * The actual restore operation will happen only after
776 * the ps_flags bit is cleared. We are just dropping
777 * the ps_usecount here.
778 */
779 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
780 ath9k_ps_restore(sc);
781 }
782
783 /*
784 * Cannot tx while the hardware is in full sleep, it first needs a full
785 * chip reset to recover from that
786 */
787 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
788 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
789 goto exit;
790 }
791
792 memset(&txctl, 0, sizeof(struct ath_tx_control));
793 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
794 txctl.sta = control->sta;
795
796 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
797
798 if (ath_tx_start(hw, skb, &txctl) != 0) {
799 ath_dbg(common, XMIT, "TX failed\n");
800 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
801 goto exit;
802 }
803
804 return;
805 exit:
806 ieee80211_free_txskb(hw, skb);
807 }
808
ath9k_stop(struct ieee80211_hw * hw)809 static void ath9k_stop(struct ieee80211_hw *hw)
810 {
811 struct ath_softc *sc = hw->priv;
812 struct ath_hw *ah = sc->sc_ah;
813 struct ath_common *common = ath9k_hw_common(ah);
814 bool prev_idle;
815
816 ath9k_deinit_channel_context(sc);
817
818 mutex_lock(&sc->mutex);
819
820 ath_cancel_work(sc);
821
822 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
823 ath_dbg(common, ANY, "Device not present\n");
824 mutex_unlock(&sc->mutex);
825 return;
826 }
827
828 /* Ensure HW is awake when we try to shut it down. */
829 ath9k_ps_wakeup(sc);
830
831 spin_lock_bh(&sc->sc_pcu_lock);
832
833 /* prevent tasklets to enable interrupts once we disable them */
834 ah->imask &= ~ATH9K_INT_GLOBAL;
835
836 /* make sure h/w will not generate any interrupt
837 * before setting the invalid flag. */
838 ath9k_hw_disable_interrupts(ah);
839
840 spin_unlock_bh(&sc->sc_pcu_lock);
841
842 /* we can now sync irq and kill any running tasklets, since we already
843 * disabled interrupts and not holding a spin lock */
844 synchronize_irq(sc->irq);
845 tasklet_kill(&sc->intr_tq);
846 tasklet_kill(&sc->bcon_tasklet);
847
848 prev_idle = sc->ps_idle;
849 sc->ps_idle = true;
850
851 spin_lock_bh(&sc->sc_pcu_lock);
852
853 if (ah->led_pin >= 0) {
854 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
855 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
856 }
857
858 ath_prepare_reset(sc);
859
860 if (sc->rx.frag) {
861 dev_kfree_skb_any(sc->rx.frag);
862 sc->rx.frag = NULL;
863 }
864
865 if (!ah->curchan)
866 ah->curchan = ath9k_cmn_get_channel(hw, ah,
867 &sc->cur_chan->chandef);
868
869 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
870 ath9k_hw_phy_disable(ah);
871
872 ath9k_hw_configpcipowersave(ah, true);
873
874 spin_unlock_bh(&sc->sc_pcu_lock);
875
876 ath9k_ps_restore(sc);
877
878 set_bit(ATH_OP_INVALID, &common->op_flags);
879 sc->ps_idle = prev_idle;
880
881 mutex_unlock(&sc->mutex);
882
883 ath_dbg(common, CONFIG, "Driver halt\n");
884 }
885
ath9k_uses_beacons(int type)886 static bool ath9k_uses_beacons(int type)
887 {
888 switch (type) {
889 case NL80211_IFTYPE_AP:
890 case NL80211_IFTYPE_ADHOC:
891 case NL80211_IFTYPE_MESH_POINT:
892 return true;
893 default:
894 return false;
895 }
896 }
897
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)898 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
899 u8 *mac, struct ieee80211_vif *vif)
900 {
901 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
902 int i;
903
904 if (iter_data->has_hw_macaddr) {
905 for (i = 0; i < ETH_ALEN; i++)
906 iter_data->mask[i] &=
907 ~(iter_data->hw_macaddr[i] ^ mac[i]);
908 } else {
909 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
910 iter_data->has_hw_macaddr = true;
911 }
912
913 if (!vif->bss_conf.use_short_slot)
914 iter_data->slottime = ATH9K_SLOT_TIME_20;
915
916 switch (vif->type) {
917 case NL80211_IFTYPE_AP:
918 iter_data->naps++;
919 break;
920 case NL80211_IFTYPE_STATION:
921 iter_data->nstations++;
922 if (avp->assoc && !iter_data->primary_sta)
923 iter_data->primary_sta = vif;
924 break;
925 case NL80211_IFTYPE_ADHOC:
926 iter_data->nadhocs++;
927 if (vif->bss_conf.enable_beacon)
928 iter_data->beacons = true;
929 break;
930 case NL80211_IFTYPE_MESH_POINT:
931 iter_data->nmeshes++;
932 if (vif->bss_conf.enable_beacon)
933 iter_data->beacons = true;
934 break;
935 case NL80211_IFTYPE_WDS:
936 iter_data->nwds++;
937 break;
938 default:
939 break;
940 }
941 }
942
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)943 static void ath9k_update_bssid_mask(struct ath_softc *sc,
944 struct ath_chanctx *ctx,
945 struct ath9k_vif_iter_data *iter_data)
946 {
947 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
948 struct ath_vif *avp;
949 int i;
950
951 if (!ath9k_is_chanctx_enabled())
952 return;
953
954 list_for_each_entry(avp, &ctx->vifs, list) {
955 if (ctx->nvifs_assigned != 1)
956 continue;
957
958 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
959 continue;
960
961 ether_addr_copy(common->curbssid, avp->bssid);
962
963 /* perm_addr will be used as the p2p device address. */
964 for (i = 0; i < ETH_ALEN; i++)
965 iter_data->mask[i] &=
966 ~(iter_data->hw_macaddr[i] ^
967 sc->hw->wiphy->perm_addr[i]);
968 }
969 }
970
971 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)972 void ath9k_calculate_iter_data(struct ath_softc *sc,
973 struct ath_chanctx *ctx,
974 struct ath9k_vif_iter_data *iter_data)
975 {
976 struct ath_vif *avp;
977
978 /*
979 * The hardware will use primary station addr together with the
980 * BSSID mask when matching addresses.
981 */
982 memset(iter_data, 0, sizeof(*iter_data));
983 memset(&iter_data->mask, 0xff, ETH_ALEN);
984 iter_data->slottime = ATH9K_SLOT_TIME_9;
985
986 list_for_each_entry(avp, &ctx->vifs, list)
987 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
988
989 ath9k_update_bssid_mask(sc, ctx, iter_data);
990 }
991
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)992 static void ath9k_set_assoc_state(struct ath_softc *sc,
993 struct ieee80211_vif *vif, bool changed)
994 {
995 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
996 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
997 unsigned long flags;
998
999 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1000
1001 ether_addr_copy(common->curbssid, avp->bssid);
1002 common->curaid = avp->aid;
1003 ath9k_hw_write_associd(sc->sc_ah);
1004
1005 if (changed) {
1006 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1007 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1008
1009 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1010 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1011 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1012 }
1013
1014 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1015 ath9k_mci_update_wlan_channels(sc, false);
1016
1017 ath_dbg(common, CONFIG,
1018 "Primary Station interface: %pM, BSSID: %pM\n",
1019 vif->addr, common->curbssid);
1020 }
1021
1022 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1023 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1024 {
1025 struct ath_hw *ah = sc->sc_ah;
1026 struct ath_common *common = ath9k_hw_common(ah);
1027 struct ieee80211_vif *vif = NULL;
1028
1029 ath9k_ps_wakeup(sc);
1030
1031 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1032 vif = sc->offchannel.scan_vif;
1033 else
1034 vif = sc->offchannel.roc_vif;
1035
1036 if (WARN_ON(!vif))
1037 goto exit;
1038
1039 eth_zero_addr(common->curbssid);
1040 eth_broadcast_addr(common->bssidmask);
1041 ether_addr_copy(common->macaddr, vif->addr);
1042 common->curaid = 0;
1043 ah->opmode = vif->type;
1044 ah->imask &= ~ATH9K_INT_SWBA;
1045 ah->imask &= ~ATH9K_INT_TSFOOR;
1046 ah->slottime = ATH9K_SLOT_TIME_9;
1047
1048 ath_hw_setbssidmask(common);
1049 ath9k_hw_setopmode(ah);
1050 ath9k_hw_write_associd(sc->sc_ah);
1051 ath9k_hw_set_interrupts(ah);
1052 ath9k_hw_init_global_settings(ah);
1053
1054 exit:
1055 ath9k_ps_restore(sc);
1056 }
1057 #endif
1058
1059 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1060 void ath9k_calculate_summary_state(struct ath_softc *sc,
1061 struct ath_chanctx *ctx)
1062 {
1063 struct ath_hw *ah = sc->sc_ah;
1064 struct ath_common *common = ath9k_hw_common(ah);
1065 struct ath9k_vif_iter_data iter_data;
1066 struct ath_beacon_config *cur_conf;
1067
1068 ath_chanctx_check_active(sc, ctx);
1069
1070 if (ctx != sc->cur_chan)
1071 return;
1072
1073 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1074 if (ctx == &sc->offchannel.chan)
1075 return ath9k_set_offchannel_state(sc);
1076 #endif
1077
1078 ath9k_ps_wakeup(sc);
1079 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1080
1081 if (iter_data.has_hw_macaddr)
1082 ether_addr_copy(common->macaddr, iter_data.hw_macaddr);
1083
1084 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1085 ath_hw_setbssidmask(common);
1086
1087 if (iter_data.naps > 0) {
1088 cur_conf = &ctx->beacon;
1089 ath9k_hw_set_tsfadjust(ah, true);
1090 ah->opmode = NL80211_IFTYPE_AP;
1091 if (cur_conf->enable_beacon)
1092 iter_data.beacons = true;
1093 } else {
1094 ath9k_hw_set_tsfadjust(ah, false);
1095
1096 if (iter_data.nmeshes)
1097 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1098 else if (iter_data.nwds)
1099 ah->opmode = NL80211_IFTYPE_AP;
1100 else if (iter_data.nadhocs)
1101 ah->opmode = NL80211_IFTYPE_ADHOC;
1102 else
1103 ah->opmode = NL80211_IFTYPE_STATION;
1104 }
1105
1106 ath9k_hw_setopmode(ah);
1107
1108 ctx->switch_after_beacon = false;
1109 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1110 ah->imask |= ATH9K_INT_TSFOOR;
1111 else {
1112 ah->imask &= ~ATH9K_INT_TSFOOR;
1113 if (iter_data.naps == 1 && iter_data.beacons)
1114 ctx->switch_after_beacon = true;
1115 }
1116
1117 ah->imask &= ~ATH9K_INT_SWBA;
1118 if (ah->opmode == NL80211_IFTYPE_STATION) {
1119 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1120
1121 if (iter_data.primary_sta) {
1122 iter_data.beacons = true;
1123 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1124 changed);
1125 ctx->primary_sta = iter_data.primary_sta;
1126 } else {
1127 ctx->primary_sta = NULL;
1128 memset(common->curbssid, 0, ETH_ALEN);
1129 common->curaid = 0;
1130 ath9k_hw_write_associd(sc->sc_ah);
1131 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1132 ath9k_mci_update_wlan_channels(sc, true);
1133 }
1134 } else if (iter_data.beacons) {
1135 ah->imask |= ATH9K_INT_SWBA;
1136 }
1137 ath9k_hw_set_interrupts(ah);
1138
1139 if (iter_data.beacons)
1140 set_bit(ATH_OP_BEACONS, &common->op_flags);
1141 else
1142 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1143
1144 if (ah->slottime != iter_data.slottime) {
1145 ah->slottime = iter_data.slottime;
1146 ath9k_hw_init_global_settings(ah);
1147 }
1148
1149 if (iter_data.primary_sta)
1150 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1151 else
1152 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1153
1154 ath_dbg(common, CONFIG,
1155 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1156 common->macaddr, common->curbssid, common->bssidmask);
1157
1158 ath9k_ps_restore(sc);
1159 }
1160
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1161 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1162 struct ieee80211_vif *vif)
1163 {
1164 int i;
1165
1166 if (!ath9k_is_chanctx_enabled())
1167 return;
1168
1169 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1170 vif->hw_queue[i] = i;
1171
1172 if (vif->type == NL80211_IFTYPE_AP)
1173 vif->cab_queue = hw->queues - 2;
1174 else
1175 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1176 }
1177
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1178 static int ath9k_add_interface(struct ieee80211_hw *hw,
1179 struct ieee80211_vif *vif)
1180 {
1181 struct ath_softc *sc = hw->priv;
1182 struct ath_hw *ah = sc->sc_ah;
1183 struct ath_common *common = ath9k_hw_common(ah);
1184 struct ath_vif *avp = (void *)vif->drv_priv;
1185 struct ath_node *an = &avp->mcast_node;
1186
1187 mutex_lock(&sc->mutex);
1188
1189 if (config_enabled(CONFIG_ATH9K_TX99)) {
1190 if (sc->cur_chan->nvifs >= 1) {
1191 mutex_unlock(&sc->mutex);
1192 return -EOPNOTSUPP;
1193 }
1194 sc->tx99_vif = vif;
1195 }
1196
1197 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1198 sc->cur_chan->nvifs++;
1199
1200 if (ath9k_uses_beacons(vif->type))
1201 ath9k_beacon_assign_slot(sc, vif);
1202
1203 avp->vif = vif;
1204 if (!ath9k_is_chanctx_enabled()) {
1205 avp->chanctx = sc->cur_chan;
1206 list_add_tail(&avp->list, &avp->chanctx->vifs);
1207 }
1208
1209 ath9k_calculate_summary_state(sc, avp->chanctx);
1210
1211 ath9k_assign_hw_queues(hw, vif);
1212
1213 an->sc = sc;
1214 an->sta = NULL;
1215 an->vif = vif;
1216 an->no_ps_filter = true;
1217 ath_tx_node_init(sc, an);
1218
1219 mutex_unlock(&sc->mutex);
1220 return 0;
1221 }
1222
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1223 static int ath9k_change_interface(struct ieee80211_hw *hw,
1224 struct ieee80211_vif *vif,
1225 enum nl80211_iftype new_type,
1226 bool p2p)
1227 {
1228 struct ath_softc *sc = hw->priv;
1229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1230 struct ath_vif *avp = (void *)vif->drv_priv;
1231
1232 mutex_lock(&sc->mutex);
1233
1234 if (config_enabled(CONFIG_ATH9K_TX99)) {
1235 mutex_unlock(&sc->mutex);
1236 return -EOPNOTSUPP;
1237 }
1238
1239 ath_dbg(common, CONFIG, "Change Interface\n");
1240
1241 if (ath9k_uses_beacons(vif->type))
1242 ath9k_beacon_remove_slot(sc, vif);
1243
1244 vif->type = new_type;
1245 vif->p2p = p2p;
1246
1247 if (ath9k_uses_beacons(vif->type))
1248 ath9k_beacon_assign_slot(sc, vif);
1249
1250 ath9k_assign_hw_queues(hw, vif);
1251 ath9k_calculate_summary_state(sc, avp->chanctx);
1252
1253 mutex_unlock(&sc->mutex);
1254 return 0;
1255 }
1256
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1257 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1258 struct ieee80211_vif *vif)
1259 {
1260 struct ath_softc *sc = hw->priv;
1261 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1262 struct ath_vif *avp = (void *)vif->drv_priv;
1263
1264 ath_dbg(common, CONFIG, "Detach Interface\n");
1265
1266 mutex_lock(&sc->mutex);
1267
1268 ath9k_p2p_remove_vif(sc, vif);
1269
1270 sc->cur_chan->nvifs--;
1271 sc->tx99_vif = NULL;
1272 if (!ath9k_is_chanctx_enabled())
1273 list_del(&avp->list);
1274
1275 if (ath9k_uses_beacons(vif->type))
1276 ath9k_beacon_remove_slot(sc, vif);
1277
1278 ath_tx_node_cleanup(sc, &avp->mcast_node);
1279
1280 ath9k_calculate_summary_state(sc, avp->chanctx);
1281
1282 mutex_unlock(&sc->mutex);
1283 }
1284
ath9k_enable_ps(struct ath_softc * sc)1285 static void ath9k_enable_ps(struct ath_softc *sc)
1286 {
1287 struct ath_hw *ah = sc->sc_ah;
1288 struct ath_common *common = ath9k_hw_common(ah);
1289
1290 if (config_enabled(CONFIG_ATH9K_TX99))
1291 return;
1292
1293 sc->ps_enabled = true;
1294 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1295 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1296 ah->imask |= ATH9K_INT_TIM_TIMER;
1297 ath9k_hw_set_interrupts(ah);
1298 }
1299 ath9k_hw_setrxabort(ah, 1);
1300 }
1301 ath_dbg(common, PS, "PowerSave enabled\n");
1302 }
1303
ath9k_disable_ps(struct ath_softc * sc)1304 static void ath9k_disable_ps(struct ath_softc *sc)
1305 {
1306 struct ath_hw *ah = sc->sc_ah;
1307 struct ath_common *common = ath9k_hw_common(ah);
1308
1309 if (config_enabled(CONFIG_ATH9K_TX99))
1310 return;
1311
1312 sc->ps_enabled = false;
1313 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1314 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1315 ath9k_hw_setrxabort(ah, 0);
1316 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1317 PS_WAIT_FOR_CAB |
1318 PS_WAIT_FOR_PSPOLL_DATA |
1319 PS_WAIT_FOR_TX_ACK);
1320 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1321 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1322 ath9k_hw_set_interrupts(ah);
1323 }
1324 }
1325 ath_dbg(common, PS, "PowerSave disabled\n");
1326 }
1327
ath9k_spectral_scan_trigger(struct ieee80211_hw * hw)1328 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1329 {
1330 struct ath_softc *sc = hw->priv;
1331 struct ath_hw *ah = sc->sc_ah;
1332 struct ath_common *common = ath9k_hw_common(ah);
1333 u32 rxfilter;
1334
1335 if (config_enabled(CONFIG_ATH9K_TX99))
1336 return;
1337
1338 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1339 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1340 return;
1341 }
1342
1343 ath9k_ps_wakeup(sc);
1344 rxfilter = ath9k_hw_getrxfilter(ah);
1345 ath9k_hw_setrxfilter(ah, rxfilter |
1346 ATH9K_RX_FILTER_PHYRADAR |
1347 ATH9K_RX_FILTER_PHYERR);
1348
1349 /* TODO: usually this should not be neccesary, but for some reason
1350 * (or in some mode?) the trigger must be called after the
1351 * configuration, otherwise the register will have its values reset
1352 * (on my ar9220 to value 0x01002310)
1353 */
1354 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1355 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1356 ath9k_ps_restore(sc);
1357 }
1358
ath9k_spectral_scan_config(struct ieee80211_hw * hw,enum spectral_mode spectral_mode)1359 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1360 enum spectral_mode spectral_mode)
1361 {
1362 struct ath_softc *sc = hw->priv;
1363 struct ath_hw *ah = sc->sc_ah;
1364 struct ath_common *common = ath9k_hw_common(ah);
1365
1366 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1367 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1368 return -1;
1369 }
1370
1371 switch (spectral_mode) {
1372 case SPECTRAL_DISABLED:
1373 sc->spec_config.enabled = 0;
1374 break;
1375 case SPECTRAL_BACKGROUND:
1376 /* send endless samples.
1377 * TODO: is this really useful for "background"?
1378 */
1379 sc->spec_config.endless = 1;
1380 sc->spec_config.enabled = 1;
1381 break;
1382 case SPECTRAL_CHANSCAN:
1383 case SPECTRAL_MANUAL:
1384 sc->spec_config.endless = 0;
1385 sc->spec_config.enabled = 1;
1386 break;
1387 default:
1388 return -1;
1389 }
1390
1391 ath9k_ps_wakeup(sc);
1392 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
1393 ath9k_ps_restore(sc);
1394
1395 sc->spectral_mode = spectral_mode;
1396
1397 return 0;
1398 }
1399
ath9k_config(struct ieee80211_hw * hw,u32 changed)1400 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1401 {
1402 struct ath_softc *sc = hw->priv;
1403 struct ath_hw *ah = sc->sc_ah;
1404 struct ath_common *common = ath9k_hw_common(ah);
1405 struct ieee80211_conf *conf = &hw->conf;
1406 struct ath_chanctx *ctx = sc->cur_chan;
1407
1408 ath9k_ps_wakeup(sc);
1409 mutex_lock(&sc->mutex);
1410
1411 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1412 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1413 if (sc->ps_idle) {
1414 ath_cancel_work(sc);
1415 ath9k_stop_btcoex(sc);
1416 } else {
1417 ath9k_start_btcoex(sc);
1418 /*
1419 * The chip needs a reset to properly wake up from
1420 * full sleep
1421 */
1422 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1423 }
1424 }
1425
1426 /*
1427 * We just prepare to enable PS. We have to wait until our AP has
1428 * ACK'd our null data frame to disable RX otherwise we'll ignore
1429 * those ACKs and end up retransmitting the same null data frames.
1430 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1431 */
1432 if (changed & IEEE80211_CONF_CHANGE_PS) {
1433 unsigned long flags;
1434 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1435 if (conf->flags & IEEE80211_CONF_PS)
1436 ath9k_enable_ps(sc);
1437 else
1438 ath9k_disable_ps(sc);
1439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1440 }
1441
1442 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1443 if (conf->flags & IEEE80211_CONF_MONITOR) {
1444 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1445 sc->sc_ah->is_monitoring = true;
1446 } else {
1447 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1448 sc->sc_ah->is_monitoring = false;
1449 }
1450 }
1451
1452 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1453 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1454 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1455 }
1456
1457 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1458 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1459 sc->cur_chan->txpower = 2 * conf->power_level;
1460 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1461 sc->cur_chan->txpower, &sc->curtxpow);
1462 }
1463
1464 mutex_unlock(&sc->mutex);
1465 ath9k_ps_restore(sc);
1466
1467 return 0;
1468 }
1469
1470 #define SUPPORTED_FILTERS \
1471 (FIF_PROMISC_IN_BSS | \
1472 FIF_ALLMULTI | \
1473 FIF_CONTROL | \
1474 FIF_PSPOLL | \
1475 FIF_OTHER_BSS | \
1476 FIF_BCN_PRBRESP_PROMISC | \
1477 FIF_PROBE_REQ | \
1478 FIF_FCSFAIL)
1479
1480 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1481 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1482 unsigned int changed_flags,
1483 unsigned int *total_flags,
1484 u64 multicast)
1485 {
1486 struct ath_softc *sc = hw->priv;
1487 u32 rfilt;
1488
1489 changed_flags &= SUPPORTED_FILTERS;
1490 *total_flags &= SUPPORTED_FILTERS;
1491
1492 spin_lock_bh(&sc->chan_lock);
1493 sc->cur_chan->rxfilter = *total_flags;
1494 spin_unlock_bh(&sc->chan_lock);
1495
1496 ath9k_ps_wakeup(sc);
1497 rfilt = ath_calcrxfilter(sc);
1498 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1499 ath9k_ps_restore(sc);
1500
1501 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1502 rfilt);
1503 }
1504
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1505 static int ath9k_sta_add(struct ieee80211_hw *hw,
1506 struct ieee80211_vif *vif,
1507 struct ieee80211_sta *sta)
1508 {
1509 struct ath_softc *sc = hw->priv;
1510 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1511 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1512 struct ieee80211_key_conf ps_key = { };
1513 int key;
1514
1515 ath_node_attach(sc, sta, vif);
1516
1517 if (vif->type != NL80211_IFTYPE_AP &&
1518 vif->type != NL80211_IFTYPE_AP_VLAN)
1519 return 0;
1520
1521 key = ath_key_config(common, vif, sta, &ps_key);
1522 if (key > 0) {
1523 an->ps_key = key;
1524 an->key_idx[0] = key;
1525 }
1526
1527 return 0;
1528 }
1529
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1530 static void ath9k_del_ps_key(struct ath_softc *sc,
1531 struct ieee80211_vif *vif,
1532 struct ieee80211_sta *sta)
1533 {
1534 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1535 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1536 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1537
1538 if (!an->ps_key)
1539 return;
1540
1541 ath_key_delete(common, &ps_key);
1542 an->ps_key = 0;
1543 an->key_idx[0] = 0;
1544 }
1545
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1546 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1547 struct ieee80211_vif *vif,
1548 struct ieee80211_sta *sta)
1549 {
1550 struct ath_softc *sc = hw->priv;
1551
1552 ath9k_del_ps_key(sc, vif, sta);
1553 ath_node_detach(sc, sta);
1554
1555 return 0;
1556 }
1557
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1558 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1559 struct ath_node *an,
1560 bool set)
1561 {
1562 int i;
1563
1564 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1565 if (!an->key_idx[i])
1566 continue;
1567 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1568 }
1569 }
1570
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1571 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1572 struct ieee80211_vif *vif,
1573 enum sta_notify_cmd cmd,
1574 struct ieee80211_sta *sta)
1575 {
1576 struct ath_softc *sc = hw->priv;
1577 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1578
1579 switch (cmd) {
1580 case STA_NOTIFY_SLEEP:
1581 an->sleeping = true;
1582 ath_tx_aggr_sleep(sta, sc, an);
1583 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1584 break;
1585 case STA_NOTIFY_AWAKE:
1586 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1587 an->sleeping = false;
1588 ath_tx_aggr_wakeup(sc, an);
1589 break;
1590 }
1591 }
1592
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1593 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1594 struct ieee80211_vif *vif, u16 queue,
1595 const struct ieee80211_tx_queue_params *params)
1596 {
1597 struct ath_softc *sc = hw->priv;
1598 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599 struct ath_txq *txq;
1600 struct ath9k_tx_queue_info qi;
1601 int ret = 0;
1602
1603 if (queue >= IEEE80211_NUM_ACS)
1604 return 0;
1605
1606 txq = sc->tx.txq_map[queue];
1607
1608 ath9k_ps_wakeup(sc);
1609 mutex_lock(&sc->mutex);
1610
1611 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1612
1613 qi.tqi_aifs = params->aifs;
1614 qi.tqi_cwmin = params->cw_min;
1615 qi.tqi_cwmax = params->cw_max;
1616 qi.tqi_burstTime = params->txop * 32;
1617
1618 ath_dbg(common, CONFIG,
1619 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1620 queue, txq->axq_qnum, params->aifs, params->cw_min,
1621 params->cw_max, params->txop);
1622
1623 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1624 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1625 if (ret)
1626 ath_err(common, "TXQ Update failed\n");
1627
1628 mutex_unlock(&sc->mutex);
1629 ath9k_ps_restore(sc);
1630
1631 return ret;
1632 }
1633
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1634 static int ath9k_set_key(struct ieee80211_hw *hw,
1635 enum set_key_cmd cmd,
1636 struct ieee80211_vif *vif,
1637 struct ieee80211_sta *sta,
1638 struct ieee80211_key_conf *key)
1639 {
1640 struct ath_softc *sc = hw->priv;
1641 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1642 struct ath_node *an = NULL;
1643 int ret = 0, i;
1644
1645 if (ath9k_modparam_nohwcrypt)
1646 return -ENOSPC;
1647
1648 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1649 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1650 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1651 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1652 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1653 /*
1654 * For now, disable hw crypto for the RSN IBSS group keys. This
1655 * could be optimized in the future to use a modified key cache
1656 * design to support per-STA RX GTK, but until that gets
1657 * implemented, use of software crypto for group addressed
1658 * frames is a acceptable to allow RSN IBSS to be used.
1659 */
1660 return -EOPNOTSUPP;
1661 }
1662
1663 mutex_lock(&sc->mutex);
1664 ath9k_ps_wakeup(sc);
1665 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1666 if (sta)
1667 an = (struct ath_node *)sta->drv_priv;
1668
1669 switch (cmd) {
1670 case SET_KEY:
1671 if (sta)
1672 ath9k_del_ps_key(sc, vif, sta);
1673
1674 key->hw_key_idx = 0;
1675 ret = ath_key_config(common, vif, sta, key);
1676 if (ret >= 0) {
1677 key->hw_key_idx = ret;
1678 /* push IV and Michael MIC generation to stack */
1679 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1680 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1681 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1682 if (sc->sc_ah->sw_mgmt_crypto &&
1683 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1684 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1685 ret = 0;
1686 }
1687 if (an && key->hw_key_idx) {
1688 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1689 if (an->key_idx[i])
1690 continue;
1691 an->key_idx[i] = key->hw_key_idx;
1692 break;
1693 }
1694 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1695 }
1696 break;
1697 case DISABLE_KEY:
1698 ath_key_delete(common, key);
1699 if (an) {
1700 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1701 if (an->key_idx[i] != key->hw_key_idx)
1702 continue;
1703 an->key_idx[i] = 0;
1704 break;
1705 }
1706 }
1707 key->hw_key_idx = 0;
1708 break;
1709 default:
1710 ret = -EINVAL;
1711 }
1712
1713 ath9k_ps_restore(sc);
1714 mutex_unlock(&sc->mutex);
1715
1716 return ret;
1717 }
1718
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1719 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1720 struct ieee80211_vif *vif,
1721 struct ieee80211_bss_conf *bss_conf,
1722 u32 changed)
1723 {
1724 #define CHECK_ANI \
1725 (BSS_CHANGED_ASSOC | \
1726 BSS_CHANGED_IBSS | \
1727 BSS_CHANGED_BEACON_ENABLED)
1728
1729 struct ath_softc *sc = hw->priv;
1730 struct ath_hw *ah = sc->sc_ah;
1731 struct ath_common *common = ath9k_hw_common(ah);
1732 struct ath_vif *avp = (void *)vif->drv_priv;
1733 int slottime;
1734
1735 ath9k_ps_wakeup(sc);
1736 mutex_lock(&sc->mutex);
1737
1738 if (changed & BSS_CHANGED_ASSOC) {
1739 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1740 bss_conf->bssid, bss_conf->assoc);
1741
1742 ether_addr_copy(avp->bssid, bss_conf->bssid);
1743 avp->aid = bss_conf->aid;
1744 avp->assoc = bss_conf->assoc;
1745
1746 ath9k_calculate_summary_state(sc, avp->chanctx);
1747
1748 if (ath9k_is_chanctx_enabled()) {
1749 if (bss_conf->assoc)
1750 ath_chanctx_event(sc, vif,
1751 ATH_CHANCTX_EVENT_ASSOC);
1752 }
1753 }
1754
1755 if (changed & BSS_CHANGED_IBSS) {
1756 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1757 common->curaid = bss_conf->aid;
1758 ath9k_hw_write_associd(sc->sc_ah);
1759 }
1760
1761 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1762 (changed & BSS_CHANGED_BEACON_INT) ||
1763 (changed & BSS_CHANGED_BEACON_INFO)) {
1764 ath9k_beacon_config(sc, vif, changed);
1765 if (changed & BSS_CHANGED_BEACON_ENABLED)
1766 ath9k_calculate_summary_state(sc, avp->chanctx);
1767 }
1768
1769 if ((avp->chanctx == sc->cur_chan) &&
1770 (changed & BSS_CHANGED_ERP_SLOT)) {
1771 if (bss_conf->use_short_slot)
1772 slottime = 9;
1773 else
1774 slottime = 20;
1775 if (vif->type == NL80211_IFTYPE_AP) {
1776 /*
1777 * Defer update, so that connected stations can adjust
1778 * their settings at the same time.
1779 * See beacon.c for more details
1780 */
1781 sc->beacon.slottime = slottime;
1782 sc->beacon.updateslot = UPDATE;
1783 } else {
1784 ah->slottime = slottime;
1785 ath9k_hw_init_global_settings(ah);
1786 }
1787 }
1788
1789 if (changed & BSS_CHANGED_P2P_PS)
1790 ath9k_p2p_bss_info_changed(sc, vif);
1791
1792 if (changed & CHECK_ANI)
1793 ath_check_ani(sc);
1794
1795 mutex_unlock(&sc->mutex);
1796 ath9k_ps_restore(sc);
1797
1798 #undef CHECK_ANI
1799 }
1800
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1801 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1802 {
1803 struct ath_softc *sc = hw->priv;
1804 u64 tsf;
1805
1806 mutex_lock(&sc->mutex);
1807 ath9k_ps_wakeup(sc);
1808 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1809 ath9k_ps_restore(sc);
1810 mutex_unlock(&sc->mutex);
1811
1812 return tsf;
1813 }
1814
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1815 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1816 struct ieee80211_vif *vif,
1817 u64 tsf)
1818 {
1819 struct ath_softc *sc = hw->priv;
1820
1821 mutex_lock(&sc->mutex);
1822 ath9k_ps_wakeup(sc);
1823 ath9k_hw_settsf64(sc->sc_ah, tsf);
1824 ath9k_ps_restore(sc);
1825 mutex_unlock(&sc->mutex);
1826 }
1827
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1828 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1829 {
1830 struct ath_softc *sc = hw->priv;
1831
1832 mutex_lock(&sc->mutex);
1833
1834 ath9k_ps_wakeup(sc);
1835 ath9k_hw_reset_tsf(sc->sc_ah);
1836 ath9k_ps_restore(sc);
1837
1838 mutex_unlock(&sc->mutex);
1839 }
1840
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum ieee80211_ampdu_mlme_action action,struct ieee80211_sta * sta,u16 tid,u16 * ssn,u8 buf_size)1841 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1842 struct ieee80211_vif *vif,
1843 enum ieee80211_ampdu_mlme_action action,
1844 struct ieee80211_sta *sta,
1845 u16 tid, u16 *ssn, u8 buf_size)
1846 {
1847 struct ath_softc *sc = hw->priv;
1848 bool flush = false;
1849 int ret = 0;
1850
1851 mutex_lock(&sc->mutex);
1852
1853 switch (action) {
1854 case IEEE80211_AMPDU_RX_START:
1855 break;
1856 case IEEE80211_AMPDU_RX_STOP:
1857 break;
1858 case IEEE80211_AMPDU_TX_START:
1859 ath9k_ps_wakeup(sc);
1860 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1861 if (!ret)
1862 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1863 ath9k_ps_restore(sc);
1864 break;
1865 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1866 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1867 flush = true;
1868 case IEEE80211_AMPDU_TX_STOP_CONT:
1869 ath9k_ps_wakeup(sc);
1870 ath_tx_aggr_stop(sc, sta, tid);
1871 if (!flush)
1872 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1873 ath9k_ps_restore(sc);
1874 break;
1875 case IEEE80211_AMPDU_TX_OPERATIONAL:
1876 ath9k_ps_wakeup(sc);
1877 ath_tx_aggr_resume(sc, sta, tid);
1878 ath9k_ps_restore(sc);
1879 break;
1880 default:
1881 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1882 }
1883
1884 mutex_unlock(&sc->mutex);
1885
1886 return ret;
1887 }
1888
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)1889 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1890 struct survey_info *survey)
1891 {
1892 struct ath_softc *sc = hw->priv;
1893 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1894 struct ieee80211_supported_band *sband;
1895 struct ieee80211_channel *chan;
1896 int pos;
1897
1898 if (config_enabled(CONFIG_ATH9K_TX99))
1899 return -EOPNOTSUPP;
1900
1901 spin_lock_bh(&common->cc_lock);
1902 if (idx == 0)
1903 ath_update_survey_stats(sc);
1904
1905 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1906 if (sband && idx >= sband->n_channels) {
1907 idx -= sband->n_channels;
1908 sband = NULL;
1909 }
1910
1911 if (!sband)
1912 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1913
1914 if (!sband || idx >= sband->n_channels) {
1915 spin_unlock_bh(&common->cc_lock);
1916 return -ENOENT;
1917 }
1918
1919 chan = &sband->channels[idx];
1920 pos = chan->hw_value;
1921 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1922 survey->channel = chan;
1923 spin_unlock_bh(&common->cc_lock);
1924
1925 return 0;
1926 }
1927
ath9k_enable_dynack(struct ath_softc * sc)1928 static void ath9k_enable_dynack(struct ath_softc *sc)
1929 {
1930 #ifdef CONFIG_ATH9K_DYNACK
1931 u32 rfilt;
1932 struct ath_hw *ah = sc->sc_ah;
1933
1934 ath_dynack_reset(ah);
1935
1936 ah->dynack.enabled = true;
1937 rfilt = ath_calcrxfilter(sc);
1938 ath9k_hw_setrxfilter(ah, rfilt);
1939 #endif
1940 }
1941
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)1942 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1943 s16 coverage_class)
1944 {
1945 struct ath_softc *sc = hw->priv;
1946 struct ath_hw *ah = sc->sc_ah;
1947
1948 if (config_enabled(CONFIG_ATH9K_TX99))
1949 return;
1950
1951 mutex_lock(&sc->mutex);
1952
1953 if (coverage_class >= 0) {
1954 ah->coverage_class = coverage_class;
1955 if (ah->dynack.enabled) {
1956 u32 rfilt;
1957
1958 ah->dynack.enabled = false;
1959 rfilt = ath_calcrxfilter(sc);
1960 ath9k_hw_setrxfilter(ah, rfilt);
1961 }
1962 ath9k_ps_wakeup(sc);
1963 ath9k_hw_init_global_settings(ah);
1964 ath9k_ps_restore(sc);
1965 } else if (!ah->dynack.enabled) {
1966 ath9k_enable_dynack(sc);
1967 }
1968
1969 mutex_unlock(&sc->mutex);
1970 }
1971
ath9k_has_tx_pending(struct ath_softc * sc)1972 static bool ath9k_has_tx_pending(struct ath_softc *sc)
1973 {
1974 int i, npend = 0;
1975
1976 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1977 if (!ATH_TXQ_SETUP(sc, i))
1978 continue;
1979
1980 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1981 if (npend)
1982 break;
1983 }
1984
1985 return !!npend;
1986 }
1987
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)1988 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1989 u32 queues, bool drop)
1990 {
1991 struct ath_softc *sc = hw->priv;
1992
1993 mutex_lock(&sc->mutex);
1994 __ath9k_flush(hw, queues, drop);
1995 mutex_unlock(&sc->mutex);
1996 }
1997
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1998 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1999 {
2000 struct ath_softc *sc = hw->priv;
2001 struct ath_hw *ah = sc->sc_ah;
2002 struct ath_common *common = ath9k_hw_common(ah);
2003 int timeout = HZ / 5; /* 200 ms */
2004 bool drain_txq;
2005
2006 cancel_delayed_work_sync(&sc->tx_complete_work);
2007
2008 if (ah->ah_flags & AH_UNPLUGGED) {
2009 ath_dbg(common, ANY, "Device has been unplugged!\n");
2010 return;
2011 }
2012
2013 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2014 ath_dbg(common, ANY, "Device not present\n");
2015 return;
2016 }
2017
2018 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
2019 timeout) > 0)
2020 drop = false;
2021
2022 if (drop) {
2023 ath9k_ps_wakeup(sc);
2024 spin_lock_bh(&sc->sc_pcu_lock);
2025 drain_txq = ath_drain_all_txq(sc);
2026 spin_unlock_bh(&sc->sc_pcu_lock);
2027
2028 if (!drain_txq)
2029 ath_reset(sc);
2030
2031 ath9k_ps_restore(sc);
2032 }
2033
2034 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2035 }
2036
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2037 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2038 {
2039 struct ath_softc *sc = hw->priv;
2040
2041 return ath9k_has_tx_pending(sc);
2042 }
2043
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2044 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2045 {
2046 struct ath_softc *sc = hw->priv;
2047 struct ath_hw *ah = sc->sc_ah;
2048 struct ieee80211_vif *vif;
2049 struct ath_vif *avp;
2050 struct ath_buf *bf;
2051 struct ath_tx_status ts;
2052 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2053 int status;
2054
2055 vif = sc->beacon.bslot[0];
2056 if (!vif)
2057 return 0;
2058
2059 if (!vif->bss_conf.enable_beacon)
2060 return 0;
2061
2062 avp = (void *)vif->drv_priv;
2063
2064 if (!sc->beacon.tx_processed && !edma) {
2065 tasklet_disable(&sc->bcon_tasklet);
2066
2067 bf = avp->av_bcbuf;
2068 if (!bf || !bf->bf_mpdu)
2069 goto skip;
2070
2071 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2072 if (status == -EINPROGRESS)
2073 goto skip;
2074
2075 sc->beacon.tx_processed = true;
2076 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2077
2078 skip:
2079 tasklet_enable(&sc->bcon_tasklet);
2080 }
2081
2082 return sc->beacon.tx_last;
2083 }
2084
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2085 static int ath9k_get_stats(struct ieee80211_hw *hw,
2086 struct ieee80211_low_level_stats *stats)
2087 {
2088 struct ath_softc *sc = hw->priv;
2089 struct ath_hw *ah = sc->sc_ah;
2090 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2091
2092 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2093 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2094 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2095 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2096 return 0;
2097 }
2098
fill_chainmask(u32 cap,u32 new)2099 static u32 fill_chainmask(u32 cap, u32 new)
2100 {
2101 u32 filled = 0;
2102 int i;
2103
2104 for (i = 0; cap && new; i++, cap >>= 1) {
2105 if (!(cap & BIT(0)))
2106 continue;
2107
2108 if (new & BIT(0))
2109 filled |= BIT(i);
2110
2111 new >>= 1;
2112 }
2113
2114 return filled;
2115 }
2116
validate_antenna_mask(struct ath_hw * ah,u32 val)2117 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2118 {
2119 if (AR_SREV_9300_20_OR_LATER(ah))
2120 return true;
2121
2122 switch (val & 0x7) {
2123 case 0x1:
2124 case 0x3:
2125 case 0x7:
2126 return true;
2127 case 0x2:
2128 return (ah->caps.rx_chainmask == 1);
2129 default:
2130 return false;
2131 }
2132 }
2133
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2134 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2135 {
2136 struct ath_softc *sc = hw->priv;
2137 struct ath_hw *ah = sc->sc_ah;
2138
2139 if (ah->caps.rx_chainmask != 1)
2140 rx_ant |= tx_ant;
2141
2142 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2143 return -EINVAL;
2144
2145 sc->ant_rx = rx_ant;
2146 sc->ant_tx = tx_ant;
2147
2148 if (ah->caps.rx_chainmask == 1)
2149 return 0;
2150
2151 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2152 if (AR_SREV_9100(ah))
2153 ah->rxchainmask = 0x7;
2154 else
2155 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2156
2157 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2158 ath9k_cmn_reload_chainmask(ah);
2159
2160 return 0;
2161 }
2162
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2163 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2164 {
2165 struct ath_softc *sc = hw->priv;
2166
2167 *tx_ant = sc->ant_tx;
2168 *rx_ant = sc->ant_rx;
2169 return 0;
2170 }
2171
ath9k_sw_scan_start(struct ieee80211_hw * hw)2172 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2173 {
2174 struct ath_softc *sc = hw->priv;
2175 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2176 set_bit(ATH_OP_SCANNING, &common->op_flags);
2177 }
2178
ath9k_sw_scan_complete(struct ieee80211_hw * hw)2179 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2180 {
2181 struct ath_softc *sc = hw->priv;
2182 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2183 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2184 }
2185
2186 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2187
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2188 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2189 struct ieee80211_scan_request *hw_req)
2190 {
2191 struct cfg80211_scan_request *req = &hw_req->req;
2192 struct ath_softc *sc = hw->priv;
2193 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2194 int ret = 0;
2195
2196 mutex_lock(&sc->mutex);
2197
2198 if (WARN_ON(sc->offchannel.scan_req)) {
2199 ret = -EBUSY;
2200 goto out;
2201 }
2202
2203 ath9k_ps_wakeup(sc);
2204 set_bit(ATH_OP_SCANNING, &common->op_flags);
2205 sc->offchannel.scan_vif = vif;
2206 sc->offchannel.scan_req = req;
2207 sc->offchannel.scan_idx = 0;
2208
2209 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2210 vif->addr);
2211
2212 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2213 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2214 ath_offchannel_next(sc);
2215 }
2216
2217 out:
2218 mutex_unlock(&sc->mutex);
2219
2220 return ret;
2221 }
2222
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2223 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2224 struct ieee80211_vif *vif)
2225 {
2226 struct ath_softc *sc = hw->priv;
2227 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2228
2229 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2230
2231 mutex_lock(&sc->mutex);
2232 del_timer_sync(&sc->offchannel.timer);
2233 ath_scan_complete(sc, true);
2234 mutex_unlock(&sc->mutex);
2235 }
2236
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2237 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2238 struct ieee80211_vif *vif,
2239 struct ieee80211_channel *chan, int duration,
2240 enum ieee80211_roc_type type)
2241 {
2242 struct ath_softc *sc = hw->priv;
2243 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2244 int ret = 0;
2245
2246 mutex_lock(&sc->mutex);
2247
2248 if (WARN_ON(sc->offchannel.roc_vif)) {
2249 ret = -EBUSY;
2250 goto out;
2251 }
2252
2253 ath9k_ps_wakeup(sc);
2254 sc->offchannel.roc_vif = vif;
2255 sc->offchannel.roc_chan = chan;
2256 sc->offchannel.roc_duration = duration;
2257
2258 ath_dbg(common, CHAN_CTX,
2259 "RoC request on vif: %pM, type: %d duration: %d\n",
2260 vif->addr, type, duration);
2261
2262 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2263 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2264 ath_offchannel_next(sc);
2265 }
2266
2267 out:
2268 mutex_unlock(&sc->mutex);
2269
2270 return ret;
2271 }
2272
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw)2273 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2274 {
2275 struct ath_softc *sc = hw->priv;
2276 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2277
2278 mutex_lock(&sc->mutex);
2279
2280 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2281 del_timer_sync(&sc->offchannel.timer);
2282
2283 if (sc->offchannel.roc_vif) {
2284 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2285 ath_roc_complete(sc, true);
2286 }
2287
2288 mutex_unlock(&sc->mutex);
2289
2290 return 0;
2291 }
2292
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2293 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2294 struct ieee80211_chanctx_conf *conf)
2295 {
2296 struct ath_softc *sc = hw->priv;
2297 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2298 struct ath_chanctx *ctx, **ptr;
2299 int pos;
2300
2301 mutex_lock(&sc->mutex);
2302
2303 ath_for_each_chanctx(sc, ctx) {
2304 if (ctx->assigned)
2305 continue;
2306
2307 ptr = (void *) conf->drv_priv;
2308 *ptr = ctx;
2309 ctx->assigned = true;
2310 pos = ctx - &sc->chanctx[0];
2311 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2312
2313 ath_dbg(common, CHAN_CTX,
2314 "Add channel context: %d MHz\n",
2315 conf->def.chan->center_freq);
2316
2317 ath_chanctx_set_channel(sc, ctx, &conf->def);
2318 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN);
2319
2320 mutex_unlock(&sc->mutex);
2321 return 0;
2322 }
2323
2324 mutex_unlock(&sc->mutex);
2325 return -ENOSPC;
2326 }
2327
2328
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2329 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2330 struct ieee80211_chanctx_conf *conf)
2331 {
2332 struct ath_softc *sc = hw->priv;
2333 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2334 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2335
2336 mutex_lock(&sc->mutex);
2337
2338 ath_dbg(common, CHAN_CTX,
2339 "Remove channel context: %d MHz\n",
2340 conf->def.chan->center_freq);
2341
2342 ctx->assigned = false;
2343 ctx->hw_queue_base = 0;
2344 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2345
2346 mutex_unlock(&sc->mutex);
2347 }
2348
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2349 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2350 struct ieee80211_chanctx_conf *conf,
2351 u32 changed)
2352 {
2353 struct ath_softc *sc = hw->priv;
2354 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2355 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2356
2357 mutex_lock(&sc->mutex);
2358 ath_dbg(common, CHAN_CTX,
2359 "Change channel context: %d MHz\n",
2360 conf->def.chan->center_freq);
2361 ath_chanctx_set_channel(sc, ctx, &conf->def);
2362 mutex_unlock(&sc->mutex);
2363 }
2364
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2365 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2366 struct ieee80211_vif *vif,
2367 struct ieee80211_chanctx_conf *conf)
2368 {
2369 struct ath_softc *sc = hw->priv;
2370 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2371 struct ath_vif *avp = (void *)vif->drv_priv;
2372 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2373 int i;
2374
2375 mutex_lock(&sc->mutex);
2376
2377 ath_dbg(common, CHAN_CTX,
2378 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2379 vif->addr, vif->type, vif->p2p,
2380 conf->def.chan->center_freq);
2381
2382 avp->chanctx = ctx;
2383 ctx->nvifs_assigned++;
2384 list_add_tail(&avp->list, &ctx->vifs);
2385 ath9k_calculate_summary_state(sc, ctx);
2386 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2387 vif->hw_queue[i] = ctx->hw_queue_base + i;
2388
2389 mutex_unlock(&sc->mutex);
2390
2391 return 0;
2392 }
2393
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2394 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2395 struct ieee80211_vif *vif,
2396 struct ieee80211_chanctx_conf *conf)
2397 {
2398 struct ath_softc *sc = hw->priv;
2399 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2400 struct ath_vif *avp = (void *)vif->drv_priv;
2401 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2402 int ac;
2403
2404 mutex_lock(&sc->mutex);
2405
2406 ath_dbg(common, CHAN_CTX,
2407 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2408 vif->addr, vif->type, vif->p2p,
2409 conf->def.chan->center_freq);
2410
2411 avp->chanctx = NULL;
2412 ctx->nvifs_assigned--;
2413 list_del(&avp->list);
2414 ath9k_calculate_summary_state(sc, ctx);
2415 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2416 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2417
2418 mutex_unlock(&sc->mutex);
2419 }
2420
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2421 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2422 struct ieee80211_vif *vif)
2423 {
2424 struct ath_softc *sc = hw->priv;
2425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2426 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2427 bool changed = false;
2428
2429 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2430 return;
2431
2432 if (!avp->chanctx)
2433 return;
2434
2435 mutex_lock(&sc->mutex);
2436
2437 spin_lock_bh(&sc->chan_lock);
2438 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) {
2439 sc->next_chan = avp->chanctx;
2440 changed = true;
2441 }
2442 ath_dbg(common, CHAN_CTX,
2443 "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n",
2444 __func__, changed);
2445 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2446 spin_unlock_bh(&sc->chan_lock);
2447
2448 if (changed)
2449 ath_chanctx_set_next(sc, true);
2450
2451 mutex_unlock(&sc->mutex);
2452 }
2453
ath9k_fill_chanctx_ops(void)2454 void ath9k_fill_chanctx_ops(void)
2455 {
2456 if (!ath9k_is_chanctx_enabled())
2457 return;
2458
2459 ath9k_ops.hw_scan = ath9k_hw_scan;
2460 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2461 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2462 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2463 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2464 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2465 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2466 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2467 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2468 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2469 }
2470
2471 #endif
2472
2473 struct ieee80211_ops ath9k_ops = {
2474 .tx = ath9k_tx,
2475 .start = ath9k_start,
2476 .stop = ath9k_stop,
2477 .add_interface = ath9k_add_interface,
2478 .change_interface = ath9k_change_interface,
2479 .remove_interface = ath9k_remove_interface,
2480 .config = ath9k_config,
2481 .configure_filter = ath9k_configure_filter,
2482 .sta_add = ath9k_sta_add,
2483 .sta_remove = ath9k_sta_remove,
2484 .sta_notify = ath9k_sta_notify,
2485 .conf_tx = ath9k_conf_tx,
2486 .bss_info_changed = ath9k_bss_info_changed,
2487 .set_key = ath9k_set_key,
2488 .get_tsf = ath9k_get_tsf,
2489 .set_tsf = ath9k_set_tsf,
2490 .reset_tsf = ath9k_reset_tsf,
2491 .ampdu_action = ath9k_ampdu_action,
2492 .get_survey = ath9k_get_survey,
2493 .rfkill_poll = ath9k_rfkill_poll_state,
2494 .set_coverage_class = ath9k_set_coverage_class,
2495 .flush = ath9k_flush,
2496 .tx_frames_pending = ath9k_tx_frames_pending,
2497 .tx_last_beacon = ath9k_tx_last_beacon,
2498 .release_buffered_frames = ath9k_release_buffered_frames,
2499 .get_stats = ath9k_get_stats,
2500 .set_antenna = ath9k_set_antenna,
2501 .get_antenna = ath9k_get_antenna,
2502
2503 #ifdef CONFIG_ATH9K_WOW
2504 .suspend = ath9k_suspend,
2505 .resume = ath9k_resume,
2506 .set_wakeup = ath9k_set_wakeup,
2507 #endif
2508
2509 #ifdef CONFIG_ATH9K_DEBUGFS
2510 .get_et_sset_count = ath9k_get_et_sset_count,
2511 .get_et_stats = ath9k_get_et_stats,
2512 .get_et_strings = ath9k_get_et_strings,
2513 #endif
2514
2515 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2516 .sta_add_debugfs = ath9k_sta_add_debugfs,
2517 #endif
2518 .sw_scan_start = ath9k_sw_scan_start,
2519 .sw_scan_complete = ath9k_sw_scan_complete,
2520 };
2521