• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20 
21 #define SKB_CB_ATHBUF(__skb)	(*((struct ath_rxbuf **)__skb->cb))
22 
ath9k_check_auto_sleep(struct ath_softc * sc)23 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
24 {
25 	return sc->ps_enabled &&
26 	       (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
27 }
28 
29 /*
30  * Setup and link descriptors.
31  *
32  * 11N: we can no longer afford to self link the last descriptor.
33  * MAC acknowledges BA status as long as it copies frames to host
34  * buffer (or rx fifo). This can incorrectly acknowledge packets
35  * to a sender if last desc is self-linked.
36  */
ath_rx_buf_link(struct ath_softc * sc,struct ath_rxbuf * bf,bool flush)37 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf,
38 			    bool flush)
39 {
40 	struct ath_hw *ah = sc->sc_ah;
41 	struct ath_common *common = ath9k_hw_common(ah);
42 	struct ath_desc *ds;
43 	struct sk_buff *skb;
44 
45 	ds = bf->bf_desc;
46 	ds->ds_link = 0; /* link to null */
47 	ds->ds_data = bf->bf_buf_addr;
48 
49 	/* virtual addr of the beginning of the buffer. */
50 	skb = bf->bf_mpdu;
51 	BUG_ON(skb == NULL);
52 	ds->ds_vdata = skb->data;
53 
54 	/*
55 	 * setup rx descriptors. The rx_bufsize here tells the hardware
56 	 * how much data it can DMA to us and that we are prepared
57 	 * to process
58 	 */
59 	ath9k_hw_setuprxdesc(ah, ds,
60 			     common->rx_bufsize,
61 			     0);
62 
63 	if (sc->rx.rxlink)
64 		*sc->rx.rxlink = bf->bf_daddr;
65 	else if (!flush)
66 		ath9k_hw_putrxbuf(ah, bf->bf_daddr);
67 
68 	sc->rx.rxlink = &ds->ds_link;
69 }
70 
ath_rx_buf_relink(struct ath_softc * sc,struct ath_rxbuf * bf,bool flush)71 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf,
72 			      bool flush)
73 {
74 	if (sc->rx.buf_hold)
75 		ath_rx_buf_link(sc, sc->rx.buf_hold, flush);
76 
77 	sc->rx.buf_hold = bf;
78 }
79 
ath_setdefantenna(struct ath_softc * sc,u32 antenna)80 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
81 {
82 	/* XXX block beacon interrupts */
83 	ath9k_hw_setantenna(sc->sc_ah, antenna);
84 	sc->rx.defant = antenna;
85 	sc->rx.rxotherant = 0;
86 }
87 
ath_opmode_init(struct ath_softc * sc)88 static void ath_opmode_init(struct ath_softc *sc)
89 {
90 	struct ath_hw *ah = sc->sc_ah;
91 	struct ath_common *common = ath9k_hw_common(ah);
92 
93 	u32 rfilt, mfilt[2];
94 
95 	/* configure rx filter */
96 	rfilt = ath_calcrxfilter(sc);
97 	ath9k_hw_setrxfilter(ah, rfilt);
98 
99 	/* configure bssid mask */
100 	ath_hw_setbssidmask(common);
101 
102 	/* configure operational mode */
103 	ath9k_hw_setopmode(ah);
104 
105 	/* calculate and install multicast filter */
106 	mfilt[0] = mfilt[1] = ~0;
107 	ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
108 }
109 
ath_rx_edma_buf_link(struct ath_softc * sc,enum ath9k_rx_qtype qtype)110 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
111 				 enum ath9k_rx_qtype qtype)
112 {
113 	struct ath_hw *ah = sc->sc_ah;
114 	struct ath_rx_edma *rx_edma;
115 	struct sk_buff *skb;
116 	struct ath_rxbuf *bf;
117 
118 	rx_edma = &sc->rx.rx_edma[qtype];
119 	if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
120 		return false;
121 
122 	bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
123 	list_del_init(&bf->list);
124 
125 	skb = bf->bf_mpdu;
126 
127 	memset(skb->data, 0, ah->caps.rx_status_len);
128 	dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
129 				ah->caps.rx_status_len, DMA_TO_DEVICE);
130 
131 	SKB_CB_ATHBUF(skb) = bf;
132 	ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
133 	__skb_queue_tail(&rx_edma->rx_fifo, skb);
134 
135 	return true;
136 }
137 
ath_rx_addbuffer_edma(struct ath_softc * sc,enum ath9k_rx_qtype qtype)138 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
139 				  enum ath9k_rx_qtype qtype)
140 {
141 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
142 	struct ath_rxbuf *bf, *tbf;
143 
144 	if (list_empty(&sc->rx.rxbuf)) {
145 		ath_dbg(common, QUEUE, "No free rx buf available\n");
146 		return;
147 	}
148 
149 	list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
150 		if (!ath_rx_edma_buf_link(sc, qtype))
151 			break;
152 
153 }
154 
ath_rx_remove_buffer(struct ath_softc * sc,enum ath9k_rx_qtype qtype)155 static void ath_rx_remove_buffer(struct ath_softc *sc,
156 				 enum ath9k_rx_qtype qtype)
157 {
158 	struct ath_rxbuf *bf;
159 	struct ath_rx_edma *rx_edma;
160 	struct sk_buff *skb;
161 
162 	rx_edma = &sc->rx.rx_edma[qtype];
163 
164 	while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
165 		bf = SKB_CB_ATHBUF(skb);
166 		BUG_ON(!bf);
167 		list_add_tail(&bf->list, &sc->rx.rxbuf);
168 	}
169 }
170 
ath_rx_edma_cleanup(struct ath_softc * sc)171 static void ath_rx_edma_cleanup(struct ath_softc *sc)
172 {
173 	struct ath_hw *ah = sc->sc_ah;
174 	struct ath_common *common = ath9k_hw_common(ah);
175 	struct ath_rxbuf *bf;
176 
177 	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
178 	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
179 
180 	list_for_each_entry(bf, &sc->rx.rxbuf, list) {
181 		if (bf->bf_mpdu) {
182 			dma_unmap_single(sc->dev, bf->bf_buf_addr,
183 					common->rx_bufsize,
184 					DMA_BIDIRECTIONAL);
185 			dev_kfree_skb_any(bf->bf_mpdu);
186 			bf->bf_buf_addr = 0;
187 			bf->bf_mpdu = NULL;
188 		}
189 	}
190 }
191 
ath_rx_edma_init_queue(struct ath_rx_edma * rx_edma,int size)192 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
193 {
194 	__skb_queue_head_init(&rx_edma->rx_fifo);
195 	rx_edma->rx_fifo_hwsize = size;
196 }
197 
ath_rx_edma_init(struct ath_softc * sc,int nbufs)198 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
199 {
200 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
201 	struct ath_hw *ah = sc->sc_ah;
202 	struct sk_buff *skb;
203 	struct ath_rxbuf *bf;
204 	int error = 0, i;
205 	u32 size;
206 
207 	ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
208 				    ah->caps.rx_status_len);
209 
210 	ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
211 			       ah->caps.rx_lp_qdepth);
212 	ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
213 			       ah->caps.rx_hp_qdepth);
214 
215 	size = sizeof(struct ath_rxbuf) * nbufs;
216 	bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
217 	if (!bf)
218 		return -ENOMEM;
219 
220 	INIT_LIST_HEAD(&sc->rx.rxbuf);
221 
222 	for (i = 0; i < nbufs; i++, bf++) {
223 		skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
224 		if (!skb) {
225 			error = -ENOMEM;
226 			goto rx_init_fail;
227 		}
228 
229 		memset(skb->data, 0, common->rx_bufsize);
230 		bf->bf_mpdu = skb;
231 
232 		bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
233 						 common->rx_bufsize,
234 						 DMA_BIDIRECTIONAL);
235 		if (unlikely(dma_mapping_error(sc->dev,
236 						bf->bf_buf_addr))) {
237 				dev_kfree_skb_any(skb);
238 				bf->bf_mpdu = NULL;
239 				bf->bf_buf_addr = 0;
240 				ath_err(common,
241 					"dma_mapping_error() on RX init\n");
242 				error = -ENOMEM;
243 				goto rx_init_fail;
244 		}
245 
246 		list_add_tail(&bf->list, &sc->rx.rxbuf);
247 	}
248 
249 	return 0;
250 
251 rx_init_fail:
252 	ath_rx_edma_cleanup(sc);
253 	return error;
254 }
255 
ath_edma_start_recv(struct ath_softc * sc)256 static void ath_edma_start_recv(struct ath_softc *sc)
257 {
258 	ath9k_hw_rxena(sc->sc_ah);
259 	ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
260 	ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
261 	ath_opmode_init(sc);
262 	ath9k_hw_startpcureceive(sc->sc_ah, sc->cur_chan->offchannel);
263 }
264 
ath_edma_stop_recv(struct ath_softc * sc)265 static void ath_edma_stop_recv(struct ath_softc *sc)
266 {
267 	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
268 	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
269 }
270 
ath_rx_init(struct ath_softc * sc,int nbufs)271 int ath_rx_init(struct ath_softc *sc, int nbufs)
272 {
273 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
274 	struct sk_buff *skb;
275 	struct ath_rxbuf *bf;
276 	int error = 0;
277 
278 	spin_lock_init(&sc->sc_pcu_lock);
279 
280 	common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
281 			     sc->sc_ah->caps.rx_status_len;
282 
283 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
284 		return ath_rx_edma_init(sc, nbufs);
285 
286 	ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
287 		common->cachelsz, common->rx_bufsize);
288 
289 	/* Initialize rx descriptors */
290 
291 	error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
292 				  "rx", nbufs, 1, 0);
293 	if (error != 0) {
294 		ath_err(common,
295 			"failed to allocate rx descriptors: %d\n",
296 			error);
297 		goto err;
298 	}
299 
300 	list_for_each_entry(bf, &sc->rx.rxbuf, list) {
301 		skb = ath_rxbuf_alloc(common, common->rx_bufsize,
302 				      GFP_KERNEL);
303 		if (skb == NULL) {
304 			error = -ENOMEM;
305 			goto err;
306 		}
307 
308 		bf->bf_mpdu = skb;
309 		bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
310 						 common->rx_bufsize,
311 						 DMA_FROM_DEVICE);
312 		if (unlikely(dma_mapping_error(sc->dev,
313 					       bf->bf_buf_addr))) {
314 			dev_kfree_skb_any(skb);
315 			bf->bf_mpdu = NULL;
316 			bf->bf_buf_addr = 0;
317 			ath_err(common,
318 				"dma_mapping_error() on RX init\n");
319 			error = -ENOMEM;
320 			goto err;
321 		}
322 	}
323 	sc->rx.rxlink = NULL;
324 err:
325 	if (error)
326 		ath_rx_cleanup(sc);
327 
328 	return error;
329 }
330 
ath_rx_cleanup(struct ath_softc * sc)331 void ath_rx_cleanup(struct ath_softc *sc)
332 {
333 	struct ath_hw *ah = sc->sc_ah;
334 	struct ath_common *common = ath9k_hw_common(ah);
335 	struct sk_buff *skb;
336 	struct ath_rxbuf *bf;
337 
338 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
339 		ath_rx_edma_cleanup(sc);
340 		return;
341 	}
342 
343 	list_for_each_entry(bf, &sc->rx.rxbuf, list) {
344 		skb = bf->bf_mpdu;
345 		if (skb) {
346 			dma_unmap_single(sc->dev, bf->bf_buf_addr,
347 					 common->rx_bufsize,
348 					 DMA_FROM_DEVICE);
349 			dev_kfree_skb(skb);
350 			bf->bf_buf_addr = 0;
351 			bf->bf_mpdu = NULL;
352 		}
353 	}
354 }
355 
356 /*
357  * Calculate the receive filter according to the
358  * operating mode and state:
359  *
360  * o always accept unicast, broadcast, and multicast traffic
361  * o maintain current state of phy error reception (the hal
362  *   may enable phy error frames for noise immunity work)
363  * o probe request frames are accepted only when operating in
364  *   hostap, adhoc, or monitor modes
365  * o enable promiscuous mode according to the interface state
366  * o accept beacons:
367  *   - when operating in adhoc mode so the 802.11 layer creates
368  *     node table entries for peers,
369  *   - when operating in station mode for collecting rssi data when
370  *     the station is otherwise quiet, or
371  *   - when operating as a repeater so we see repeater-sta beacons
372  *   - when scanning
373  */
374 
ath_calcrxfilter(struct ath_softc * sc)375 u32 ath_calcrxfilter(struct ath_softc *sc)
376 {
377 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
378 	u32 rfilt;
379 
380 	if (config_enabled(CONFIG_ATH9K_TX99))
381 		return 0;
382 
383 	rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
384 		| ATH9K_RX_FILTER_MCAST;
385 
386 	/* if operating on a DFS channel, enable radar pulse detection */
387 	if (sc->hw->conf.radar_enabled)
388 		rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
389 
390 	spin_lock_bh(&sc->chan_lock);
391 
392 	if (sc->cur_chan->rxfilter & FIF_PROBE_REQ)
393 		rfilt |= ATH9K_RX_FILTER_PROBEREQ;
394 
395 	/*
396 	 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
397 	 * mode interface or when in monitor mode. AP mode does not need this
398 	 * since it receives all in-BSS frames anyway.
399 	 */
400 	if (sc->sc_ah->is_monitoring)
401 		rfilt |= ATH9K_RX_FILTER_PROM;
402 
403 	if ((sc->cur_chan->rxfilter & FIF_CONTROL) ||
404 	    sc->sc_ah->dynack.enabled)
405 		rfilt |= ATH9K_RX_FILTER_CONTROL;
406 
407 	if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
408 	    (sc->cur_chan->nvifs <= 1) &&
409 	    !(sc->cur_chan->rxfilter & FIF_BCN_PRBRESP_PROMISC))
410 		rfilt |= ATH9K_RX_FILTER_MYBEACON;
411 	else
412 		rfilt |= ATH9K_RX_FILTER_BEACON;
413 
414 	if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
415 	    (sc->cur_chan->rxfilter & FIF_PSPOLL))
416 		rfilt |= ATH9K_RX_FILTER_PSPOLL;
417 
418 	if (sc->cur_chandef.width != NL80211_CHAN_WIDTH_20_NOHT)
419 		rfilt |= ATH9K_RX_FILTER_COMP_BAR;
420 
421 	if (sc->cur_chan->nvifs > 1 || (sc->cur_chan->rxfilter & FIF_OTHER_BSS)) {
422 		/* This is needed for older chips */
423 		if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
424 			rfilt |= ATH9K_RX_FILTER_PROM;
425 		rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
426 	}
427 
428 	if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah))
429 		rfilt |= ATH9K_RX_FILTER_4ADDRESS;
430 
431 	if (ath9k_is_chanctx_enabled() &&
432 	    test_bit(ATH_OP_SCANNING, &common->op_flags))
433 		rfilt |= ATH9K_RX_FILTER_BEACON;
434 
435 	spin_unlock_bh(&sc->chan_lock);
436 
437 	return rfilt;
438 
439 }
440 
ath_startrecv(struct ath_softc * sc)441 void ath_startrecv(struct ath_softc *sc)
442 {
443 	struct ath_hw *ah = sc->sc_ah;
444 	struct ath_rxbuf *bf, *tbf;
445 
446 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
447 		ath_edma_start_recv(sc);
448 		return;
449 	}
450 
451 	if (list_empty(&sc->rx.rxbuf))
452 		goto start_recv;
453 
454 	sc->rx.buf_hold = NULL;
455 	sc->rx.rxlink = NULL;
456 	list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
457 		ath_rx_buf_link(sc, bf, false);
458 	}
459 
460 	/* We could have deleted elements so the list may be empty now */
461 	if (list_empty(&sc->rx.rxbuf))
462 		goto start_recv;
463 
464 	bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
465 	ath9k_hw_putrxbuf(ah, bf->bf_daddr);
466 	ath9k_hw_rxena(ah);
467 
468 start_recv:
469 	ath_opmode_init(sc);
470 	ath9k_hw_startpcureceive(ah, sc->cur_chan->offchannel);
471 }
472 
ath_flushrecv(struct ath_softc * sc)473 static void ath_flushrecv(struct ath_softc *sc)
474 {
475 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
476 		ath_rx_tasklet(sc, 1, true);
477 	ath_rx_tasklet(sc, 1, false);
478 }
479 
ath_stoprecv(struct ath_softc * sc)480 bool ath_stoprecv(struct ath_softc *sc)
481 {
482 	struct ath_hw *ah = sc->sc_ah;
483 	bool stopped, reset = false;
484 
485 	ath9k_hw_abortpcurecv(ah);
486 	ath9k_hw_setrxfilter(ah, 0);
487 	stopped = ath9k_hw_stopdmarecv(ah, &reset);
488 
489 	ath_flushrecv(sc);
490 
491 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
492 		ath_edma_stop_recv(sc);
493 	else
494 		sc->rx.rxlink = NULL;
495 
496 	if (!(ah->ah_flags & AH_UNPLUGGED) &&
497 	    unlikely(!stopped)) {
498 		ath_err(ath9k_hw_common(sc->sc_ah),
499 			"Could not stop RX, we could be "
500 			"confusing the DMA engine when we start RX up\n");
501 		ATH_DBG_WARN_ON_ONCE(!stopped);
502 	}
503 	return stopped && !reset;
504 }
505 
ath_beacon_dtim_pending_cab(struct sk_buff * skb)506 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
507 {
508 	/* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
509 	struct ieee80211_mgmt *mgmt;
510 	u8 *pos, *end, id, elen;
511 	struct ieee80211_tim_ie *tim;
512 
513 	mgmt = (struct ieee80211_mgmt *)skb->data;
514 	pos = mgmt->u.beacon.variable;
515 	end = skb->data + skb->len;
516 
517 	while (pos + 2 < end) {
518 		id = *pos++;
519 		elen = *pos++;
520 		if (pos + elen > end)
521 			break;
522 
523 		if (id == WLAN_EID_TIM) {
524 			if (elen < sizeof(*tim))
525 				break;
526 			tim = (struct ieee80211_tim_ie *) pos;
527 			if (tim->dtim_count != 0)
528 				break;
529 			return tim->bitmap_ctrl & 0x01;
530 		}
531 
532 		pos += elen;
533 	}
534 
535 	return false;
536 }
537 
ath_rx_ps_beacon(struct ath_softc * sc,struct sk_buff * skb)538 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
539 {
540 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
541 	bool skip_beacon = false;
542 
543 	if (skb->len < 24 + 8 + 2 + 2)
544 		return;
545 
546 	sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
547 
548 	if (sc->ps_flags & PS_BEACON_SYNC) {
549 		sc->ps_flags &= ~PS_BEACON_SYNC;
550 		ath_dbg(common, PS,
551 			"Reconfigure beacon timers based on synchronized timestamp\n");
552 
553 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
554 		if (ath9k_is_chanctx_enabled()) {
555 			if (sc->cur_chan == &sc->offchannel.chan)
556 				skip_beacon = true;
557 		}
558 #endif
559 
560 		if (!skip_beacon &&
561 		    !(WARN_ON_ONCE(sc->cur_chan->beacon.beacon_interval == 0)))
562 			ath9k_set_beacon(sc);
563 
564 		ath9k_p2p_beacon_sync(sc);
565 	}
566 
567 	if (ath_beacon_dtim_pending_cab(skb)) {
568 		/*
569 		 * Remain awake waiting for buffered broadcast/multicast
570 		 * frames. If the last broadcast/multicast frame is not
571 		 * received properly, the next beacon frame will work as
572 		 * a backup trigger for returning into NETWORK SLEEP state,
573 		 * so we are waiting for it as well.
574 		 */
575 		ath_dbg(common, PS,
576 			"Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
577 		sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
578 		return;
579 	}
580 
581 	if (sc->ps_flags & PS_WAIT_FOR_CAB) {
582 		/*
583 		 * This can happen if a broadcast frame is dropped or the AP
584 		 * fails to send a frame indicating that all CAB frames have
585 		 * been delivered.
586 		 */
587 		sc->ps_flags &= ~PS_WAIT_FOR_CAB;
588 		ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
589 	}
590 }
591 
ath_rx_ps(struct ath_softc * sc,struct sk_buff * skb,bool mybeacon)592 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
593 {
594 	struct ieee80211_hdr *hdr;
595 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
596 
597 	hdr = (struct ieee80211_hdr *)skb->data;
598 
599 	/* Process Beacon and CAB receive in PS state */
600 	if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
601 	    && mybeacon) {
602 		ath_rx_ps_beacon(sc, skb);
603 	} else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
604 		   (ieee80211_is_data(hdr->frame_control) ||
605 		    ieee80211_is_action(hdr->frame_control)) &&
606 		   is_multicast_ether_addr(hdr->addr1) &&
607 		   !ieee80211_has_moredata(hdr->frame_control)) {
608 		/*
609 		 * No more broadcast/multicast frames to be received at this
610 		 * point.
611 		 */
612 		sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
613 		ath_dbg(common, PS,
614 			"All PS CAB frames received, back to sleep\n");
615 	} else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
616 		   !is_multicast_ether_addr(hdr->addr1) &&
617 		   !ieee80211_has_morefrags(hdr->frame_control)) {
618 		sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
619 		ath_dbg(common, PS,
620 			"Going back to sleep after having received PS-Poll data (0x%lx)\n",
621 			sc->ps_flags & (PS_WAIT_FOR_BEACON |
622 					PS_WAIT_FOR_CAB |
623 					PS_WAIT_FOR_PSPOLL_DATA |
624 					PS_WAIT_FOR_TX_ACK));
625 	}
626 }
627 
ath_edma_get_buffers(struct ath_softc * sc,enum ath9k_rx_qtype qtype,struct ath_rx_status * rs,struct ath_rxbuf ** dest)628 static bool ath_edma_get_buffers(struct ath_softc *sc,
629 				 enum ath9k_rx_qtype qtype,
630 				 struct ath_rx_status *rs,
631 				 struct ath_rxbuf **dest)
632 {
633 	struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
634 	struct ath_hw *ah = sc->sc_ah;
635 	struct ath_common *common = ath9k_hw_common(ah);
636 	struct sk_buff *skb;
637 	struct ath_rxbuf *bf;
638 	int ret;
639 
640 	skb = skb_peek(&rx_edma->rx_fifo);
641 	if (!skb)
642 		return false;
643 
644 	bf = SKB_CB_ATHBUF(skb);
645 	BUG_ON(!bf);
646 
647 	dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
648 				common->rx_bufsize, DMA_FROM_DEVICE);
649 
650 	ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
651 	if (ret == -EINPROGRESS) {
652 		/*let device gain the buffer again*/
653 		dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
654 				common->rx_bufsize, DMA_FROM_DEVICE);
655 		return false;
656 	}
657 
658 	__skb_unlink(skb, &rx_edma->rx_fifo);
659 	if (ret == -EINVAL) {
660 		/* corrupt descriptor, skip this one and the following one */
661 		list_add_tail(&bf->list, &sc->rx.rxbuf);
662 		ath_rx_edma_buf_link(sc, qtype);
663 
664 		skb = skb_peek(&rx_edma->rx_fifo);
665 		if (skb) {
666 			bf = SKB_CB_ATHBUF(skb);
667 			BUG_ON(!bf);
668 
669 			__skb_unlink(skb, &rx_edma->rx_fifo);
670 			list_add_tail(&bf->list, &sc->rx.rxbuf);
671 			ath_rx_edma_buf_link(sc, qtype);
672 		}
673 
674 		bf = NULL;
675 	}
676 
677 	*dest = bf;
678 	return true;
679 }
680 
ath_edma_get_next_rx_buf(struct ath_softc * sc,struct ath_rx_status * rs,enum ath9k_rx_qtype qtype)681 static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
682 						struct ath_rx_status *rs,
683 						enum ath9k_rx_qtype qtype)
684 {
685 	struct ath_rxbuf *bf = NULL;
686 
687 	while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
688 		if (!bf)
689 			continue;
690 
691 		return bf;
692 	}
693 	return NULL;
694 }
695 
ath_get_next_rx_buf(struct ath_softc * sc,struct ath_rx_status * rs)696 static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc,
697 					   struct ath_rx_status *rs)
698 {
699 	struct ath_hw *ah = sc->sc_ah;
700 	struct ath_common *common = ath9k_hw_common(ah);
701 	struct ath_desc *ds;
702 	struct ath_rxbuf *bf;
703 	int ret;
704 
705 	if (list_empty(&sc->rx.rxbuf)) {
706 		sc->rx.rxlink = NULL;
707 		return NULL;
708 	}
709 
710 	bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
711 	if (bf == sc->rx.buf_hold)
712 		return NULL;
713 
714 	ds = bf->bf_desc;
715 
716 	/*
717 	 * Must provide the virtual address of the current
718 	 * descriptor, the physical address, and the virtual
719 	 * address of the next descriptor in the h/w chain.
720 	 * This allows the HAL to look ahead to see if the
721 	 * hardware is done with a descriptor by checking the
722 	 * done bit in the following descriptor and the address
723 	 * of the current descriptor the DMA engine is working
724 	 * on.  All this is necessary because of our use of
725 	 * a self-linked list to avoid rx overruns.
726 	 */
727 	ret = ath9k_hw_rxprocdesc(ah, ds, rs);
728 	if (ret == -EINPROGRESS) {
729 		struct ath_rx_status trs;
730 		struct ath_rxbuf *tbf;
731 		struct ath_desc *tds;
732 
733 		memset(&trs, 0, sizeof(trs));
734 		if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
735 			sc->rx.rxlink = NULL;
736 			return NULL;
737 		}
738 
739 		tbf = list_entry(bf->list.next, struct ath_rxbuf, list);
740 
741 		/*
742 		 * On some hardware the descriptor status words could
743 		 * get corrupted, including the done bit. Because of
744 		 * this, check if the next descriptor's done bit is
745 		 * set or not.
746 		 *
747 		 * If the next descriptor's done bit is set, the current
748 		 * descriptor has been corrupted. Force s/w to discard
749 		 * this descriptor and continue...
750 		 */
751 
752 		tds = tbf->bf_desc;
753 		ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
754 		if (ret == -EINPROGRESS)
755 			return NULL;
756 
757 		/*
758 		 * Re-check previous descriptor, in case it has been filled
759 		 * in the mean time.
760 		 */
761 		ret = ath9k_hw_rxprocdesc(ah, ds, rs);
762 		if (ret == -EINPROGRESS) {
763 			/*
764 			 * mark descriptor as zero-length and set the 'more'
765 			 * flag to ensure that both buffers get discarded
766 			 */
767 			rs->rs_datalen = 0;
768 			rs->rs_more = true;
769 		}
770 	}
771 
772 	list_del(&bf->list);
773 	if (!bf->bf_mpdu)
774 		return bf;
775 
776 	/*
777 	 * Synchronize the DMA transfer with CPU before
778 	 * 1. accessing the frame
779 	 * 2. requeueing the same buffer to h/w
780 	 */
781 	dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
782 			common->rx_bufsize,
783 			DMA_FROM_DEVICE);
784 
785 	return bf;
786 }
787 
ath9k_process_tsf(struct ath_rx_status * rs,struct ieee80211_rx_status * rxs,u64 tsf)788 static void ath9k_process_tsf(struct ath_rx_status *rs,
789 			      struct ieee80211_rx_status *rxs,
790 			      u64 tsf)
791 {
792 	u32 tsf_lower = tsf & 0xffffffff;
793 
794 	rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp;
795 	if (rs->rs_tstamp > tsf_lower &&
796 	    unlikely(rs->rs_tstamp - tsf_lower > 0x10000000))
797 		rxs->mactime -= 0x100000000ULL;
798 
799 	if (rs->rs_tstamp < tsf_lower &&
800 	    unlikely(tsf_lower - rs->rs_tstamp > 0x10000000))
801 		rxs->mactime += 0x100000000ULL;
802 }
803 
804 /*
805  * For Decrypt or Demic errors, we only mark packet status here and always push
806  * up the frame up to let mac80211 handle the actual error case, be it no
807  * decryption key or real decryption error. This let us keep statistics there.
808  */
ath9k_rx_skb_preprocess(struct ath_softc * sc,struct sk_buff * skb,struct ath_rx_status * rx_stats,struct ieee80211_rx_status * rx_status,bool * decrypt_error,u64 tsf)809 static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
810 				   struct sk_buff *skb,
811 				   struct ath_rx_status *rx_stats,
812 				   struct ieee80211_rx_status *rx_status,
813 				   bool *decrypt_error, u64 tsf)
814 {
815 	struct ieee80211_hw *hw = sc->hw;
816 	struct ath_hw *ah = sc->sc_ah;
817 	struct ath_common *common = ath9k_hw_common(ah);
818 	struct ieee80211_hdr *hdr;
819 	bool discard_current = sc->rx.discard_next;
820 
821 	/*
822 	 * Discard corrupt descriptors which are marked in
823 	 * ath_get_next_rx_buf().
824 	 */
825 	if (discard_current)
826 		goto corrupt;
827 
828 	sc->rx.discard_next = false;
829 
830 	/*
831 	 * Discard zero-length packets.
832 	 */
833 	if (!rx_stats->rs_datalen) {
834 		RX_STAT_INC(rx_len_err);
835 		goto corrupt;
836 	}
837 
838 	/*
839 	 * rs_status follows rs_datalen so if rs_datalen is too large
840 	 * we can take a hint that hardware corrupted it, so ignore
841 	 * those frames.
842 	 */
843 	if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) {
844 		RX_STAT_INC(rx_len_err);
845 		goto corrupt;
846 	}
847 
848 	/* Only use status info from the last fragment */
849 	if (rx_stats->rs_more)
850 		return 0;
851 
852 	/*
853 	 * Return immediately if the RX descriptor has been marked
854 	 * as corrupt based on the various error bits.
855 	 *
856 	 * This is different from the other corrupt descriptor
857 	 * condition handled above.
858 	 */
859 	if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC)
860 		goto corrupt;
861 
862 	hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len);
863 
864 	ath9k_process_tsf(rx_stats, rx_status, tsf);
865 	ath_debug_stat_rx(sc, rx_stats);
866 
867 	/*
868 	 * Process PHY errors and return so that the packet
869 	 * can be dropped.
870 	 */
871 	if (rx_stats->rs_status & ATH9K_RXERR_PHY) {
872 		ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime);
873 		if (ath_process_fft(sc, hdr, rx_stats, rx_status->mactime))
874 			RX_STAT_INC(rx_spectral);
875 
876 		return -EINVAL;
877 	}
878 
879 	/*
880 	 * everything but the rate is checked here, the rate check is done
881 	 * separately to avoid doing two lookups for a rate for each frame.
882 	 */
883 	spin_lock_bh(&sc->chan_lock);
884 	if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error,
885 				 sc->cur_chan->rxfilter)) {
886 		spin_unlock_bh(&sc->chan_lock);
887 		return -EINVAL;
888 	}
889 	spin_unlock_bh(&sc->chan_lock);
890 
891 	if (ath_is_mybeacon(common, hdr)) {
892 		RX_STAT_INC(rx_beacons);
893 		rx_stats->is_mybeacon = true;
894 	}
895 
896 	/*
897 	 * This shouldn't happen, but have a safety check anyway.
898 	 */
899 	if (WARN_ON(!ah->curchan))
900 		return -EINVAL;
901 
902 	if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) {
903 		/*
904 		 * No valid hardware bitrate found -- we should not get here
905 		 * because hardware has already validated this frame as OK.
906 		 */
907 		ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
908 			rx_stats->rs_rate);
909 		RX_STAT_INC(rx_rate_err);
910 		return -EINVAL;
911 	}
912 
913 	if (ath9k_is_chanctx_enabled()) {
914 		if (rx_stats->is_mybeacon)
915 			ath_chanctx_beacon_recv_ev(sc,
916 					   ATH_CHANCTX_EVENT_BEACON_RECEIVED);
917 	}
918 
919 	ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status);
920 
921 	rx_status->band = ah->curchan->chan->band;
922 	rx_status->freq = ah->curchan->chan->center_freq;
923 	rx_status->antenna = rx_stats->rs_antenna;
924 	rx_status->flag |= RX_FLAG_MACTIME_END;
925 
926 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
927 	if (ieee80211_is_data_present(hdr->frame_control) &&
928 	    !ieee80211_is_qos_nullfunc(hdr->frame_control))
929 		sc->rx.num_pkts++;
930 #endif
931 
932 	return 0;
933 
934 corrupt:
935 	sc->rx.discard_next = rx_stats->rs_more;
936 	return -EINVAL;
937 }
938 
939 /*
940  * Run the LNA combining algorithm only in these cases:
941  *
942  * Standalone WLAN cards with both LNA/Antenna diversity
943  * enabled in the EEPROM.
944  *
945  * WLAN+BT cards which are in the supported card list
946  * in ath_pci_id_table and the user has loaded the
947  * driver with "bt_ant_diversity" set to true.
948  */
ath9k_antenna_check(struct ath_softc * sc,struct ath_rx_status * rs)949 static void ath9k_antenna_check(struct ath_softc *sc,
950 				struct ath_rx_status *rs)
951 {
952 	struct ath_hw *ah = sc->sc_ah;
953 	struct ath9k_hw_capabilities *pCap = &ah->caps;
954 	struct ath_common *common = ath9k_hw_common(ah);
955 
956 	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
957 		return;
958 
959 	/*
960 	 * Change the default rx antenna if rx diversity
961 	 * chooses the other antenna 3 times in a row.
962 	 */
963 	if (sc->rx.defant != rs->rs_antenna) {
964 		if (++sc->rx.rxotherant >= 3)
965 			ath_setdefantenna(sc, rs->rs_antenna);
966 	} else {
967 		sc->rx.rxotherant = 0;
968 	}
969 
970 	if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) {
971 		if (common->bt_ant_diversity)
972 			ath_ant_comb_scan(sc, rs);
973 	} else {
974 		ath_ant_comb_scan(sc, rs);
975 	}
976 }
977 
ath9k_apply_ampdu_details(struct ath_softc * sc,struct ath_rx_status * rs,struct ieee80211_rx_status * rxs)978 static void ath9k_apply_ampdu_details(struct ath_softc *sc,
979 	struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
980 {
981 	if (rs->rs_isaggr) {
982 		rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
983 
984 		rxs->ampdu_reference = sc->rx.ampdu_ref;
985 
986 		if (!rs->rs_moreaggr) {
987 			rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
988 			sc->rx.ampdu_ref++;
989 		}
990 
991 		if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
992 			rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
993 	}
994 }
995 
ath_rx_tasklet(struct ath_softc * sc,int flush,bool hp)996 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
997 {
998 	struct ath_rxbuf *bf;
999 	struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1000 	struct ieee80211_rx_status *rxs;
1001 	struct ath_hw *ah = sc->sc_ah;
1002 	struct ath_common *common = ath9k_hw_common(ah);
1003 	struct ieee80211_hw *hw = sc->hw;
1004 	int retval;
1005 	struct ath_rx_status rs;
1006 	enum ath9k_rx_qtype qtype;
1007 	bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1008 	int dma_type;
1009 	u64 tsf = 0;
1010 	unsigned long flags;
1011 	dma_addr_t new_buf_addr;
1012 	unsigned int budget = 512;
1013 	struct ieee80211_hdr *hdr;
1014 
1015 	if (edma)
1016 		dma_type = DMA_BIDIRECTIONAL;
1017 	else
1018 		dma_type = DMA_FROM_DEVICE;
1019 
1020 	qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1021 
1022 	tsf = ath9k_hw_gettsf64(ah);
1023 
1024 	do {
1025 		bool decrypt_error = false;
1026 
1027 		memset(&rs, 0, sizeof(rs));
1028 		if (edma)
1029 			bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1030 		else
1031 			bf = ath_get_next_rx_buf(sc, &rs);
1032 
1033 		if (!bf)
1034 			break;
1035 
1036 		skb = bf->bf_mpdu;
1037 		if (!skb)
1038 			continue;
1039 
1040 		/*
1041 		 * Take frame header from the first fragment and RX status from
1042 		 * the last one.
1043 		 */
1044 		if (sc->rx.frag)
1045 			hdr_skb = sc->rx.frag;
1046 		else
1047 			hdr_skb = skb;
1048 
1049 		rxs = IEEE80211_SKB_RXCB(hdr_skb);
1050 		memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1051 
1052 		retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs,
1053 						 &decrypt_error, tsf);
1054 		if (retval)
1055 			goto requeue_drop_frag;
1056 
1057 		/* Ensure we always have an skb to requeue once we are done
1058 		 * processing the current buffer's skb */
1059 		requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1060 
1061 		/* If there is no memory we ignore the current RX'd frame,
1062 		 * tell hardware it can give us a new frame using the old
1063 		 * skb and put it at the tail of the sc->rx.rxbuf list for
1064 		 * processing. */
1065 		if (!requeue_skb) {
1066 			RX_STAT_INC(rx_oom_err);
1067 			goto requeue_drop_frag;
1068 		}
1069 
1070 		/* We will now give hardware our shiny new allocated skb */
1071 		new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1072 					      common->rx_bufsize, dma_type);
1073 		if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
1074 			dev_kfree_skb_any(requeue_skb);
1075 			goto requeue_drop_frag;
1076 		}
1077 
1078 		/* Unmap the frame */
1079 		dma_unmap_single(sc->dev, bf->bf_buf_addr,
1080 				 common->rx_bufsize, dma_type);
1081 
1082 		bf->bf_mpdu = requeue_skb;
1083 		bf->bf_buf_addr = new_buf_addr;
1084 
1085 		skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1086 		if (ah->caps.rx_status_len)
1087 			skb_pull(skb, ah->caps.rx_status_len);
1088 
1089 		if (!rs.rs_more)
1090 			ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs,
1091 						     rxs, decrypt_error);
1092 
1093 		if (rs.rs_more) {
1094 			RX_STAT_INC(rx_frags);
1095 			/*
1096 			 * rs_more indicates chained descriptors which can be
1097 			 * used to link buffers together for a sort of
1098 			 * scatter-gather operation.
1099 			 */
1100 			if (sc->rx.frag) {
1101 				/* too many fragments - cannot handle frame */
1102 				dev_kfree_skb_any(sc->rx.frag);
1103 				dev_kfree_skb_any(skb);
1104 				RX_STAT_INC(rx_too_many_frags_err);
1105 				skb = NULL;
1106 			}
1107 			sc->rx.frag = skb;
1108 			goto requeue;
1109 		}
1110 
1111 		if (sc->rx.frag) {
1112 			int space = skb->len - skb_tailroom(hdr_skb);
1113 
1114 			if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1115 				dev_kfree_skb(skb);
1116 				RX_STAT_INC(rx_oom_err);
1117 				goto requeue_drop_frag;
1118 			}
1119 
1120 			sc->rx.frag = NULL;
1121 
1122 			skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1123 						  skb->len);
1124 			dev_kfree_skb_any(skb);
1125 			skb = hdr_skb;
1126 		}
1127 
1128 		if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1129 			skb_trim(skb, skb->len - 8);
1130 
1131 		spin_lock_irqsave(&sc->sc_pm_lock, flags);
1132 		if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1133 				     PS_WAIT_FOR_CAB |
1134 				     PS_WAIT_FOR_PSPOLL_DATA)) ||
1135 		    ath9k_check_auto_sleep(sc))
1136 			ath_rx_ps(sc, skb, rs.is_mybeacon);
1137 		spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1138 
1139 		ath9k_antenna_check(sc, &rs);
1140 		ath9k_apply_ampdu_details(sc, &rs, rxs);
1141 		ath_debug_rate_stats(sc, &rs, skb);
1142 
1143 		hdr = (struct ieee80211_hdr *)skb->data;
1144 		if (ieee80211_is_ack(hdr->frame_control))
1145 			ath_dynack_sample_ack_ts(sc->sc_ah, skb, rs.rs_tstamp);
1146 
1147 		ieee80211_rx(hw, skb);
1148 
1149 requeue_drop_frag:
1150 		if (sc->rx.frag) {
1151 			dev_kfree_skb_any(sc->rx.frag);
1152 			sc->rx.frag = NULL;
1153 		}
1154 requeue:
1155 		list_add_tail(&bf->list, &sc->rx.rxbuf);
1156 
1157 		if (!edma) {
1158 			ath_rx_buf_relink(sc, bf, flush);
1159 			if (!flush)
1160 				ath9k_hw_rxena(ah);
1161 		} else if (!flush) {
1162 			ath_rx_edma_buf_link(sc, qtype);
1163 		}
1164 
1165 		if (!budget--)
1166 			break;
1167 	} while (1);
1168 
1169 	if (!(ah->imask & ATH9K_INT_RXEOL)) {
1170 		ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1171 		ath9k_hw_set_interrupts(ah);
1172 	}
1173 
1174 	return 0;
1175 }
1176