1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #ifndef __RTW_PWRCTRL_H_
21 #define __RTW_PWRCTRL_H_
22
23 #include <osdep_service.h>
24 #include <drv_types.h>
25
26 #define FW_PWR0 0
27 #define FW_PWR1 1
28 #define FW_PWR2 2
29 #define FW_PWR3 3
30 #define HW_PWR0 7
31 #define HW_PWR1 6
32 #define HW_PWR2 2
33 #define HW_PWR3 0
34 #define HW_PWR4 8
35
36 #define FW_PWRMSK 0x7
37
38 #define XMIT_ALIVE BIT(0)
39 #define RECV_ALIVE BIT(1)
40 #define CMD_ALIVE BIT(2)
41 #define EVT_ALIVE BIT(3)
42
43 enum power_mgnt {
44 PS_MODE_ACTIVE = 0,
45 PS_MODE_MIN,
46 PS_MODE_MAX,
47 PS_MODE_DTIM,
48 PS_MODE_VOIP,
49 PS_MODE_UAPSD_WMM,
50 PS_MODE_UAPSD,
51 PS_MODE_IBSS,
52 PS_MODE_WWLAN,
53 PM_Radio_Off,
54 PM_Card_Disable,
55 PS_MODE_NUM
56 };
57
58 /*
59 BIT[2:0] = HW state
60 BIT[3] = Protocol PS state, 0: register active state,
61 1: register sleep state
62 BIT[4] = sub-state
63 */
64
65 #define PS_DPS BIT(0)
66 #define PS_LCLK (PS_DPS)
67 #define PS_RF_OFF BIT(1)
68 #define PS_ALL_ON BIT(2)
69 #define PS_ST_ACTIVE BIT(3)
70
71 #define PS_ISR_ENABLE BIT(4)
72 #define PS_IMR_ENABLE BIT(5)
73 #define PS_ACK BIT(6)
74 #define PS_TOGGLE BIT(7)
75
76 #define PS_STATE_MASK (0x0F)
77 #define PS_STATE_HW_MASK (0x07)
78 #define PS_SEQ_MASK (0xc0)
79
80 #define PS_STATE(x) (PS_STATE_MASK & (x))
81 #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
82 #define PS_SEQ(x) (PS_SEQ_MASK & (x))
83
84 #define PS_STATE_S0 (PS_DPS)
85 #define PS_STATE_S1 (PS_LCLK)
86 #define PS_STATE_S2 (PS_RF_OFF)
87 #define PS_STATE_S3 (PS_ALL_ON)
88 #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
89
90 #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
91 #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
92 #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
93
94 struct reportpwrstate_parm {
95 unsigned char mode;
96 unsigned char state; /* the CPWM value */
97 unsigned short rsvd;
98 };
99
_init_pwrlock(struct semaphore * plock)100 static inline void _init_pwrlock(struct semaphore *plock)
101 {
102 sema_init(plock, 1);
103 }
104
_enter_pwrlock(struct semaphore * plock)105 static inline void _enter_pwrlock(struct semaphore *plock)
106 {
107 _rtw_down_sema(plock);
108 }
109
_exit_pwrlock(struct semaphore * plock)110 static inline void _exit_pwrlock(struct semaphore *plock)
111 {
112 up(plock);
113 }
114
115 #define LPS_DELAY_TIME 1*HZ /* 1 sec */
116
117 #define EXE_PWR_NONE 0x01
118 #define EXE_PWR_IPS 0x02
119 #define EXE_PWR_LPS 0x04
120
121 /* RF state. */
122 enum rt_rf_power_state {
123 rf_on, /* RF is on after RFSleep or RFOff */
124 rf_sleep, /* 802.11 Power Save mode */
125 rf_off, /* HW/SW Radio OFF or Inactive Power Save */
126 /* Add the new RF state above this line===== */
127 rf_max
128 };
129
130 /* RF Off Level for IPS or HW/SW radio off */
131 #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */
132 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */
133 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */
134 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-init hw param*/
135 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW*/
136 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */
137 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock
138 * Req in initialization. */
139 #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R
140 * if no packet is RX or TX. */
141 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */
142
143 #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) \
144 ((ppsc->cur_ps_level & _PS_FLAG) ? true : false)
145 #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) \
146 (ppsc->cur_ps_level &= (~(_PS_FLAG)))
147 #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) \
148 (ppsc->cur_ps_level |= _PS_FLAG)
149
150 enum _PS_BBRegBackup_ {
151 PSBBREG_RF0 = 0,
152 PSBBREG_RF1,
153 PSBBREG_RF2,
154 PSBBREG_AFE0,
155 PSBBREG_TOTALCNT
156 };
157
158 enum { /* for ips_mode */
159 IPS_NONE = 0,
160 IPS_NORMAL,
161 IPS_LEVEL_2,
162 };
163
164 struct pwrctrl_priv {
165 struct semaphore lock;
166 volatile u8 rpwm; /* requested power state for fw */
167 volatile u8 cpwm; /* fw current power state. updated when
168 * 1. read from HCPWM 2. driver lowers power level */
169 volatile u8 tog; /* toggling */
170 volatile u8 cpwm_tog; /* toggling */
171
172 u8 pwr_mode;
173 u8 smart_ps;
174 u8 bcn_ant_mode;
175
176 u32 alives;
177 struct work_struct cpwm_event;
178 u8 bpower_saving;
179
180 u8 b_hw_radio_off;
181 u8 reg_rfoff;
182 u8 reg_pdnmode; /* powerdown mode */
183 u32 rfoff_reason;
184
185 /* RF OFF Level */
186 u32 cur_ps_level;
187 u32 reg_rfps_level;
188 uint ips_enter_cnts;
189 uint ips_leave_cnts;
190
191 u8 ips_mode;
192 u8 ips_mode_req; /* used to accept the mode setting request,
193 * will update to ipsmode later */
194 uint bips_processing;
195 unsigned long ips_deny_time; /* will deny IPS when system time less than this */
196 u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */
197
198 u8 bLeisurePs;
199 u8 LpsIdleCount;
200 u8 power_mgnt;
201 u8 bFwCurrentInPSMode;
202 u32 DelayLPSLastTimeStamp;
203 u8 btcoex_rfon;
204 s32 pnp_current_pwr_state;
205 u8 pnp_bstop_trx;
206
207 u8 bInternalAutoSuspend;
208 u8 bInSuspend;
209 u8 bSupportRemoteWakeup;
210 struct timer_list pwr_state_check_timer;
211 int pwr_state_check_interval;
212 u8 pwr_state_check_cnts;
213
214 int ps_flag;
215
216 enum rt_rf_power_state rf_pwrstate;/* cur power state */
217 enum rt_rf_power_state change_rfpwrstate;
218
219 u8 wepkeymask;
220 u8 bHWPowerdown;/* if support hw power down */
221 u8 bHWPwrPindetect;
222 u8 bkeepfwalive;
223 u8 brfoffbyhw;
224 unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
225 };
226
227 #define rtw_get_ips_mode_req(pwrctrlpriv) \
228 (pwrctrlpriv)->ips_mode_req
229
230 #define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
231 ((pwrctrlpriv)->ips_mode_req = (ips_mode))
232
233 #define RTW_PWR_STATE_CHK_INTERVAL 2000
234
235 #define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
236 do { \
237 _set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
238 } while (0)
239
240 #define rtw_set_pwr_state_check_timer(pwrctrl) \
241 _rtw_set_pwr_state_check_timer((pwrctrl), \
242 (pwrctrl)->pwr_state_check_interval)
243
244 void rtw_init_pwrctrl_priv(struct adapter *adapter);
245
246 void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps,
247 u8 bcn_ant_mode);
248 void rtw_set_rpwm(struct adapter *adapter, u8 val8);
249 void LeaveAllPowerSaveMode(struct adapter *adapter);
250 void ips_enter(struct adapter *padapter);
251 int ips_leave(struct adapter *padapter);
252
253 void rtw_ps_processor(struct adapter *padapter);
254
255 enum rt_rf_power_state RfOnOffDetect(struct adapter *iadapter);
256
257 s32 LPS_RF_ON_check(struct adapter *adapter, u32 delay_ms);
258 void LPS_Enter(struct adapter *adapter);
259 void LPS_Leave(struct adapter *adapter);
260
261 void rtw_set_ips_deny(struct adapter *adapter, u32 ms);
262 int _rtw_pwr_wakeup(struct adapter *adapter, u32 ips_defer_ms,
263 const char *caller);
264 #define rtw_pwr_wakeup(adapter) \
265 _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __func__)
266 #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) \
267 _rtw_pwr_wakeup(adapter, ips_deffer_ms, __func__)
268 int rtw_pm_set_ips(struct adapter *adapter, u8 mode);
269 int rtw_pm_set_lps(struct adapter *adapter, u8 mode);
270
271 #endif /* __RTL871X_PWRCTRL_H_ */
272