1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mm.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
39
40 #include <asm/bootinfo.h>
41 #include <asm/branch.h>
42 #include <asm/break.h>
43 #include <asm/cop2.h>
44 #include <asm/cpu.h>
45 #include <asm/cpu-type.h>
46 #include <asm/dsp.h>
47 #include <asm/fpu.h>
48 #include <asm/fpu_emulator.h>
49 #include <asm/idle.h>
50 #include <asm/mips-r2-to-r6-emul.h>
51 #include <asm/mipsregs.h>
52 #include <asm/mipsmtregs.h>
53 #include <asm/module.h>
54 #include <asm/msa.h>
55 #include <asm/pgtable.h>
56 #include <asm/ptrace.h>
57 #include <asm/sections.h>
58 #include <asm/siginfo.h>
59 #include <asm/tlbdebug.h>
60 #include <asm/traps.h>
61 #include <asm/uaccess.h>
62 #include <asm/watch.h>
63 #include <asm/mmu_context.h>
64 #include <asm/types.h>
65 #include <asm/stacktrace.h>
66 #include <asm/uasm.h>
67
68 extern void check_wait(void);
69 extern asmlinkage void rollback_handle_int(void);
70 extern asmlinkage void handle_int(void);
71 extern u32 handle_tlbl[];
72 extern u32 handle_tlbs[];
73 extern u32 handle_tlbm[];
74 extern asmlinkage void handle_adel(void);
75 extern asmlinkage void handle_ades(void);
76 extern asmlinkage void handle_ibe(void);
77 extern asmlinkage void handle_dbe(void);
78 extern asmlinkage void handle_sys(void);
79 extern asmlinkage void handle_bp(void);
80 extern asmlinkage void handle_ri(void);
81 extern asmlinkage void handle_ri_rdhwr_vivt(void);
82 extern asmlinkage void handle_ri_rdhwr(void);
83 extern asmlinkage void handle_cpu(void);
84 extern asmlinkage void handle_ov(void);
85 extern asmlinkage void handle_tr(void);
86 extern asmlinkage void handle_msa_fpe(void);
87 extern asmlinkage void handle_fpe(void);
88 extern asmlinkage void handle_ftlb(void);
89 extern asmlinkage void handle_msa(void);
90 extern asmlinkage void handle_mdmx(void);
91 extern asmlinkage void handle_watch(void);
92 extern asmlinkage void handle_mt(void);
93 extern asmlinkage void handle_dsp(void);
94 extern asmlinkage void handle_mcheck(void);
95 extern asmlinkage void handle_reserved(void);
96 extern void tlb_do_page_fault_0(void);
97
98 void (*board_be_init)(void);
99 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
100 void (*board_nmi_handler_setup)(void);
101 void (*board_ejtag_handler_setup)(void);
102 void (*board_bind_eic_interrupt)(int irq, int regset);
103 void (*board_ebase_setup)(void);
104 void(*board_cache_error_setup)(void);
105
show_raw_backtrace(unsigned long reg29)106 static void show_raw_backtrace(unsigned long reg29)
107 {
108 unsigned long *sp = (unsigned long *)(reg29 & ~3);
109 unsigned long addr;
110
111 printk("Call Trace:");
112 #ifdef CONFIG_KALLSYMS
113 printk("\n");
114 #endif
115 while (!kstack_end(sp)) {
116 unsigned long __user *p =
117 (unsigned long __user *)(unsigned long)sp++;
118 if (__get_user(addr, p)) {
119 printk(" (Bad stack address)");
120 break;
121 }
122 if (__kernel_text_address(addr))
123 print_ip_sym(addr);
124 }
125 printk("\n");
126 }
127
128 #ifdef CONFIG_KALLSYMS
129 int raw_show_trace;
set_raw_show_trace(char * str)130 static int __init set_raw_show_trace(char *str)
131 {
132 raw_show_trace = 1;
133 return 1;
134 }
135 __setup("raw_show_trace", set_raw_show_trace);
136 #endif
137
show_backtrace(struct task_struct * task,const struct pt_regs * regs)138 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
139 {
140 unsigned long sp = regs->regs[29];
141 unsigned long ra = regs->regs[31];
142 unsigned long pc = regs->cp0_epc;
143
144 if (!task)
145 task = current;
146
147 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
148 show_raw_backtrace(sp);
149 return;
150 }
151 printk("Call Trace:\n");
152 do {
153 print_ip_sym(pc);
154 pc = unwind_stack(task, &sp, pc, &ra);
155 } while (pc);
156 printk("\n");
157 }
158
159 /*
160 * This routine abuses get_user()/put_user() to reference pointers
161 * with at least a bit of error checking ...
162 */
show_stacktrace(struct task_struct * task,const struct pt_regs * regs)163 static void show_stacktrace(struct task_struct *task,
164 const struct pt_regs *regs)
165 {
166 const int field = 2 * sizeof(unsigned long);
167 long stackdata;
168 int i;
169 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
170
171 printk("Stack :");
172 i = 0;
173 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
174 if (i && ((i % (64 / field)) == 0))
175 printk("\n ");
176 if (i > 39) {
177 printk(" ...");
178 break;
179 }
180
181 if (__get_user(stackdata, sp++)) {
182 printk(" (Bad stack address)");
183 break;
184 }
185
186 printk(" %0*lx", field, stackdata);
187 i++;
188 }
189 printk("\n");
190 show_backtrace(task, regs);
191 }
192
show_stack(struct task_struct * task,unsigned long * sp)193 void show_stack(struct task_struct *task, unsigned long *sp)
194 {
195 struct pt_regs regs;
196 mm_segment_t old_fs = get_fs();
197
198 regs.cp0_status = KSU_KERNEL;
199 if (sp) {
200 regs.regs[29] = (unsigned long)sp;
201 regs.regs[31] = 0;
202 regs.cp0_epc = 0;
203 } else {
204 if (task && task != current) {
205 regs.regs[29] = task->thread.reg29;
206 regs.regs[31] = 0;
207 regs.cp0_epc = task->thread.reg31;
208 #ifdef CONFIG_KGDB_KDB
209 } else if (atomic_read(&kgdb_active) != -1 &&
210 kdb_current_regs) {
211 memcpy(®s, kdb_current_regs, sizeof(regs));
212 #endif /* CONFIG_KGDB_KDB */
213 } else {
214 prepare_frametrace(®s);
215 }
216 }
217 /*
218 * show_stack() deals exclusively with kernel mode, so be sure to access
219 * the stack in the kernel (not user) address space.
220 */
221 set_fs(KERNEL_DS);
222 show_stacktrace(task, ®s);
223 set_fs(old_fs);
224 }
225
show_code(unsigned int __user * pc)226 static void show_code(unsigned int __user *pc)
227 {
228 long i;
229 unsigned short __user *pc16 = NULL;
230
231 printk("\nCode:");
232
233 if ((unsigned long)pc & 1)
234 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
235 for(i = -3 ; i < 6 ; i++) {
236 unsigned int insn;
237 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
238 printk(" (Bad address in epc)\n");
239 break;
240 }
241 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
242 }
243 }
244
__show_regs(const struct pt_regs * regs)245 static void __show_regs(const struct pt_regs *regs)
246 {
247 const int field = 2 * sizeof(unsigned long);
248 unsigned int cause = regs->cp0_cause;
249 unsigned int exccode;
250 int i;
251
252 show_regs_print_info(KERN_DEFAULT);
253
254 /*
255 * Saved main processor registers
256 */
257 for (i = 0; i < 32; ) {
258 if ((i % 4) == 0)
259 printk("$%2d :", i);
260 if (i == 0)
261 printk(" %0*lx", field, 0UL);
262 else if (i == 26 || i == 27)
263 printk(" %*s", field, "");
264 else
265 printk(" %0*lx", field, regs->regs[i]);
266
267 i++;
268 if ((i % 4) == 0)
269 printk("\n");
270 }
271
272 #ifdef CONFIG_CPU_HAS_SMARTMIPS
273 printk("Acx : %0*lx\n", field, regs->acx);
274 #endif
275 printk("Hi : %0*lx\n", field, regs->hi);
276 printk("Lo : %0*lx\n", field, regs->lo);
277
278 /*
279 * Saved cp0 registers
280 */
281 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
282 (void *) regs->cp0_epc);
283 printk("ra : %0*lx %pS\n", field, regs->regs[31],
284 (void *) regs->regs[31]);
285
286 printk("Status: %08x ", (uint32_t) regs->cp0_status);
287
288 if (cpu_has_3kex) {
289 if (regs->cp0_status & ST0_KUO)
290 printk("KUo ");
291 if (regs->cp0_status & ST0_IEO)
292 printk("IEo ");
293 if (regs->cp0_status & ST0_KUP)
294 printk("KUp ");
295 if (regs->cp0_status & ST0_IEP)
296 printk("IEp ");
297 if (regs->cp0_status & ST0_KUC)
298 printk("KUc ");
299 if (regs->cp0_status & ST0_IEC)
300 printk("IEc ");
301 } else if (cpu_has_4kex) {
302 if (regs->cp0_status & ST0_KX)
303 printk("KX ");
304 if (regs->cp0_status & ST0_SX)
305 printk("SX ");
306 if (regs->cp0_status & ST0_UX)
307 printk("UX ");
308 switch (regs->cp0_status & ST0_KSU) {
309 case KSU_USER:
310 printk("USER ");
311 break;
312 case KSU_SUPERVISOR:
313 printk("SUPERVISOR ");
314 break;
315 case KSU_KERNEL:
316 printk("KERNEL ");
317 break;
318 default:
319 printk("BAD_MODE ");
320 break;
321 }
322 if (regs->cp0_status & ST0_ERL)
323 printk("ERL ");
324 if (regs->cp0_status & ST0_EXL)
325 printk("EXL ");
326 if (regs->cp0_status & ST0_IE)
327 printk("IE ");
328 }
329 printk("\n");
330
331 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
332 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
333
334 if (1 <= exccode && exccode <= 5)
335 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
336
337 printk("PrId : %08x (%s)\n", read_c0_prid(),
338 cpu_name_string());
339 }
340
341 /*
342 * FIXME: really the generic show_regs should take a const pointer argument.
343 */
show_regs(struct pt_regs * regs)344 void show_regs(struct pt_regs *regs)
345 {
346 __show_regs((struct pt_regs *)regs);
347 }
348
show_registers(struct pt_regs * regs)349 void show_registers(struct pt_regs *regs)
350 {
351 const int field = 2 * sizeof(unsigned long);
352 mm_segment_t old_fs = get_fs();
353
354 __show_regs(regs);
355 print_modules();
356 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
357 current->comm, current->pid, current_thread_info(), current,
358 field, current_thread_info()->tp_value);
359 if (cpu_has_userlocal) {
360 unsigned long tls;
361
362 tls = read_c0_userlocal();
363 if (tls != current_thread_info()->tp_value)
364 printk("*HwTLS: %0*lx\n", field, tls);
365 }
366
367 if (!user_mode(regs))
368 /* Necessary for getting the correct stack content */
369 set_fs(KERNEL_DS);
370 show_stacktrace(current, regs);
371 show_code((unsigned int __user *) regs->cp0_epc);
372 printk("\n");
373 set_fs(old_fs);
374 }
375
regs_to_trapnr(struct pt_regs * regs)376 static int regs_to_trapnr(struct pt_regs *regs)
377 {
378 return (regs->cp0_cause >> 2) & 0x1f;
379 }
380
381 static DEFINE_RAW_SPINLOCK(die_lock);
382
die(const char * str,struct pt_regs * regs)383 void __noreturn die(const char *str, struct pt_regs *regs)
384 {
385 static int die_counter;
386 int sig = SIGSEGV;
387
388 oops_enter();
389
390 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
391 SIGSEGV) == NOTIFY_STOP)
392 sig = 0;
393
394 console_verbose();
395 raw_spin_lock_irq(&die_lock);
396 bust_spinlocks(1);
397
398 printk("%s[#%d]:\n", str, ++die_counter);
399 show_registers(regs);
400 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
401 raw_spin_unlock_irq(&die_lock);
402
403 oops_exit();
404
405 if (in_interrupt())
406 panic("Fatal exception in interrupt");
407
408 if (panic_on_oops) {
409 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
410 ssleep(5);
411 panic("Fatal exception");
412 }
413
414 if (regs && kexec_should_crash(current))
415 crash_kexec(regs);
416
417 do_exit(sig);
418 }
419
420 extern struct exception_table_entry __start___dbe_table[];
421 extern struct exception_table_entry __stop___dbe_table[];
422
423 __asm__(
424 " .section __dbe_table, \"a\"\n"
425 " .previous \n");
426
427 /* Given an address, look for it in the exception tables. */
search_dbe_tables(unsigned long addr)428 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
429 {
430 const struct exception_table_entry *e;
431
432 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
433 if (!e)
434 e = search_module_dbetables(addr);
435 return e;
436 }
437
do_be(struct pt_regs * regs)438 asmlinkage void do_be(struct pt_regs *regs)
439 {
440 const int field = 2 * sizeof(unsigned long);
441 const struct exception_table_entry *fixup = NULL;
442 int data = regs->cp0_cause & 4;
443 int action = MIPS_BE_FATAL;
444 enum ctx_state prev_state;
445
446 prev_state = exception_enter();
447 /* XXX For now. Fixme, this searches the wrong table ... */
448 if (data && !user_mode(regs))
449 fixup = search_dbe_tables(exception_epc(regs));
450
451 if (fixup)
452 action = MIPS_BE_FIXUP;
453
454 if (board_be_handler)
455 action = board_be_handler(regs, fixup != NULL);
456
457 switch (action) {
458 case MIPS_BE_DISCARD:
459 goto out;
460 case MIPS_BE_FIXUP:
461 if (fixup) {
462 regs->cp0_epc = fixup->nextinsn;
463 goto out;
464 }
465 break;
466 default:
467 break;
468 }
469
470 /*
471 * Assume it would be too dangerous to continue ...
472 */
473 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
474 data ? "Data" : "Instruction",
475 field, regs->cp0_epc, field, regs->regs[31]);
476 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
477 SIGBUS) == NOTIFY_STOP)
478 goto out;
479
480 die_if_kernel("Oops", regs);
481 force_sig(SIGBUS, current);
482
483 out:
484 exception_exit(prev_state);
485 }
486
487 /*
488 * ll/sc, rdhwr, sync emulation
489 */
490
491 #define OPCODE 0xfc000000
492 #define BASE 0x03e00000
493 #define RT 0x001f0000
494 #define OFFSET 0x0000ffff
495 #define LL 0xc0000000
496 #define SC 0xe0000000
497 #define SPEC0 0x00000000
498 #define SPEC3 0x7c000000
499 #define RD 0x0000f800
500 #define FUNC 0x0000003f
501 #define SYNC 0x0000000f
502 #define RDHWR 0x0000003b
503
504 /* microMIPS definitions */
505 #define MM_POOL32A_FUNC 0xfc00ffff
506 #define MM_RDHWR 0x00006b3c
507 #define MM_RS 0x001f0000
508 #define MM_RT 0x03e00000
509
510 /*
511 * The ll_bit is cleared by r*_switch.S
512 */
513
514 unsigned int ll_bit;
515 struct task_struct *ll_task;
516
simulate_ll(struct pt_regs * regs,unsigned int opcode)517 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
518 {
519 unsigned long value, __user *vaddr;
520 long offset;
521
522 /*
523 * analyse the ll instruction that just caused a ri exception
524 * and put the referenced address to addr.
525 */
526
527 /* sign extend offset */
528 offset = opcode & OFFSET;
529 offset <<= 16;
530 offset >>= 16;
531
532 vaddr = (unsigned long __user *)
533 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
534
535 if ((unsigned long)vaddr & 3)
536 return SIGBUS;
537 if (get_user(value, vaddr))
538 return SIGSEGV;
539
540 preempt_disable();
541
542 if (ll_task == NULL || ll_task == current) {
543 ll_bit = 1;
544 } else {
545 ll_bit = 0;
546 }
547 ll_task = current;
548
549 preempt_enable();
550
551 regs->regs[(opcode & RT) >> 16] = value;
552
553 return 0;
554 }
555
simulate_sc(struct pt_regs * regs,unsigned int opcode)556 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
557 {
558 unsigned long __user *vaddr;
559 unsigned long reg;
560 long offset;
561
562 /*
563 * analyse the sc instruction that just caused a ri exception
564 * and put the referenced address to addr.
565 */
566
567 /* sign extend offset */
568 offset = opcode & OFFSET;
569 offset <<= 16;
570 offset >>= 16;
571
572 vaddr = (unsigned long __user *)
573 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
574 reg = (opcode & RT) >> 16;
575
576 if ((unsigned long)vaddr & 3)
577 return SIGBUS;
578
579 preempt_disable();
580
581 if (ll_bit == 0 || ll_task != current) {
582 regs->regs[reg] = 0;
583 preempt_enable();
584 return 0;
585 }
586
587 preempt_enable();
588
589 if (put_user(regs->regs[reg], vaddr))
590 return SIGSEGV;
591
592 regs->regs[reg] = 1;
593
594 return 0;
595 }
596
597 /*
598 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
599 * opcodes are supposed to result in coprocessor unusable exceptions if
600 * executed on ll/sc-less processors. That's the theory. In practice a
601 * few processors such as NEC's VR4100 throw reserved instruction exceptions
602 * instead, so we're doing the emulation thing in both exception handlers.
603 */
simulate_llsc(struct pt_regs * regs,unsigned int opcode)604 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
605 {
606 if ((opcode & OPCODE) == LL) {
607 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
608 1, regs, 0);
609 return simulate_ll(regs, opcode);
610 }
611 if ((opcode & OPCODE) == SC) {
612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
613 1, regs, 0);
614 return simulate_sc(regs, opcode);
615 }
616
617 return -1; /* Must be something else ... */
618 }
619
620 /*
621 * Simulate trapping 'rdhwr' instructions to provide user accessible
622 * registers not implemented in hardware.
623 */
simulate_rdhwr(struct pt_regs * regs,int rd,int rt)624 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
625 {
626 struct thread_info *ti = task_thread_info(current);
627
628 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
629 1, regs, 0);
630 switch (rd) {
631 case 0: /* CPU number */
632 regs->regs[rt] = smp_processor_id();
633 return 0;
634 case 1: /* SYNCI length */
635 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
636 current_cpu_data.icache.linesz);
637 return 0;
638 case 2: /* Read count register */
639 regs->regs[rt] = read_c0_count();
640 return 0;
641 case 3: /* Count register resolution */
642 switch (current_cpu_type()) {
643 case CPU_20KC:
644 case CPU_25KF:
645 regs->regs[rt] = 1;
646 break;
647 default:
648 regs->regs[rt] = 2;
649 }
650 return 0;
651 case 29:
652 regs->regs[rt] = ti->tp_value;
653 return 0;
654 default:
655 return -1;
656 }
657 }
658
simulate_rdhwr_normal(struct pt_regs * regs,unsigned int opcode)659 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
660 {
661 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
662 int rd = (opcode & RD) >> 11;
663 int rt = (opcode & RT) >> 16;
664
665 simulate_rdhwr(regs, rd, rt);
666 return 0;
667 }
668
669 /* Not ours. */
670 return -1;
671 }
672
simulate_rdhwr_mm(struct pt_regs * regs,unsigned short opcode)673 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
674 {
675 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
676 int rd = (opcode & MM_RS) >> 16;
677 int rt = (opcode & MM_RT) >> 21;
678 simulate_rdhwr(regs, rd, rt);
679 return 0;
680 }
681
682 /* Not ours. */
683 return -1;
684 }
685
simulate_sync(struct pt_regs * regs,unsigned int opcode)686 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
687 {
688 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
689 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
690 1, regs, 0);
691 return 0;
692 }
693
694 return -1; /* Must be something else ... */
695 }
696
do_ov(struct pt_regs * regs)697 asmlinkage void do_ov(struct pt_regs *regs)
698 {
699 enum ctx_state prev_state;
700 siginfo_t info = {
701 .si_signo = SIGFPE,
702 .si_code = FPE_INTOVF,
703 .si_addr = (void __user *)regs->cp0_epc,
704 };
705
706 prev_state = exception_enter();
707 die_if_kernel("Integer overflow", regs);
708
709 force_sig_info(SIGFPE, &info, current);
710 exception_exit(prev_state);
711 }
712
process_fpemu_return(int sig,void __user * fault_addr,unsigned long fcr31)713 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
714 {
715 struct siginfo si = { 0 };
716
717 switch (sig) {
718 case 0:
719 return 0;
720
721 case SIGFPE:
722 si.si_addr = fault_addr;
723 si.si_signo = sig;
724 /*
725 * Inexact can happen together with Overflow or Underflow.
726 * Respect the mask to deliver the correct exception.
727 */
728 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
729 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
730 if (fcr31 & FPU_CSR_INV_X)
731 si.si_code = FPE_FLTINV;
732 else if (fcr31 & FPU_CSR_DIV_X)
733 si.si_code = FPE_FLTDIV;
734 else if (fcr31 & FPU_CSR_OVF_X)
735 si.si_code = FPE_FLTOVF;
736 else if (fcr31 & FPU_CSR_UDF_X)
737 si.si_code = FPE_FLTUND;
738 else if (fcr31 & FPU_CSR_INE_X)
739 si.si_code = FPE_FLTRES;
740 else
741 si.si_code = __SI_FAULT;
742 force_sig_info(sig, &si, current);
743 return 1;
744
745 case SIGBUS:
746 si.si_addr = fault_addr;
747 si.si_signo = sig;
748 si.si_code = BUS_ADRERR;
749 force_sig_info(sig, &si, current);
750 return 1;
751
752 case SIGSEGV:
753 si.si_addr = fault_addr;
754 si.si_signo = sig;
755 down_read(¤t->mm->mmap_sem);
756 if (find_vma(current->mm, (unsigned long)fault_addr))
757 si.si_code = SEGV_ACCERR;
758 else
759 si.si_code = SEGV_MAPERR;
760 up_read(¤t->mm->mmap_sem);
761 force_sig_info(sig, &si, current);
762 return 1;
763
764 default:
765 force_sig(sig, current);
766 return 1;
767 }
768 }
769
simulate_fp(struct pt_regs * regs,unsigned int opcode,unsigned long old_epc,unsigned long old_ra)770 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
771 unsigned long old_epc, unsigned long old_ra)
772 {
773 union mips_instruction inst = { .word = opcode };
774 void __user *fault_addr;
775 unsigned long fcr31;
776 int sig;
777
778 /* If it's obviously not an FP instruction, skip it */
779 switch (inst.i_format.opcode) {
780 case cop1_op:
781 case cop1x_op:
782 case lwc1_op:
783 case ldc1_op:
784 case swc1_op:
785 case sdc1_op:
786 break;
787
788 default:
789 return -1;
790 }
791
792 /*
793 * do_ri skipped over the instruction via compute_return_epc, undo
794 * that for the FPU emulator.
795 */
796 regs->cp0_epc = old_epc;
797 regs->regs[31] = old_ra;
798
799 /* Save the FP context to struct thread_struct */
800 lose_fpu(1);
801
802 /* Run the emulator */
803 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
804 &fault_addr);
805 fcr31 = current->thread.fpu.fcr31;
806
807 /*
808 * We can't allow the emulated instruction to leave any of
809 * the cause bits set in $fcr31.
810 */
811 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
812
813 /* Restore the hardware register state */
814 own_fpu(1);
815
816 /* Send a signal if required. */
817 process_fpemu_return(sig, fault_addr, fcr31);
818
819 return 0;
820 }
821
822 /*
823 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
824 */
do_fpe(struct pt_regs * regs,unsigned long fcr31)825 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
826 {
827 enum ctx_state prev_state;
828 void __user *fault_addr;
829 int sig;
830
831 prev_state = exception_enter();
832 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
833 SIGFPE) == NOTIFY_STOP)
834 goto out;
835
836 /* Clear FCSR.Cause before enabling interrupts */
837 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
838 local_irq_enable();
839
840 die_if_kernel("FP exception in kernel code", regs);
841
842 if (fcr31 & FPU_CSR_UNI_X) {
843 /*
844 * Unimplemented operation exception. If we've got the full
845 * software emulator on-board, let's use it...
846 *
847 * Force FPU to dump state into task/thread context. We're
848 * moving a lot of data here for what is probably a single
849 * instruction, but the alternative is to pre-decode the FP
850 * register operands before invoking the emulator, which seems
851 * a bit extreme for what should be an infrequent event.
852 */
853 /* Ensure 'resume' not overwrite saved fp context again. */
854 lose_fpu(1);
855
856 /* Run the emulator */
857 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
858 &fault_addr);
859 fcr31 = current->thread.fpu.fcr31;
860
861 /*
862 * We can't allow the emulated instruction to leave any of
863 * the cause bits set in $fcr31.
864 */
865 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
866
867 /* Restore the hardware register state */
868 own_fpu(1); /* Using the FPU again. */
869 } else {
870 sig = SIGFPE;
871 fault_addr = (void __user *) regs->cp0_epc;
872 }
873
874 /* Send a signal if required. */
875 process_fpemu_return(sig, fault_addr, fcr31);
876
877 out:
878 exception_exit(prev_state);
879 }
880
do_trap_or_bp(struct pt_regs * regs,unsigned int code,int si_code,const char * str)881 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
882 const char *str)
883 {
884 siginfo_t info = { 0 };
885 char b[40];
886
887 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
888 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
889 return;
890 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
891
892 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
893 SIGTRAP) == NOTIFY_STOP)
894 return;
895
896 /*
897 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
898 * insns, even for trap and break codes that indicate arithmetic
899 * failures. Weird ...
900 * But should we continue the brokenness??? --macro
901 */
902 switch (code) {
903 case BRK_OVERFLOW:
904 case BRK_DIVZERO:
905 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
906 die_if_kernel(b, regs);
907 if (code == BRK_DIVZERO)
908 info.si_code = FPE_INTDIV;
909 else
910 info.si_code = FPE_INTOVF;
911 info.si_signo = SIGFPE;
912 info.si_addr = (void __user *) regs->cp0_epc;
913 force_sig_info(SIGFPE, &info, current);
914 break;
915 case BRK_BUG:
916 die_if_kernel("Kernel bug detected", regs);
917 force_sig(SIGTRAP, current);
918 break;
919 case BRK_MEMU:
920 /*
921 * This breakpoint code is used by the FPU emulator to retake
922 * control of the CPU after executing the instruction from the
923 * delay slot of an emulated branch.
924 *
925 * Terminate if exception was recognized as a delay slot return
926 * otherwise handle as normal.
927 */
928 if (do_dsemulret(regs))
929 return;
930
931 die_if_kernel("Math emu break/trap", regs);
932 force_sig(SIGTRAP, current);
933 break;
934 default:
935 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
936 die_if_kernel(b, regs);
937 if (si_code) {
938 info.si_signo = SIGTRAP;
939 info.si_code = si_code;
940 force_sig_info(SIGTRAP, &info, current);
941 } else {
942 force_sig(SIGTRAP, current);
943 }
944 }
945 }
946
do_bp(struct pt_regs * regs)947 asmlinkage void do_bp(struct pt_regs *regs)
948 {
949 unsigned long epc = msk_isa16_mode(exception_epc(regs));
950 unsigned int opcode, bcode;
951 enum ctx_state prev_state;
952 mm_segment_t seg;
953
954 seg = get_fs();
955 if (!user_mode(regs))
956 set_fs(KERNEL_DS);
957
958 prev_state = exception_enter();
959 if (get_isa16_mode(regs->cp0_epc)) {
960 u16 instr[2];
961
962 if (__get_user(instr[0], (u16 __user *)epc))
963 goto out_sigsegv;
964
965 if (!cpu_has_mmips) {
966 /* MIPS16e mode */
967 bcode = (instr[0] >> 5) & 0x3f;
968 } else if (mm_insn_16bit(instr[0])) {
969 /* 16-bit microMIPS BREAK */
970 bcode = instr[0] & 0xf;
971 } else {
972 /* 32-bit microMIPS BREAK */
973 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
974 goto out_sigsegv;
975 opcode = (instr[0] << 16) | instr[1];
976 bcode = (opcode >> 6) & ((1 << 20) - 1);
977 }
978 } else {
979 if (__get_user(opcode, (unsigned int __user *)epc))
980 goto out_sigsegv;
981 bcode = (opcode >> 6) & ((1 << 20) - 1);
982 }
983
984 /*
985 * There is the ancient bug in the MIPS assemblers that the break
986 * code starts left to bit 16 instead to bit 6 in the opcode.
987 * Gas is bug-compatible, but not always, grrr...
988 * We handle both cases with a simple heuristics. --macro
989 */
990 if (bcode >= (1 << 10))
991 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
992
993 /*
994 * notify the kprobe handlers, if instruction is likely to
995 * pertain to them.
996 */
997 switch (bcode) {
998 case BRK_KPROBE_BP:
999 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1000 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
1001 goto out;
1002 else
1003 break;
1004 case BRK_KPROBE_SSTEPBP:
1005 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1006 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
1007 goto out;
1008 else
1009 break;
1010 default:
1011 break;
1012 }
1013
1014 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1015
1016 out:
1017 set_fs(seg);
1018 exception_exit(prev_state);
1019 return;
1020
1021 out_sigsegv:
1022 force_sig(SIGSEGV, current);
1023 goto out;
1024 }
1025
do_tr(struct pt_regs * regs)1026 asmlinkage void do_tr(struct pt_regs *regs)
1027 {
1028 u32 opcode, tcode = 0;
1029 enum ctx_state prev_state;
1030 u16 instr[2];
1031 mm_segment_t seg;
1032 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1033
1034 seg = get_fs();
1035 if (!user_mode(regs))
1036 set_fs(get_ds());
1037
1038 prev_state = exception_enter();
1039 if (get_isa16_mode(regs->cp0_epc)) {
1040 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1041 __get_user(instr[1], (u16 __user *)(epc + 2)))
1042 goto out_sigsegv;
1043 opcode = (instr[0] << 16) | instr[1];
1044 /* Immediate versions don't provide a code. */
1045 if (!(opcode & OPCODE))
1046 tcode = (opcode >> 12) & ((1 << 4) - 1);
1047 } else {
1048 if (__get_user(opcode, (u32 __user *)epc))
1049 goto out_sigsegv;
1050 /* Immediate versions don't provide a code. */
1051 if (!(opcode & OPCODE))
1052 tcode = (opcode >> 6) & ((1 << 10) - 1);
1053 }
1054
1055 do_trap_or_bp(regs, tcode, 0, "Trap");
1056
1057 out:
1058 set_fs(seg);
1059 exception_exit(prev_state);
1060 return;
1061
1062 out_sigsegv:
1063 force_sig(SIGSEGV, current);
1064 goto out;
1065 }
1066
do_ri(struct pt_regs * regs)1067 asmlinkage void do_ri(struct pt_regs *regs)
1068 {
1069 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1070 unsigned long old_epc = regs->cp0_epc;
1071 unsigned long old31 = regs->regs[31];
1072 enum ctx_state prev_state;
1073 unsigned int opcode = 0;
1074 int status = -1;
1075
1076 /*
1077 * Avoid any kernel code. Just emulate the R2 instruction
1078 * as quickly as possible.
1079 */
1080 if (mipsr2_emulation && cpu_has_mips_r6 &&
1081 likely(user_mode(regs)) &&
1082 likely(get_user(opcode, epc) >= 0)) {
1083 unsigned long fcr31 = 0;
1084
1085 status = mipsr2_decoder(regs, opcode, &fcr31);
1086 switch (status) {
1087 case 0:
1088 case SIGEMT:
1089 task_thread_info(current)->r2_emul_return = 1;
1090 return;
1091 case SIGILL:
1092 goto no_r2_instr;
1093 default:
1094 process_fpemu_return(status,
1095 ¤t->thread.cp0_baduaddr,
1096 fcr31);
1097 task_thread_info(current)->r2_emul_return = 1;
1098 return;
1099 }
1100 }
1101
1102 no_r2_instr:
1103
1104 prev_state = exception_enter();
1105
1106 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
1107 SIGILL) == NOTIFY_STOP)
1108 goto out;
1109
1110 die_if_kernel("Reserved instruction in kernel code", regs);
1111
1112 if (unlikely(compute_return_epc(regs) < 0))
1113 goto out;
1114
1115 if (get_isa16_mode(regs->cp0_epc)) {
1116 unsigned short mmop[2] = { 0 };
1117
1118 if (unlikely(get_user(mmop[0], epc) < 0))
1119 status = SIGSEGV;
1120 if (unlikely(get_user(mmop[1], epc) < 0))
1121 status = SIGSEGV;
1122 opcode = (mmop[0] << 16) | mmop[1];
1123
1124 if (status < 0)
1125 status = simulate_rdhwr_mm(regs, opcode);
1126 } else {
1127 if (unlikely(get_user(opcode, epc) < 0))
1128 status = SIGSEGV;
1129
1130 if (!cpu_has_llsc && status < 0)
1131 status = simulate_llsc(regs, opcode);
1132
1133 if (status < 0)
1134 status = simulate_rdhwr_normal(regs, opcode);
1135
1136 if (status < 0)
1137 status = simulate_sync(regs, opcode);
1138
1139 if (status < 0)
1140 status = simulate_fp(regs, opcode, old_epc, old31);
1141 }
1142
1143 if (status < 0)
1144 status = SIGILL;
1145
1146 if (unlikely(status > 0)) {
1147 regs->cp0_epc = old_epc; /* Undo skip-over. */
1148 regs->regs[31] = old31;
1149 force_sig(status, current);
1150 }
1151
1152 out:
1153 exception_exit(prev_state);
1154 }
1155
1156 /*
1157 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1158 * emulated more than some threshold number of instructions, force migration to
1159 * a "CPU" that has FP support.
1160 */
mt_ase_fp_affinity(void)1161 static void mt_ase_fp_affinity(void)
1162 {
1163 #ifdef CONFIG_MIPS_MT_FPAFF
1164 if (mt_fpemul_threshold > 0 &&
1165 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1166 /*
1167 * If there's no FPU present, or if the application has already
1168 * restricted the allowed set to exclude any CPUs with FPUs,
1169 * we'll skip the procedure.
1170 */
1171 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1172 cpumask_t tmask;
1173
1174 current->thread.user_cpus_allowed
1175 = current->cpus_allowed;
1176 cpus_and(tmask, current->cpus_allowed,
1177 mt_fpu_cpumask);
1178 set_cpus_allowed_ptr(current, &tmask);
1179 set_thread_flag(TIF_FPUBOUND);
1180 }
1181 }
1182 #endif /* CONFIG_MIPS_MT_FPAFF */
1183 }
1184
1185 /*
1186 * No lock; only written during early bootup by CPU 0.
1187 */
1188 static RAW_NOTIFIER_HEAD(cu2_chain);
1189
register_cu2_notifier(struct notifier_block * nb)1190 int __ref register_cu2_notifier(struct notifier_block *nb)
1191 {
1192 return raw_notifier_chain_register(&cu2_chain, nb);
1193 }
1194
cu2_notifier_call_chain(unsigned long val,void * v)1195 int cu2_notifier_call_chain(unsigned long val, void *v)
1196 {
1197 return raw_notifier_call_chain(&cu2_chain, val, v);
1198 }
1199
default_cu2_call(struct notifier_block * nfb,unsigned long action,void * data)1200 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1201 void *data)
1202 {
1203 struct pt_regs *regs = data;
1204
1205 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1206 "instruction", regs);
1207 force_sig(SIGILL, current);
1208
1209 return NOTIFY_OK;
1210 }
1211
wait_on_fp_mode_switch(atomic_t * p)1212 static int wait_on_fp_mode_switch(atomic_t *p)
1213 {
1214 /*
1215 * The FP mode for this task is currently being switched. That may
1216 * involve modifications to the format of this tasks FP context which
1217 * make it unsafe to proceed with execution for the moment. Instead,
1218 * schedule some other task.
1219 */
1220 schedule();
1221 return 0;
1222 }
1223
enable_restore_fp_context(int msa)1224 static int enable_restore_fp_context(int msa)
1225 {
1226 int err, was_fpu_owner, prior_msa;
1227
1228 /*
1229 * If an FP mode switch is currently underway, wait for it to
1230 * complete before proceeding.
1231 */
1232 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1233 wait_on_fp_mode_switch, TASK_KILLABLE);
1234
1235 if (!used_math()) {
1236 /* First time FP context user. */
1237 preempt_disable();
1238 err = init_fpu();
1239 if (msa && !err) {
1240 enable_msa();
1241 init_msa_upper();
1242 set_thread_flag(TIF_USEDMSA);
1243 set_thread_flag(TIF_MSA_CTX_LIVE);
1244 }
1245 preempt_enable();
1246 if (!err)
1247 set_used_math();
1248 return err;
1249 }
1250
1251 /*
1252 * This task has formerly used the FP context.
1253 *
1254 * If this thread has no live MSA vector context then we can simply
1255 * restore the scalar FP context. If it has live MSA vector context
1256 * (that is, it has or may have used MSA since last performing a
1257 * function call) then we'll need to restore the vector context. This
1258 * applies even if we're currently only executing a scalar FP
1259 * instruction. This is because if we were to later execute an MSA
1260 * instruction then we'd either have to:
1261 *
1262 * - Restore the vector context & clobber any registers modified by
1263 * scalar FP instructions between now & then.
1264 *
1265 * or
1266 *
1267 * - Not restore the vector context & lose the most significant bits
1268 * of all vector registers.
1269 *
1270 * Neither of those options is acceptable. We cannot restore the least
1271 * significant bits of the registers now & only restore the most
1272 * significant bits later because the most significant bits of any
1273 * vector registers whose aliased FP register is modified now will have
1274 * been zeroed. We'd have no way to know that when restoring the vector
1275 * context & thus may load an outdated value for the most significant
1276 * bits of a vector register.
1277 */
1278 if (!msa && !thread_msa_context_live())
1279 return own_fpu(1);
1280
1281 /*
1282 * This task is using or has previously used MSA. Thus we require
1283 * that Status.FR == 1.
1284 */
1285 preempt_disable();
1286 was_fpu_owner = is_fpu_owner();
1287 err = own_fpu_inatomic(0);
1288 if (err)
1289 goto out;
1290
1291 enable_msa();
1292 write_msa_csr(current->thread.fpu.msacsr);
1293 set_thread_flag(TIF_USEDMSA);
1294
1295 /*
1296 * If this is the first time that the task is using MSA and it has
1297 * previously used scalar FP in this time slice then we already nave
1298 * FP context which we shouldn't clobber. We do however need to clear
1299 * the upper 64b of each vector register so that this task has no
1300 * opportunity to see data left behind by another.
1301 */
1302 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1303 if (!prior_msa && was_fpu_owner) {
1304 init_msa_upper();
1305
1306 goto out;
1307 }
1308
1309 if (!prior_msa) {
1310 /*
1311 * Restore the least significant 64b of each vector register
1312 * from the existing scalar FP context.
1313 */
1314 _restore_fp(current);
1315
1316 /*
1317 * The task has not formerly used MSA, so clear the upper 64b
1318 * of each vector register such that it cannot see data left
1319 * behind by another task.
1320 */
1321 init_msa_upper();
1322 } else {
1323 /* We need to restore the vector context. */
1324 restore_msa(current);
1325
1326 /* Restore the scalar FP control & status register */
1327 if (!was_fpu_owner)
1328 write_32bit_cp1_register(CP1_STATUS,
1329 current->thread.fpu.fcr31);
1330 }
1331
1332 out:
1333 preempt_enable();
1334
1335 return 0;
1336 }
1337
do_cpu(struct pt_regs * regs)1338 asmlinkage void do_cpu(struct pt_regs *regs)
1339 {
1340 enum ctx_state prev_state;
1341 unsigned int __user *epc;
1342 unsigned long old_epc, old31;
1343 void __user *fault_addr;
1344 unsigned int opcode;
1345 unsigned long fcr31;
1346 unsigned int cpid;
1347 int status, err;
1348 unsigned long __maybe_unused flags;
1349 int sig;
1350
1351 prev_state = exception_enter();
1352 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1353
1354 if (cpid != 2)
1355 die_if_kernel("do_cpu invoked from kernel context!", regs);
1356
1357 switch (cpid) {
1358 case 0:
1359 epc = (unsigned int __user *)exception_epc(regs);
1360 old_epc = regs->cp0_epc;
1361 old31 = regs->regs[31];
1362 opcode = 0;
1363 status = -1;
1364
1365 if (unlikely(compute_return_epc(regs) < 0))
1366 break;
1367
1368 if (get_isa16_mode(regs->cp0_epc)) {
1369 unsigned short mmop[2] = { 0 };
1370
1371 if (unlikely(get_user(mmop[0], epc) < 0))
1372 status = SIGSEGV;
1373 if (unlikely(get_user(mmop[1], epc) < 0))
1374 status = SIGSEGV;
1375 opcode = (mmop[0] << 16) | mmop[1];
1376
1377 if (status < 0)
1378 status = simulate_rdhwr_mm(regs, opcode);
1379 } else {
1380 if (unlikely(get_user(opcode, epc) < 0))
1381 status = SIGSEGV;
1382
1383 if (!cpu_has_llsc && status < 0)
1384 status = simulate_llsc(regs, opcode);
1385
1386 if (status < 0)
1387 status = simulate_rdhwr_normal(regs, opcode);
1388 }
1389
1390 if (status < 0)
1391 status = SIGILL;
1392
1393 if (unlikely(status > 0)) {
1394 regs->cp0_epc = old_epc; /* Undo skip-over. */
1395 regs->regs[31] = old31;
1396 force_sig(status, current);
1397 }
1398
1399 break;
1400
1401 case 3:
1402 /*
1403 * The COP3 opcode space and consequently the CP0.Status.CU3
1404 * bit and the CP0.Cause.CE=3 encoding have been removed as
1405 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1406 * up the space has been reused for COP1X instructions, that
1407 * are enabled by the CP0.Status.CU1 bit and consequently
1408 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1409 * exceptions. Some FPU-less processors that implement one
1410 * of these ISAs however use this code erroneously for COP1X
1411 * instructions. Therefore we redirect this trap to the FP
1412 * emulator too.
1413 */
1414 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1415 force_sig(SIGILL, current);
1416 break;
1417 }
1418 /* Fall through. */
1419
1420 case 1:
1421 err = enable_restore_fp_context(0);
1422
1423 if (raw_cpu_has_fpu && !err)
1424 break;
1425
1426 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1427 &fault_addr);
1428 fcr31 = current->thread.fpu.fcr31;
1429
1430 /*
1431 * We can't allow the emulated instruction to leave
1432 * any of the cause bits set in $fcr31.
1433 */
1434 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1435
1436 /* Send a signal if required. */
1437 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1438 mt_ase_fp_affinity();
1439
1440 break;
1441
1442 case 2:
1443 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1444 break;
1445 }
1446
1447 exception_exit(prev_state);
1448 }
1449
do_msa_fpe(struct pt_regs * regs,unsigned int msacsr)1450 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1451 {
1452 enum ctx_state prev_state;
1453
1454 prev_state = exception_enter();
1455 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1456 regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP)
1457 goto out;
1458
1459 /* Clear MSACSR.Cause before enabling interrupts */
1460 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1461 local_irq_enable();
1462
1463 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1464 force_sig(SIGFPE, current);
1465 out:
1466 exception_exit(prev_state);
1467 }
1468
do_msa(struct pt_regs * regs)1469 asmlinkage void do_msa(struct pt_regs *regs)
1470 {
1471 enum ctx_state prev_state;
1472 int err;
1473
1474 prev_state = exception_enter();
1475
1476 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1477 force_sig(SIGILL, current);
1478 goto out;
1479 }
1480
1481 die_if_kernel("do_msa invoked from kernel context!", regs);
1482
1483 err = enable_restore_fp_context(1);
1484 if (err)
1485 force_sig(SIGILL, current);
1486 out:
1487 exception_exit(prev_state);
1488 }
1489
do_mdmx(struct pt_regs * regs)1490 asmlinkage void do_mdmx(struct pt_regs *regs)
1491 {
1492 enum ctx_state prev_state;
1493
1494 prev_state = exception_enter();
1495 force_sig(SIGILL, current);
1496 exception_exit(prev_state);
1497 }
1498
1499 /*
1500 * Called with interrupts disabled.
1501 */
do_watch(struct pt_regs * regs)1502 asmlinkage void do_watch(struct pt_regs *regs)
1503 {
1504 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1505 enum ctx_state prev_state;
1506 u32 cause;
1507
1508 prev_state = exception_enter();
1509 /*
1510 * Clear WP (bit 22) bit of cause register so we don't loop
1511 * forever.
1512 */
1513 cause = read_c0_cause();
1514 cause &= ~(1 << 22);
1515 write_c0_cause(cause);
1516
1517 /*
1518 * If the current thread has the watch registers loaded, save
1519 * their values and send SIGTRAP. Otherwise another thread
1520 * left the registers set, clear them and continue.
1521 */
1522 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1523 mips_read_watch_registers();
1524 local_irq_enable();
1525 force_sig_info(SIGTRAP, &info, current);
1526 } else {
1527 mips_clear_watch_registers();
1528 local_irq_enable();
1529 }
1530 exception_exit(prev_state);
1531 }
1532
do_mcheck(struct pt_regs * regs)1533 asmlinkage void do_mcheck(struct pt_regs *regs)
1534 {
1535 const int field = 2 * sizeof(unsigned long);
1536 int multi_match = regs->cp0_status & ST0_TS;
1537 enum ctx_state prev_state;
1538 mm_segment_t old_fs = get_fs();
1539
1540 prev_state = exception_enter();
1541 show_regs(regs);
1542
1543 if (multi_match) {
1544 pr_err("Index : %0x\n", read_c0_index());
1545 pr_err("Pagemask: %0x\n", read_c0_pagemask());
1546 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
1547 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1548 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1549 pr_err("Wired : %0x\n", read_c0_wired());
1550 pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
1551 if (cpu_has_htw) {
1552 pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
1553 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());
1554 pr_err("PWCtl : %0x\n", read_c0_pwctl());
1555 }
1556 pr_err("\n");
1557 dump_tlb_all();
1558 }
1559
1560 if (!user_mode(regs))
1561 set_fs(KERNEL_DS);
1562
1563 show_code((unsigned int __user *) regs->cp0_epc);
1564
1565 set_fs(old_fs);
1566
1567 /*
1568 * Some chips may have other causes of machine check (e.g. SB1
1569 * graduation timer)
1570 */
1571 panic("Caught Machine Check exception - %scaused by multiple "
1572 "matching entries in the TLB.",
1573 (multi_match) ? "" : "not ");
1574 }
1575
do_mt(struct pt_regs * regs)1576 asmlinkage void do_mt(struct pt_regs *regs)
1577 {
1578 int subcode;
1579
1580 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1581 >> VPECONTROL_EXCPT_SHIFT;
1582 switch (subcode) {
1583 case 0:
1584 printk(KERN_DEBUG "Thread Underflow\n");
1585 break;
1586 case 1:
1587 printk(KERN_DEBUG "Thread Overflow\n");
1588 break;
1589 case 2:
1590 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1591 break;
1592 case 3:
1593 printk(KERN_DEBUG "Gating Storage Exception\n");
1594 break;
1595 case 4:
1596 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1597 break;
1598 case 5:
1599 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1600 break;
1601 default:
1602 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1603 subcode);
1604 break;
1605 }
1606 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1607
1608 force_sig(SIGILL, current);
1609 }
1610
1611
do_dsp(struct pt_regs * regs)1612 asmlinkage void do_dsp(struct pt_regs *regs)
1613 {
1614 if (cpu_has_dsp)
1615 panic("Unexpected DSP exception");
1616
1617 force_sig(SIGILL, current);
1618 }
1619
do_reserved(struct pt_regs * regs)1620 asmlinkage void do_reserved(struct pt_regs *regs)
1621 {
1622 /*
1623 * Game over - no way to handle this if it ever occurs. Most probably
1624 * caused by a new unknown cpu type or after another deadly
1625 * hard/software error.
1626 */
1627 show_regs(regs);
1628 panic("Caught reserved exception %ld - should not happen.",
1629 (regs->cp0_cause & 0x7f) >> 2);
1630 }
1631
1632 static int __initdata l1parity = 1;
nol1parity(char * s)1633 static int __init nol1parity(char *s)
1634 {
1635 l1parity = 0;
1636 return 1;
1637 }
1638 __setup("nol1par", nol1parity);
1639 static int __initdata l2parity = 1;
nol2parity(char * s)1640 static int __init nol2parity(char *s)
1641 {
1642 l2parity = 0;
1643 return 1;
1644 }
1645 __setup("nol2par", nol2parity);
1646
1647 /*
1648 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1649 * it different ways.
1650 */
parity_protection_init(void)1651 static inline void parity_protection_init(void)
1652 {
1653 switch (current_cpu_type()) {
1654 case CPU_24K:
1655 case CPU_34K:
1656 case CPU_74K:
1657 case CPU_1004K:
1658 case CPU_1074K:
1659 case CPU_INTERAPTIV:
1660 case CPU_PROAPTIV:
1661 case CPU_P5600:
1662 case CPU_QEMU_GENERIC:
1663 {
1664 #define ERRCTL_PE 0x80000000
1665 #define ERRCTL_L2P 0x00800000
1666 unsigned long errctl;
1667 unsigned int l1parity_present, l2parity_present;
1668
1669 errctl = read_c0_ecc();
1670 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1671
1672 /* probe L1 parity support */
1673 write_c0_ecc(errctl | ERRCTL_PE);
1674 back_to_back_c0_hazard();
1675 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1676
1677 /* probe L2 parity support */
1678 write_c0_ecc(errctl|ERRCTL_L2P);
1679 back_to_back_c0_hazard();
1680 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1681
1682 if (l1parity_present && l2parity_present) {
1683 if (l1parity)
1684 errctl |= ERRCTL_PE;
1685 if (l1parity ^ l2parity)
1686 errctl |= ERRCTL_L2P;
1687 } else if (l1parity_present) {
1688 if (l1parity)
1689 errctl |= ERRCTL_PE;
1690 } else if (l2parity_present) {
1691 if (l2parity)
1692 errctl |= ERRCTL_L2P;
1693 } else {
1694 /* No parity available */
1695 }
1696
1697 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1698
1699 write_c0_ecc(errctl);
1700 back_to_back_c0_hazard();
1701 errctl = read_c0_ecc();
1702 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1703
1704 if (l1parity_present)
1705 printk(KERN_INFO "Cache parity protection %sabled\n",
1706 (errctl & ERRCTL_PE) ? "en" : "dis");
1707
1708 if (l2parity_present) {
1709 if (l1parity_present && l1parity)
1710 errctl ^= ERRCTL_L2P;
1711 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1712 (errctl & ERRCTL_L2P) ? "en" : "dis");
1713 }
1714 }
1715 break;
1716
1717 case CPU_5KC:
1718 case CPU_5KE:
1719 case CPU_LOONGSON1:
1720 write_c0_ecc(0x80000000);
1721 back_to_back_c0_hazard();
1722 /* Set the PE bit (bit 31) in the c0_errctl register. */
1723 printk(KERN_INFO "Cache parity protection %sabled\n",
1724 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1725 break;
1726 case CPU_20KC:
1727 case CPU_25KF:
1728 /* Clear the DE bit (bit 16) in the c0_status register. */
1729 printk(KERN_INFO "Enable cache parity protection for "
1730 "MIPS 20KC/25KF CPUs.\n");
1731 clear_c0_status(ST0_DE);
1732 break;
1733 default:
1734 break;
1735 }
1736 }
1737
cache_parity_error(void)1738 asmlinkage void cache_parity_error(void)
1739 {
1740 const int field = 2 * sizeof(unsigned long);
1741 unsigned int reg_val;
1742
1743 /* For the moment, report the problem and hang. */
1744 printk("Cache error exception:\n");
1745 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1746 reg_val = read_c0_cacheerr();
1747 printk("c0_cacheerr == %08x\n", reg_val);
1748
1749 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1750 reg_val & (1<<30) ? "secondary" : "primary",
1751 reg_val & (1<<31) ? "data" : "insn");
1752 if ((cpu_has_mips_r2_r6) &&
1753 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1754 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1755 reg_val & (1<<29) ? "ED " : "",
1756 reg_val & (1<<28) ? "ET " : "",
1757 reg_val & (1<<27) ? "ES " : "",
1758 reg_val & (1<<26) ? "EE " : "",
1759 reg_val & (1<<25) ? "EB " : "",
1760 reg_val & (1<<24) ? "EI " : "",
1761 reg_val & (1<<23) ? "E1 " : "",
1762 reg_val & (1<<22) ? "E0 " : "");
1763 } else {
1764 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1765 reg_val & (1<<29) ? "ED " : "",
1766 reg_val & (1<<28) ? "ET " : "",
1767 reg_val & (1<<26) ? "EE " : "",
1768 reg_val & (1<<25) ? "EB " : "",
1769 reg_val & (1<<24) ? "EI " : "",
1770 reg_val & (1<<23) ? "E1 " : "",
1771 reg_val & (1<<22) ? "E0 " : "");
1772 }
1773 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1774
1775 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1776 if (reg_val & (1<<22))
1777 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1778
1779 if (reg_val & (1<<23))
1780 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1781 #endif
1782
1783 panic("Can't handle the cache error!");
1784 }
1785
do_ftlb(void)1786 asmlinkage void do_ftlb(void)
1787 {
1788 const int field = 2 * sizeof(unsigned long);
1789 unsigned int reg_val;
1790
1791 /* For the moment, report the problem and hang. */
1792 if ((cpu_has_mips_r2_r6) &&
1793 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1794 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1795 read_c0_ecc());
1796 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1797 reg_val = read_c0_cacheerr();
1798 pr_err("c0_cacheerr == %08x\n", reg_val);
1799
1800 if ((reg_val & 0xc0000000) == 0xc0000000) {
1801 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1802 } else {
1803 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1804 reg_val & (1<<30) ? "secondary" : "primary",
1805 reg_val & (1<<31) ? "data" : "insn");
1806 }
1807 } else {
1808 pr_err("FTLB error exception\n");
1809 }
1810 /* Just print the cacheerr bits for now */
1811 cache_parity_error();
1812 }
1813
1814 /*
1815 * SDBBP EJTAG debug exception handler.
1816 * We skip the instruction and return to the next instruction.
1817 */
ejtag_exception_handler(struct pt_regs * regs)1818 void ejtag_exception_handler(struct pt_regs *regs)
1819 {
1820 const int field = 2 * sizeof(unsigned long);
1821 unsigned long depc, old_epc, old_ra;
1822 unsigned int debug;
1823
1824 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1825 depc = read_c0_depc();
1826 debug = read_c0_debug();
1827 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1828 if (debug & 0x80000000) {
1829 /*
1830 * In branch delay slot.
1831 * We cheat a little bit here and use EPC to calculate the
1832 * debug return address (DEPC). EPC is restored after the
1833 * calculation.
1834 */
1835 old_epc = regs->cp0_epc;
1836 old_ra = regs->regs[31];
1837 regs->cp0_epc = depc;
1838 compute_return_epc(regs);
1839 depc = regs->cp0_epc;
1840 regs->cp0_epc = old_epc;
1841 regs->regs[31] = old_ra;
1842 } else
1843 depc += 4;
1844 write_c0_depc(depc);
1845
1846 #if 0
1847 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1848 write_c0_debug(debug | 0x100);
1849 #endif
1850 }
1851
1852 /*
1853 * NMI exception handler.
1854 * No lock; only written during early bootup by CPU 0.
1855 */
1856 static RAW_NOTIFIER_HEAD(nmi_chain);
1857
register_nmi_notifier(struct notifier_block * nb)1858 int register_nmi_notifier(struct notifier_block *nb)
1859 {
1860 return raw_notifier_chain_register(&nmi_chain, nb);
1861 }
1862
nmi_exception_handler(struct pt_regs * regs)1863 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1864 {
1865 char str[100];
1866
1867 raw_notifier_call_chain(&nmi_chain, 0, regs);
1868 bust_spinlocks(1);
1869 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1870 smp_processor_id(), regs->cp0_epc);
1871 regs->cp0_epc = read_c0_errorepc();
1872 die(str, regs);
1873 }
1874
1875 #define VECTORSPACING 0x100 /* for EI/VI mode */
1876
1877 unsigned long ebase;
1878 unsigned long exception_handlers[32];
1879 unsigned long vi_handlers[64];
1880
set_except_vector(int n,void * addr)1881 void __init *set_except_vector(int n, void *addr)
1882 {
1883 unsigned long handler = (unsigned long) addr;
1884 unsigned long old_handler;
1885
1886 #ifdef CONFIG_CPU_MICROMIPS
1887 /*
1888 * Only the TLB handlers are cache aligned with an even
1889 * address. All other handlers are on an odd address and
1890 * require no modification. Otherwise, MIPS32 mode will
1891 * be entered when handling any TLB exceptions. That
1892 * would be bad...since we must stay in microMIPS mode.
1893 */
1894 if (!(handler & 0x1))
1895 handler |= 1;
1896 #endif
1897 old_handler = xchg(&exception_handlers[n], handler);
1898
1899 if (n == 0 && cpu_has_divec) {
1900 #ifdef CONFIG_CPU_MICROMIPS
1901 unsigned long jump_mask = ~((1 << 27) - 1);
1902 #else
1903 unsigned long jump_mask = ~((1 << 28) - 1);
1904 #endif
1905 u32 *buf = (u32 *)(ebase + 0x200);
1906 unsigned int k0 = 26;
1907 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1908 uasm_i_j(&buf, handler & ~jump_mask);
1909 uasm_i_nop(&buf);
1910 } else {
1911 UASM_i_LA(&buf, k0, handler);
1912 uasm_i_jr(&buf, k0);
1913 uasm_i_nop(&buf);
1914 }
1915 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1916 }
1917 return (void *)old_handler;
1918 }
1919
do_default_vi(void)1920 static void do_default_vi(void)
1921 {
1922 show_regs(get_irq_regs());
1923 panic("Caught unexpected vectored interrupt.");
1924 }
1925
set_vi_srs_handler(int n,vi_handler_t addr,int srs)1926 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1927 {
1928 unsigned long handler;
1929 unsigned long old_handler = vi_handlers[n];
1930 int srssets = current_cpu_data.srsets;
1931 u16 *h;
1932 unsigned char *b;
1933
1934 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1935
1936 if (addr == NULL) {
1937 handler = (unsigned long) do_default_vi;
1938 srs = 0;
1939 } else
1940 handler = (unsigned long) addr;
1941 vi_handlers[n] = handler;
1942
1943 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1944
1945 if (srs >= srssets)
1946 panic("Shadow register set %d not supported", srs);
1947
1948 if (cpu_has_veic) {
1949 if (board_bind_eic_interrupt)
1950 board_bind_eic_interrupt(n, srs);
1951 } else if (cpu_has_vint) {
1952 /* SRSMap is only defined if shadow sets are implemented */
1953 if (srssets > 1)
1954 change_c0_srsmap(0xf << n*4, srs << n*4);
1955 }
1956
1957 if (srs == 0) {
1958 /*
1959 * If no shadow set is selected then use the default handler
1960 * that does normal register saving and standard interrupt exit
1961 */
1962 extern char except_vec_vi, except_vec_vi_lui;
1963 extern char except_vec_vi_ori, except_vec_vi_end;
1964 extern char rollback_except_vec_vi;
1965 char *vec_start = using_rollback_handler() ?
1966 &rollback_except_vec_vi : &except_vec_vi;
1967 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1968 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1969 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1970 #else
1971 const int lui_offset = &except_vec_vi_lui - vec_start;
1972 const int ori_offset = &except_vec_vi_ori - vec_start;
1973 #endif
1974 const int handler_len = &except_vec_vi_end - vec_start;
1975
1976 if (handler_len > VECTORSPACING) {
1977 /*
1978 * Sigh... panicing won't help as the console
1979 * is probably not configured :(
1980 */
1981 panic("VECTORSPACING too small");
1982 }
1983
1984 set_handler(((unsigned long)b - ebase), vec_start,
1985 #ifdef CONFIG_CPU_MICROMIPS
1986 (handler_len - 1));
1987 #else
1988 handler_len);
1989 #endif
1990 h = (u16 *)(b + lui_offset);
1991 *h = (handler >> 16) & 0xffff;
1992 h = (u16 *)(b + ori_offset);
1993 *h = (handler & 0xffff);
1994 local_flush_icache_range((unsigned long)b,
1995 (unsigned long)(b+handler_len));
1996 }
1997 else {
1998 /*
1999 * In other cases jump directly to the interrupt handler. It
2000 * is the handler's responsibility to save registers if required
2001 * (eg hi/lo) and return from the exception using "eret".
2002 */
2003 u32 insn;
2004
2005 h = (u16 *)b;
2006 /* j handler */
2007 #ifdef CONFIG_CPU_MICROMIPS
2008 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2009 #else
2010 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2011 #endif
2012 h[0] = (insn >> 16) & 0xffff;
2013 h[1] = insn & 0xffff;
2014 h[2] = 0;
2015 h[3] = 0;
2016 local_flush_icache_range((unsigned long)b,
2017 (unsigned long)(b+8));
2018 }
2019
2020 return (void *)old_handler;
2021 }
2022
set_vi_handler(int n,vi_handler_t addr)2023 void *set_vi_handler(int n, vi_handler_t addr)
2024 {
2025 return set_vi_srs_handler(n, addr, 0);
2026 }
2027
2028 extern void tlb_init(void);
2029
2030 /*
2031 * Timer interrupt
2032 */
2033 int cp0_compare_irq;
2034 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2035 int cp0_compare_irq_shift;
2036
2037 /*
2038 * Performance counter IRQ or -1 if shared with timer
2039 */
2040 int cp0_perfcount_irq;
2041 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2042
2043 static int noulri;
2044
ulri_disable(char * s)2045 static int __init ulri_disable(char *s)
2046 {
2047 pr_info("Disabling ulri\n");
2048 noulri = 1;
2049
2050 return 1;
2051 }
2052 __setup("noulri", ulri_disable);
2053
2054 /* configure STATUS register */
configure_status(void)2055 static void configure_status(void)
2056 {
2057 /*
2058 * Disable coprocessors and select 32-bit or 64-bit addressing
2059 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2060 * flag that some firmware may have left set and the TS bit (for
2061 * IP27). Set XX for ISA IV code to work.
2062 */
2063 unsigned int status_set = ST0_CU0;
2064 #ifdef CONFIG_64BIT
2065 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2066 #endif
2067 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2068 status_set |= ST0_XX;
2069 if (cpu_has_dsp)
2070 status_set |= ST0_MX;
2071
2072 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2073 status_set);
2074 }
2075
2076 /* configure HWRENA register */
configure_hwrena(void)2077 static void configure_hwrena(void)
2078 {
2079 unsigned int hwrena = cpu_hwrena_impl_bits;
2080
2081 if (cpu_has_mips_r2_r6)
2082 hwrena |= 0x0000000f;
2083
2084 if (!noulri && cpu_has_userlocal)
2085 hwrena |= (1 << 29);
2086
2087 if (hwrena)
2088 write_c0_hwrena(hwrena);
2089 }
2090
configure_exception_vector(void)2091 static void configure_exception_vector(void)
2092 {
2093 if (cpu_has_veic || cpu_has_vint) {
2094 unsigned long sr = set_c0_status(ST0_BEV);
2095 write_c0_ebase(ebase);
2096 write_c0_status(sr);
2097 /* Setting vector spacing enables EI/VI mode */
2098 change_c0_intctl(0x3e0, VECTORSPACING);
2099 }
2100 if (cpu_has_divec) {
2101 if (cpu_has_mipsmt) {
2102 unsigned int vpflags = dvpe();
2103 set_c0_cause(CAUSEF_IV);
2104 evpe(vpflags);
2105 } else
2106 set_c0_cause(CAUSEF_IV);
2107 }
2108 }
2109
per_cpu_trap_init(bool is_boot_cpu)2110 void per_cpu_trap_init(bool is_boot_cpu)
2111 {
2112 unsigned int cpu = smp_processor_id();
2113
2114 configure_status();
2115 configure_hwrena();
2116
2117 configure_exception_vector();
2118
2119 /*
2120 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2121 *
2122 * o read IntCtl.IPTI to determine the timer interrupt
2123 * o read IntCtl.IPPCI to determine the performance counter interrupt
2124 */
2125 if (cpu_has_mips_r2_r6) {
2126 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2127 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2128 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2129 if (cp0_perfcount_irq == cp0_compare_irq)
2130 cp0_perfcount_irq = -1;
2131 } else {
2132 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2133 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2134 cp0_perfcount_irq = -1;
2135 }
2136
2137 if (!cpu_data[cpu].asid_cache)
2138 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2139
2140 atomic_inc(&init_mm.mm_count);
2141 current->active_mm = &init_mm;
2142 BUG_ON(current->mm);
2143 enter_lazy_tlb(&init_mm, current);
2144
2145 /* Boot CPU's cache setup in setup_arch(). */
2146 if (!is_boot_cpu)
2147 cpu_cache_init();
2148 tlb_init();
2149 TLBMISS_HANDLER_SETUP();
2150 }
2151
2152 /* Install CPU exception handler */
set_handler(unsigned long offset,void * addr,unsigned long size)2153 void set_handler(unsigned long offset, void *addr, unsigned long size)
2154 {
2155 #ifdef CONFIG_CPU_MICROMIPS
2156 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2157 #else
2158 memcpy((void *)(ebase + offset), addr, size);
2159 #endif
2160 local_flush_icache_range(ebase + offset, ebase + offset + size);
2161 }
2162
2163 static char panic_null_cerr[] =
2164 "Trying to set NULL cache error exception handler";
2165
2166 /*
2167 * Install uncached CPU exception handler.
2168 * This is suitable only for the cache error exception which is the only
2169 * exception handler that is being run uncached.
2170 */
set_uncached_handler(unsigned long offset,void * addr,unsigned long size)2171 void set_uncached_handler(unsigned long offset, void *addr,
2172 unsigned long size)
2173 {
2174 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2175
2176 if (!addr)
2177 panic(panic_null_cerr);
2178
2179 memcpy((void *)(uncached_ebase + offset), addr, size);
2180 }
2181
2182 static int __initdata rdhwr_noopt;
set_rdhwr_noopt(char * str)2183 static int __init set_rdhwr_noopt(char *str)
2184 {
2185 rdhwr_noopt = 1;
2186 return 1;
2187 }
2188
2189 __setup("rdhwr_noopt", set_rdhwr_noopt);
2190
trap_init(void)2191 void __init trap_init(void)
2192 {
2193 extern char except_vec3_generic;
2194 extern char except_vec4;
2195 extern char except_vec3_r4000;
2196 unsigned long i;
2197
2198 check_wait();
2199
2200 if (cpu_has_veic || cpu_has_vint) {
2201 unsigned long size = 0x200 + VECTORSPACING*64;
2202 ebase = (unsigned long)
2203 __alloc_bootmem(size, 1 << fls(size), 0);
2204 } else {
2205 #ifdef CONFIG_KVM_GUEST
2206 #define KVM_GUEST_KSEG0 0x40000000
2207 ebase = KVM_GUEST_KSEG0;
2208 #else
2209 ebase = CKSEG0;
2210 #endif
2211 if (cpu_has_mips_r2_r6)
2212 ebase += (read_c0_ebase() & 0x3ffff000);
2213 }
2214
2215 if (cpu_has_mmips) {
2216 unsigned int config3 = read_c0_config3();
2217
2218 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2219 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2220 else
2221 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2222 }
2223
2224 if (board_ebase_setup)
2225 board_ebase_setup();
2226 per_cpu_trap_init(true);
2227
2228 /*
2229 * Copy the generic exception handlers to their final destination.
2230 * This will be overriden later as suitable for a particular
2231 * configuration.
2232 */
2233 set_handler(0x180, &except_vec3_generic, 0x80);
2234
2235 /*
2236 * Setup default vectors
2237 */
2238 for (i = 0; i <= 31; i++)
2239 set_except_vector(i, handle_reserved);
2240
2241 /*
2242 * Copy the EJTAG debug exception vector handler code to it's final
2243 * destination.
2244 */
2245 if (cpu_has_ejtag && board_ejtag_handler_setup)
2246 board_ejtag_handler_setup();
2247
2248 /*
2249 * Only some CPUs have the watch exceptions.
2250 */
2251 if (cpu_has_watch)
2252 set_except_vector(23, handle_watch);
2253
2254 /*
2255 * Initialise interrupt handlers
2256 */
2257 if (cpu_has_veic || cpu_has_vint) {
2258 int nvec = cpu_has_veic ? 64 : 8;
2259 for (i = 0; i < nvec; i++)
2260 set_vi_handler(i, NULL);
2261 }
2262 else if (cpu_has_divec)
2263 set_handler(0x200, &except_vec4, 0x8);
2264
2265 /*
2266 * Some CPUs can enable/disable for cache parity detection, but does
2267 * it different ways.
2268 */
2269 parity_protection_init();
2270
2271 /*
2272 * The Data Bus Errors / Instruction Bus Errors are signaled
2273 * by external hardware. Therefore these two exceptions
2274 * may have board specific handlers.
2275 */
2276 if (board_be_init)
2277 board_be_init();
2278
2279 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2280 : handle_int);
2281 set_except_vector(1, handle_tlbm);
2282 set_except_vector(2, handle_tlbl);
2283 set_except_vector(3, handle_tlbs);
2284
2285 set_except_vector(4, handle_adel);
2286 set_except_vector(5, handle_ades);
2287
2288 set_except_vector(6, handle_ibe);
2289 set_except_vector(7, handle_dbe);
2290
2291 set_except_vector(8, handle_sys);
2292 set_except_vector(9, handle_bp);
2293 set_except_vector(10, rdhwr_noopt ? handle_ri :
2294 (cpu_has_vtag_icache ?
2295 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2296 set_except_vector(11, handle_cpu);
2297 set_except_vector(12, handle_ov);
2298 set_except_vector(13, handle_tr);
2299 set_except_vector(14, handle_msa_fpe);
2300
2301 if (current_cpu_type() == CPU_R6000 ||
2302 current_cpu_type() == CPU_R6000A) {
2303 /*
2304 * The R6000 is the only R-series CPU that features a machine
2305 * check exception (similar to the R4000 cache error) and
2306 * unaligned ldc1/sdc1 exception. The handlers have not been
2307 * written yet. Well, anyway there is no R6000 machine on the
2308 * current list of targets for Linux/MIPS.
2309 * (Duh, crap, there is someone with a triple R6k machine)
2310 */
2311 //set_except_vector(14, handle_mc);
2312 //set_except_vector(15, handle_ndc);
2313 }
2314
2315
2316 if (board_nmi_handler_setup)
2317 board_nmi_handler_setup();
2318
2319 if (cpu_has_fpu && !cpu_has_nofpuex)
2320 set_except_vector(15, handle_fpe);
2321
2322 set_except_vector(16, handle_ftlb);
2323
2324 if (cpu_has_rixiex) {
2325 set_except_vector(19, tlb_do_page_fault_0);
2326 set_except_vector(20, tlb_do_page_fault_0);
2327 }
2328
2329 set_except_vector(21, handle_msa);
2330 set_except_vector(22, handle_mdmx);
2331
2332 if (cpu_has_mcheck)
2333 set_except_vector(24, handle_mcheck);
2334
2335 if (cpu_has_mipsmt)
2336 set_except_vector(25, handle_mt);
2337
2338 set_except_vector(26, handle_dsp);
2339
2340 if (board_cache_error_setup)
2341 board_cache_error_setup();
2342
2343 if (cpu_has_vce)
2344 /* Special exception: R4[04]00 uses also the divec space. */
2345 set_handler(0x180, &except_vec3_r4000, 0x100);
2346 else if (cpu_has_4kex)
2347 set_handler(0x180, &except_vec3_generic, 0x80);
2348 else
2349 set_handler(0x080, &except_vec3_generic, 0x80);
2350
2351 local_flush_icache_range(ebase, ebase + 0x400);
2352
2353 sort_extable(__start___dbe_table, __stop___dbe_table);
2354
2355 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2356 }
2357
trap_pm_notifier(struct notifier_block * self,unsigned long cmd,void * v)2358 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2359 void *v)
2360 {
2361 switch (cmd) {
2362 case CPU_PM_ENTER_FAILED:
2363 case CPU_PM_EXIT:
2364 configure_status();
2365 configure_hwrena();
2366 configure_exception_vector();
2367
2368 /* Restore register with CPU number for TLB handlers */
2369 TLBMISS_HANDLER_RESTORE();
2370
2371 break;
2372 }
2373
2374 return NOTIFY_OK;
2375 }
2376
2377 static struct notifier_block trap_pm_notifier_block = {
2378 .notifier_call = trap_pm_notifier,
2379 };
2380
trap_pm_init(void)2381 static int __init trap_pm_init(void)
2382 {
2383 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2384 }
2385 arch_initcall(trap_pm_init);
2386