1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/firmware.h>
24
25 #include "mac.h"
26 #include "ani.h"
27 #include "eeprom.h"
28 #include "calib.h"
29 #include "reg.h"
30 #include "phy.h"
31 #include "btcoex.h"
32 #include "dynack.h"
33
34 #include "../regd.h"
35
36 #define ATHEROS_VENDOR_ID 0x168c
37
38 #define AR5416_DEVID_PCI 0x0023
39 #define AR5416_DEVID_PCIE 0x0024
40 #define AR9160_DEVID_PCI 0x0027
41 #define AR9280_DEVID_PCI 0x0029
42 #define AR9280_DEVID_PCIE 0x002a
43 #define AR9285_DEVID_PCIE 0x002b
44 #define AR2427_DEVID_PCIE 0x002c
45 #define AR9287_DEVID_PCI 0x002d
46 #define AR9287_DEVID_PCIE 0x002e
47 #define AR9300_DEVID_PCIE 0x0030
48 #define AR9300_DEVID_AR9340 0x0031
49 #define AR9300_DEVID_AR9485_PCIE 0x0032
50 #define AR9300_DEVID_AR9580 0x0033
51 #define AR9300_DEVID_AR9462 0x0034
52 #define AR9300_DEVID_AR9330 0x0035
53 #define AR9300_DEVID_QCA955X 0x0038
54 #define AR9485_DEVID_AR1111 0x0037
55 #define AR9300_DEVID_AR9565 0x0036
56 #define AR9300_DEVID_AR953X 0x003d
57
58 #define AR5416_AR9100_DEVID 0x000b
59
60 #define AR_SUBVENDOR_ID_NOG 0x0e11
61 #define AR_SUBVENDOR_ID_NEW_A 0x7065
62 #define AR5416_MAGIC 0x19641014
63
64 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
65 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
66 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
67
68 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
69
70 #define ATH_DEFAULT_NOISE_FLOOR -95
71
72 #define ATH9K_RSSI_BAD -128
73
74 #define ATH9K_NUM_CHANNELS 38
75
76 /* Register read/write primitives */
77 #define REG_WRITE(_ah, _reg, _val) \
78 (_ah)->reg_ops.write((_ah), (_val), (_reg))
79
80 #define REG_READ(_ah, _reg) \
81 (_ah)->reg_ops.read((_ah), (_reg))
82
83 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
84 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
85
86 #define REG_RMW(_ah, _reg, _set, _clr) \
87 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
88
89 #define ENABLE_REGWRITE_BUFFER(_ah) \
90 do { \
91 if ((_ah)->reg_ops.enable_write_buffer) \
92 (_ah)->reg_ops.enable_write_buffer((_ah)); \
93 } while (0)
94
95 #define REGWRITE_BUFFER_FLUSH(_ah) \
96 do { \
97 if ((_ah)->reg_ops.write_flush) \
98 (_ah)->reg_ops.write_flush((_ah)); \
99 } while (0)
100
101 #define PR_EEP(_s, _val) \
102 do { \
103 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
104 _s, (_val)); \
105 } while (0)
106
107 #define SM(_v, _f) (((_v) << _f##_S) & _f)
108 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
109 #define REG_RMW_FIELD(_a, _r, _f, _v) \
110 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
111 #define REG_READ_FIELD(_a, _r, _f) \
112 (((REG_READ(_a, _r) & _f) >> _f##_S))
113 #define REG_SET_BIT(_a, _r, _f) \
114 REG_RMW(_a, _r, (_f), 0)
115 #define REG_CLR_BIT(_a, _r, _f) \
116 REG_RMW(_a, _r, 0, (_f))
117
118 #define DO_DELAY(x) do { \
119 if (((++(x) % 64) == 0) && \
120 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
121 != ATH_USB)) \
122 udelay(1); \
123 } while (0)
124
125 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
126 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
127
128 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
129 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
130 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
131 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
132 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
133 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
134 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
139 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
140 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
141 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
142 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
143 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
144 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
145
146 #define AR_GPIOD_MASK 0x00001FFF
147 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
148
149 #define BASE_ACTIVATE_DELAY 100
150 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
151 #define COEF_SCALE_S 24
152 #define HT40_CHANNEL_CENTER_SHIFT 10
153
154 #define ATH9K_ANTENNA0_CHAINMASK 0x1
155 #define ATH9K_ANTENNA1_CHAINMASK 0x2
156
157 #define ATH9K_NUM_DMA_DEBUG_REGS 8
158 #define ATH9K_NUM_QUEUES 10
159
160 #define MAX_RATE_POWER 63
161 #define AH_WAIT_TIMEOUT 100000 /* (us) */
162 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
163 #define AH_TIME_QUANTUM 10
164 #define AR_KEYTABLE_SIZE 128
165 #define POWER_UP_TIME 10000
166 #define SPUR_RSSI_THRESH 40
167 #define UPPER_5G_SUB_BAND_START 5700
168 #define MID_5G_SUB_BAND_START 5400
169
170 #define CAB_TIMEOUT_VAL 10
171 #define BEACON_TIMEOUT_VAL 10
172 #define MIN_BEACON_TIMEOUT_VAL 1
173 #define SLEEP_SLOP TU_TO_USEC(3)
174
175 #define INIT_CONFIG_STATUS 0x00000000
176 #define INIT_RSSI_THR 0x00000700
177 #define INIT_BCON_CNTRL_REG 0x00000000
178
179 #define TU_TO_USEC(_tu) ((_tu) << 10)
180
181 #define ATH9K_HW_RX_HP_QDEPTH 16
182 #define ATH9K_HW_RX_LP_QDEPTH 128
183
184 #define PAPRD_GAIN_TABLE_ENTRIES 32
185 #define PAPRD_TABLE_SZ 24
186 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
187
188 /*
189 * Wake on Wireless
190 */
191
192 /* Keep Alive Frame */
193 #define KAL_FRAME_LEN 28
194 #define KAL_FRAME_TYPE 0x2 /* data frame */
195 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
196 #define KAL_DURATION_ID 0x3d
197 #define KAL_NUM_DATA_WORDS 6
198 #define KAL_NUM_DESC_WORDS 12
199 #define KAL_ANTENNA_MODE 1
200 #define KAL_TO_DS 1
201 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
202 #define KAL_TIMEOUT 900
203
204 #define MAX_PATTERN_SIZE 256
205 #define MAX_PATTERN_MASK_SIZE 32
206 #define MAX_NUM_PATTERN 8
207 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
208 deauthenticate packets */
209
210 /*
211 * WoW trigger mapping to hardware code
212 */
213
214 #define AH_WOW_USER_PATTERN_EN BIT(0)
215 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
216 #define AH_WOW_LINK_CHANGE BIT(2)
217 #define AH_WOW_BEACON_MISS BIT(3)
218
219 enum ath_hw_txq_subtype {
220 ATH_TXQ_AC_BK = 0,
221 ATH_TXQ_AC_BE = 1,
222 ATH_TXQ_AC_VI = 2,
223 ATH_TXQ_AC_VO = 3,
224 };
225
226 enum ath_ini_subsys {
227 ATH_INI_PRE = 0,
228 ATH_INI_CORE,
229 ATH_INI_POST,
230 ATH_INI_NUM_SPLIT,
231 };
232
233 enum ath9k_hw_caps {
234 ATH9K_HW_CAP_HT = BIT(0),
235 ATH9K_HW_CAP_RFSILENT = BIT(1),
236 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
237 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
238 ATH9K_HW_CAP_EDMA = BIT(4),
239 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
240 ATH9K_HW_CAP_LDPC = BIT(6),
241 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
242 ATH9K_HW_CAP_SGI_20 = BIT(8),
243 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
244 ATH9K_HW_CAP_2GHZ = BIT(11),
245 ATH9K_HW_CAP_5GHZ = BIT(12),
246 ATH9K_HW_CAP_APM = BIT(13),
247 ATH9K_HW_CAP_RTT = BIT(14),
248 ATH9K_HW_CAP_MCI = BIT(15),
249 ATH9K_HW_CAP_DFS = BIT(16),
250 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
251 ATH9K_HW_CAP_PAPRD = BIT(18),
252 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19),
253 ATH9K_HW_CAP_BT_ANT_DIV = BIT(20),
254 };
255
256 /*
257 * WoW device capabilities
258 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
259 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
260 * an exact user defined pattern or de-authentication/disassoc pattern.
261 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
262 * bytes of the pattern for user defined pattern, de-authentication and
263 * disassociation patterns for all types of possible frames recieved
264 * of those types.
265 */
266
267 struct ath9k_hw_capabilities {
268 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
269 u16 rts_aggr_limit;
270 u8 tx_chainmask;
271 u8 rx_chainmask;
272 u8 max_txchains;
273 u8 max_rxchains;
274 u8 num_gpio_pins;
275 u8 rx_hp_qdepth;
276 u8 rx_lp_qdepth;
277 u8 rx_status_len;
278 u8 tx_desc_len;
279 u8 txs_len;
280 };
281
282 #define AR_NO_SPUR 0x8000
283 #define AR_BASE_FREQ_2GHZ 2300
284 #define AR_BASE_FREQ_5GHZ 4900
285 #define AR_SPUR_FEEQ_BOUND_HT40 19
286 #define AR_SPUR_FEEQ_BOUND_HT20 10
287
288 enum ath9k_hw_hang_checks {
289 HW_BB_WATCHDOG = BIT(0),
290 HW_PHYRESTART_CLC_WAR = BIT(1),
291 HW_BB_RIFS_HANG = BIT(2),
292 HW_BB_DFS_HANG = BIT(3),
293 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
294 HW_MAC_HANG = BIT(5),
295 };
296
297 struct ath9k_ops_config {
298 int dma_beacon_response_time;
299 int sw_beacon_response_time;
300 u32 cwm_ignore_extcca;
301 u32 pcie_waen;
302 u8 analog_shiftreg;
303 u32 ofdm_trig_low;
304 u32 ofdm_trig_high;
305 u32 cck_trig_high;
306 u32 cck_trig_low;
307 u32 enable_paprd;
308 int serialize_regmode;
309 bool rx_intr_mitigation;
310 bool tx_intr_mitigation;
311 u8 max_txtrig_level;
312 u16 ani_poll_interval; /* ANI poll interval in ms */
313 u16 hw_hang_checks;
314 u16 rimt_first;
315 u16 rimt_last;
316
317 /* Platform specific config */
318 u32 aspm_l1_fix;
319 u32 xlna_gpio;
320 u32 ant_ctrl_comm2g_switch_enable;
321 bool xatten_margin_cfg;
322 bool alt_mingainidx;
323 bool no_pll_pwrsave;
324 bool tx_gain_buffalo;
325 };
326
327 enum ath9k_int {
328 ATH9K_INT_RX = 0x00000001,
329 ATH9K_INT_RXDESC = 0x00000002,
330 ATH9K_INT_RXHP = 0x00000001,
331 ATH9K_INT_RXLP = 0x00000002,
332 ATH9K_INT_RXNOFRM = 0x00000008,
333 ATH9K_INT_RXEOL = 0x00000010,
334 ATH9K_INT_RXORN = 0x00000020,
335 ATH9K_INT_TX = 0x00000040,
336 ATH9K_INT_TXDESC = 0x00000080,
337 ATH9K_INT_TIM_TIMER = 0x00000100,
338 ATH9K_INT_MCI = 0x00000200,
339 ATH9K_INT_BB_WATCHDOG = 0x00000400,
340 ATH9K_INT_TXURN = 0x00000800,
341 ATH9K_INT_MIB = 0x00001000,
342 ATH9K_INT_RXPHY = 0x00004000,
343 ATH9K_INT_RXKCM = 0x00008000,
344 ATH9K_INT_SWBA = 0x00010000,
345 ATH9K_INT_BMISS = 0x00040000,
346 ATH9K_INT_BNR = 0x00100000,
347 ATH9K_INT_TIM = 0x00200000,
348 ATH9K_INT_DTIM = 0x00400000,
349 ATH9K_INT_DTIMSYNC = 0x00800000,
350 ATH9K_INT_GPIO = 0x01000000,
351 ATH9K_INT_CABEND = 0x02000000,
352 ATH9K_INT_TSFOOR = 0x04000000,
353 ATH9K_INT_GENTIMER = 0x08000000,
354 ATH9K_INT_CST = 0x10000000,
355 ATH9K_INT_GTT = 0x20000000,
356 ATH9K_INT_FATAL = 0x40000000,
357 ATH9K_INT_GLOBAL = 0x80000000,
358 ATH9K_INT_BMISC = ATH9K_INT_TIM |
359 ATH9K_INT_DTIM |
360 ATH9K_INT_DTIMSYNC |
361 ATH9K_INT_TSFOOR |
362 ATH9K_INT_CABEND,
363 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
364 ATH9K_INT_RXDESC |
365 ATH9K_INT_RXEOL |
366 ATH9K_INT_RXORN |
367 ATH9K_INT_TXURN |
368 ATH9K_INT_TXDESC |
369 ATH9K_INT_MIB |
370 ATH9K_INT_RXPHY |
371 ATH9K_INT_RXKCM |
372 ATH9K_INT_SWBA |
373 ATH9K_INT_BMISS |
374 ATH9K_INT_GPIO,
375 ATH9K_INT_NOCARD = 0xffffffff
376 };
377
378 #define MAX_RTT_TABLE_ENTRY 6
379 #define MAX_IQCAL_MEASUREMENT 8
380 #define MAX_CL_TAB_ENTRY 16
381 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
382
383 enum ath9k_cal_flags {
384 RTT_DONE,
385 PAPRD_PACKET_SENT,
386 PAPRD_DONE,
387 NFCAL_PENDING,
388 NFCAL_INTF,
389 TXIQCAL_DONE,
390 TXCLCAL_DONE,
391 SW_PKDET_DONE,
392 };
393
394 struct ath9k_hw_cal_data {
395 u16 channel;
396 u16 channelFlags;
397 unsigned long cal_flags;
398 int32_t CalValid;
399 int8_t iCoff;
400 int8_t qCoff;
401 u8 caldac[2];
402 u16 small_signal_gain[AR9300_MAX_CHAINS];
403 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
404 u32 num_measures[AR9300_MAX_CHAINS];
405 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
406 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
407 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
408 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
409 };
410
411 struct ath9k_channel {
412 struct ieee80211_channel *chan;
413 u16 channel;
414 u16 channelFlags;
415 s16 noisefloor;
416 };
417
418 #define CHANNEL_5GHZ BIT(0)
419 #define CHANNEL_HALF BIT(1)
420 #define CHANNEL_QUARTER BIT(2)
421 #define CHANNEL_HT BIT(3)
422 #define CHANNEL_HT40PLUS BIT(4)
423 #define CHANNEL_HT40MINUS BIT(5)
424
425 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
426 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
427
428 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
429 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
430 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
431 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
432
433 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
434
435 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
436
437 #define IS_CHAN_HT40(_c) \
438 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
439
440 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
441 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
442
443 enum ath9k_power_mode {
444 ATH9K_PM_AWAKE = 0,
445 ATH9K_PM_FULL_SLEEP,
446 ATH9K_PM_NETWORK_SLEEP,
447 ATH9K_PM_UNDEFINED
448 };
449
450 enum ser_reg_mode {
451 SER_REG_MODE_OFF = 0,
452 SER_REG_MODE_ON = 1,
453 SER_REG_MODE_AUTO = 2,
454 };
455
456 enum ath9k_rx_qtype {
457 ATH9K_RX_QUEUE_HP,
458 ATH9K_RX_QUEUE_LP,
459 ATH9K_RX_QUEUE_MAX,
460 };
461
462 struct ath9k_beacon_state {
463 u32 bs_nexttbtt;
464 u32 bs_nextdtim;
465 u32 bs_intval;
466 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
467 u32 bs_dtimperiod;
468 u16 bs_bmissthreshold;
469 u32 bs_sleepduration;
470 u32 bs_tsfoor_threshold;
471 };
472
473 struct chan_centers {
474 u16 synth_center;
475 u16 ctl_center;
476 u16 ext_center;
477 };
478
479 enum {
480 ATH9K_RESET_POWER_ON,
481 ATH9K_RESET_WARM,
482 ATH9K_RESET_COLD,
483 };
484
485 struct ath9k_hw_version {
486 u32 magic;
487 u16 devid;
488 u16 subvendorid;
489 u32 macVersion;
490 u16 macRev;
491 u16 phyRev;
492 u16 analog5GhzRev;
493 u16 analog2GhzRev;
494 enum ath_usb_dev usbdev;
495 };
496
497 /* Generic TSF timer definitions */
498
499 #define ATH_MAX_GEN_TIMER 16
500
501 #define AR_GENTMR_BIT(_index) (1 << (_index))
502
503 struct ath_gen_timer_configuration {
504 u32 next_addr;
505 u32 period_addr;
506 u32 mode_addr;
507 u32 mode_mask;
508 };
509
510 struct ath_gen_timer {
511 void (*trigger)(void *arg);
512 void (*overflow)(void *arg);
513 void *arg;
514 u8 index;
515 };
516
517 struct ath_gen_timer_table {
518 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
519 u16 timer_mask;
520 };
521
522 struct ath_hw_antcomb_conf {
523 u8 main_lna_conf;
524 u8 alt_lna_conf;
525 u8 fast_div_bias;
526 u8 main_gaintb;
527 u8 alt_gaintb;
528 int lna1_lna2_delta;
529 int lna1_lna2_switch_delta;
530 u8 div_group;
531 };
532
533 /**
534 * struct ath_hw_radar_conf - radar detection initialization parameters
535 *
536 * @pulse_inband: threshold for checking the ratio of in-band power
537 * to total power for short radar pulses (half dB steps)
538 * @pulse_inband_step: threshold for checking an in-band power to total
539 * power ratio increase for short radar pulses (half dB steps)
540 * @pulse_height: threshold for detecting the beginning of a short
541 * radar pulse (dB step)
542 * @pulse_rssi: threshold for detecting if a short radar pulse is
543 * gone (dB step)
544 * @pulse_maxlen: maximum pulse length (0.8 us steps)
545 *
546 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
547 * @radar_inband: threshold for checking the ratio of in-band power
548 * to total power for long radar pulses (half dB steps)
549 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
550 *
551 * @ext_channel: enable extension channel radar detection
552 */
553 struct ath_hw_radar_conf {
554 unsigned int pulse_inband;
555 unsigned int pulse_inband_step;
556 unsigned int pulse_height;
557 unsigned int pulse_rssi;
558 unsigned int pulse_maxlen;
559
560 unsigned int radar_rssi;
561 unsigned int radar_inband;
562 int fir_power;
563
564 bool ext_channel;
565 };
566
567 /**
568 * struct ath_hw_private_ops - callbacks used internally by hardware code
569 *
570 * This structure contains private callbacks designed to only be used internally
571 * by the hardware core.
572 *
573 * @init_cal_settings: setup types of calibrations supported
574 * @init_cal: starts actual calibration
575 *
576 * @init_mode_gain_regs: Initialize TX/RX gain registers
577 *
578 * @rf_set_freq: change frequency
579 * @spur_mitigate_freq: spur mitigation
580 * @set_rf_regs:
581 * @compute_pll_control: compute the PLL control value to use for
582 * AR_RTC_PLL_CONTROL for a given channel
583 * @setup_calibration: set up calibration
584 * @iscal_supported: used to query if a type of calibration is supported
585 *
586 * @ani_cache_ini_regs: cache the values for ANI from the initial
587 * register settings through the register initialization.
588 */
589 struct ath_hw_private_ops {
590 void (*init_hang_checks)(struct ath_hw *ah);
591 bool (*detect_mac_hang)(struct ath_hw *ah);
592 bool (*detect_bb_hang)(struct ath_hw *ah);
593
594 /* Calibration ops */
595 void (*init_cal_settings)(struct ath_hw *ah);
596 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
597
598 void (*init_mode_gain_regs)(struct ath_hw *ah);
599 void (*setup_calibration)(struct ath_hw *ah,
600 struct ath9k_cal_list *currCal);
601
602 /* PHY ops */
603 int (*rf_set_freq)(struct ath_hw *ah,
604 struct ath9k_channel *chan);
605 void (*spur_mitigate_freq)(struct ath_hw *ah,
606 struct ath9k_channel *chan);
607 bool (*set_rf_regs)(struct ath_hw *ah,
608 struct ath9k_channel *chan,
609 u16 modesIndex);
610 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
611 void (*init_bb)(struct ath_hw *ah,
612 struct ath9k_channel *chan);
613 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
614 void (*olc_init)(struct ath_hw *ah);
615 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
616 void (*mark_phy_inactive)(struct ath_hw *ah);
617 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
618 bool (*rfbus_req)(struct ath_hw *ah);
619 void (*rfbus_done)(struct ath_hw *ah);
620 void (*restore_chainmask)(struct ath_hw *ah);
621 u32 (*compute_pll_control)(struct ath_hw *ah,
622 struct ath9k_channel *chan);
623 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
624 int param);
625 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
626 void (*set_radar_params)(struct ath_hw *ah,
627 struct ath_hw_radar_conf *conf);
628 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
629 u8 *ini_reloaded);
630
631 /* ANI */
632 void (*ani_cache_ini_regs)(struct ath_hw *ah);
633 };
634
635 /**
636 * struct ath_spec_scan - parameters for Atheros spectral scan
637 *
638 * @enabled: enable/disable spectral scan
639 * @short_repeat: controls whether the chip is in spectral scan mode
640 * for 4 usec (enabled) or 204 usec (disabled)
641 * @count: number of scan results requested. There are special meanings
642 * in some chip revisions:
643 * AR92xx: highest bit set (>=128) for endless mode
644 * (spectral scan won't stopped until explicitly disabled)
645 * AR9300 and newer: 0 for endless mode
646 * @endless: true if endless mode is intended. Otherwise, count value is
647 * corrected to the next possible value.
648 * @period: time duration between successive spectral scan entry points
649 * (period*256*Tclk). Tclk = ath_common->clockrate
650 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
651 *
652 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
653 * Typically it's 44MHz in 2/5GHz on later chips, but there's
654 * a "fast clock" check for this in 5GHz.
655 *
656 */
657 struct ath_spec_scan {
658 bool enabled;
659 bool short_repeat;
660 bool endless;
661 u8 count;
662 u8 period;
663 u8 fft_period;
664 };
665
666 /**
667 * struct ath_hw_ops - callbacks used by hardware code and driver code
668 *
669 * This structure contains callbacks designed to to be used internally by
670 * hardware code and also by the lower level driver.
671 *
672 * @config_pci_powersave:
673 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
674 *
675 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
676 * @spectral_scan_trigger: trigger a spectral scan run
677 * @spectral_scan_wait: wait for a spectral scan run to finish
678 */
679 struct ath_hw_ops {
680 void (*config_pci_powersave)(struct ath_hw *ah,
681 bool power_off);
682 void (*rx_enable)(struct ath_hw *ah);
683 void (*set_desc_link)(void *ds, u32 link);
684 bool (*calibrate)(struct ath_hw *ah,
685 struct ath9k_channel *chan,
686 u8 rxchainmask,
687 bool longcal);
688 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
689 u32 *sync_cause_p);
690 void (*set_txdesc)(struct ath_hw *ah, void *ds,
691 struct ath_tx_info *i);
692 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
693 struct ath_tx_status *ts);
694 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
695 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
696 struct ath_hw_antcomb_conf *antconf);
697 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
698 struct ath_hw_antcomb_conf *antconf);
699 void (*spectral_scan_config)(struct ath_hw *ah,
700 struct ath_spec_scan *param);
701 void (*spectral_scan_trigger)(struct ath_hw *ah);
702 void (*spectral_scan_wait)(struct ath_hw *ah);
703
704 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
705 void (*tx99_stop)(struct ath_hw *ah);
706 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
707
708 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
709 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
710 #endif
711 };
712
713 struct ath_nf_limits {
714 s16 max;
715 s16 min;
716 s16 nominal;
717 };
718
719 enum ath_cal_list {
720 TX_IQ_CAL = BIT(0),
721 TX_IQ_ON_AGC_CAL = BIT(1),
722 TX_CL_CAL = BIT(2),
723 };
724
725 /* ah_flags */
726 #define AH_USE_EEPROM 0x1
727 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
728 #define AH_FASTCC 0x4
729
730 struct ath_hw {
731 struct ath_ops reg_ops;
732
733 struct device *dev;
734 struct ieee80211_hw *hw;
735 struct ath_common common;
736 struct ath9k_hw_version hw_version;
737 struct ath9k_ops_config config;
738 struct ath9k_hw_capabilities caps;
739 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
740 struct ath9k_channel *curchan;
741
742 union {
743 struct ar5416_eeprom_def def;
744 struct ar5416_eeprom_4k map4k;
745 struct ar9287_eeprom map9287;
746 struct ar9300_eeprom ar9300_eep;
747 } eeprom;
748 const struct eeprom_ops *eep_ops;
749
750 bool sw_mgmt_crypto;
751 bool is_pciexpress;
752 bool aspm_enabled;
753 bool is_monitoring;
754 bool need_an_top2_fixup;
755 u16 tx_trig_level;
756
757 u32 nf_regs[6];
758 struct ath_nf_limits nf_2g;
759 struct ath_nf_limits nf_5g;
760 u16 rfsilent;
761 u32 rfkill_gpio;
762 u32 rfkill_polarity;
763 u32 ah_flags;
764
765 bool reset_power_on;
766 bool htc_reset_init;
767
768 enum nl80211_iftype opmode;
769 enum ath9k_power_mode power_mode;
770
771 s8 noise;
772 struct ath9k_hw_cal_data *caldata;
773 struct ath9k_pacal_info pacal_info;
774 struct ar5416Stats stats;
775 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
776
777 enum ath9k_int imask;
778 u32 imrs2_reg;
779 u32 txok_interrupt_mask;
780 u32 txerr_interrupt_mask;
781 u32 txdesc_interrupt_mask;
782 u32 txeol_interrupt_mask;
783 u32 txurn_interrupt_mask;
784 atomic_t intr_ref_cnt;
785 bool chip_fullsleep;
786 u32 modes_index;
787
788 /* Calibration */
789 u32 supp_cals;
790 struct ath9k_cal_list iq_caldata;
791 struct ath9k_cal_list adcgain_caldata;
792 struct ath9k_cal_list adcdc_caldata;
793 struct ath9k_cal_list *cal_list;
794 struct ath9k_cal_list *cal_list_last;
795 struct ath9k_cal_list *cal_list_curr;
796 #define totalPowerMeasI meas0.unsign
797 #define totalPowerMeasQ meas1.unsign
798 #define totalIqCorrMeas meas2.sign
799 #define totalAdcIOddPhase meas0.unsign
800 #define totalAdcIEvenPhase meas1.unsign
801 #define totalAdcQOddPhase meas2.unsign
802 #define totalAdcQEvenPhase meas3.unsign
803 #define totalAdcDcOffsetIOddPhase meas0.sign
804 #define totalAdcDcOffsetIEvenPhase meas1.sign
805 #define totalAdcDcOffsetQOddPhase meas2.sign
806 #define totalAdcDcOffsetQEvenPhase meas3.sign
807 union {
808 u32 unsign[AR5416_MAX_CHAINS];
809 int32_t sign[AR5416_MAX_CHAINS];
810 } meas0;
811 union {
812 u32 unsign[AR5416_MAX_CHAINS];
813 int32_t sign[AR5416_MAX_CHAINS];
814 } meas1;
815 union {
816 u32 unsign[AR5416_MAX_CHAINS];
817 int32_t sign[AR5416_MAX_CHAINS];
818 } meas2;
819 union {
820 u32 unsign[AR5416_MAX_CHAINS];
821 int32_t sign[AR5416_MAX_CHAINS];
822 } meas3;
823 u16 cal_samples;
824 u8 enabled_cals;
825
826 u32 sta_id1_defaults;
827 u32 misc_mode;
828
829 /* Private to hardware code */
830 struct ath_hw_private_ops private_ops;
831 /* Accessed by the lower level driver */
832 struct ath_hw_ops ops;
833
834 /* Used to program the radio on non single-chip devices */
835 u32 *analogBank6Data;
836
837 int coverage_class;
838 u32 slottime;
839 u32 globaltxtimeout;
840
841 /* ANI */
842 u32 aniperiod;
843 enum ath9k_ani_cmd ani_function;
844 u32 ani_skip_count;
845 struct ar5416AniState ani;
846
847 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
848 struct ath_btcoex_hw btcoex_hw;
849 #endif
850
851 u32 intr_txqs;
852 u8 txchainmask;
853 u8 rxchainmask;
854
855 struct ath_hw_radar_conf radar_conf;
856
857 u32 originalGain[22];
858 int initPDADC;
859 int PDADCdelta;
860 int led_pin;
861 u32 gpio_mask;
862 u32 gpio_val;
863
864 struct ar5416IniArray ini_dfs;
865 struct ar5416IniArray iniModes;
866 struct ar5416IniArray iniCommon;
867 struct ar5416IniArray iniBB_RfGain;
868 struct ar5416IniArray iniBank6;
869 struct ar5416IniArray iniAddac;
870 struct ar5416IniArray iniPcieSerdes;
871 struct ar5416IniArray iniPcieSerdesLowPower;
872 struct ar5416IniArray iniModesFastClock;
873 struct ar5416IniArray iniAdditional;
874 struct ar5416IniArray iniModesRxGain;
875 struct ar5416IniArray ini_modes_rx_gain_bounds;
876 struct ar5416IniArray iniModesTxGain;
877 struct ar5416IniArray iniCckfirNormal;
878 struct ar5416IniArray iniCckfirJapan2484;
879 struct ar5416IniArray iniModes_9271_ANI_reg;
880 struct ar5416IniArray ini_radio_post_sys2ant;
881 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
882 struct ar5416IniArray ini_modes_rxgain_bb_core;
883 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
884
885 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
886 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
887 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
888 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
889
890 u32 intr_gen_timer_trigger;
891 u32 intr_gen_timer_thresh;
892 struct ath_gen_timer_table hw_gen_timers;
893
894 struct ar9003_txs *ts_ring;
895 u32 ts_paddr_start;
896 u32 ts_paddr_end;
897 u16 ts_tail;
898 u16 ts_size;
899
900 u32 bb_watchdog_last_status;
901 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
902 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
903
904 unsigned int paprd_target_power;
905 unsigned int paprd_training_power;
906 unsigned int paprd_ratemask;
907 unsigned int paprd_ratemask_ht40;
908 bool paprd_table_write_done;
909 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
910 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
911 /*
912 * Store the permanent value of Reg 0x4004in WARegVal
913 * so we dont have to R/M/W. We should not be reading
914 * this register when in sleep states.
915 */
916 u32 WARegVal;
917
918 /* Enterprise mode cap */
919 u32 ent_mode;
920
921 #ifdef CONFIG_ATH9K_WOW
922 u32 wow_event_mask;
923 #endif
924 bool is_clk_25mhz;
925 int (*get_mac_revision)(void);
926 int (*external_reset)(void);
927
928 const struct firmware *eeprom_blob;
929
930 struct ath_dynack dynack;
931 };
932
933 struct ath_bus_ops {
934 enum ath_bus_type ath_bus_type;
935 void (*read_cachesize)(struct ath_common *common, int *csz);
936 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
937 void (*bt_coex_prep)(struct ath_common *common);
938 void (*aspm_init)(struct ath_common *common);
939 };
940
ath9k_hw_common(struct ath_hw * ah)941 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
942 {
943 return &ah->common;
944 }
945
ath9k_hw_regulatory(struct ath_hw * ah)946 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
947 {
948 return &(ath9k_hw_common(ah)->regulatory);
949 }
950
ath9k_hw_private_ops(struct ath_hw * ah)951 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
952 {
953 return &ah->private_ops;
954 }
955
ath9k_hw_ops(struct ath_hw * ah)956 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
957 {
958 return &ah->ops;
959 }
960
get_streams(int mask)961 static inline u8 get_streams(int mask)
962 {
963 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
964 }
965
966 /* Initialization, Detach, Reset */
967 void ath9k_hw_deinit(struct ath_hw *ah);
968 int ath9k_hw_init(struct ath_hw *ah);
969 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
970 struct ath9k_hw_cal_data *caldata, bool fastcc);
971 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
972 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
973
974 /* GPIO / RFKILL / Antennae */
975 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
976 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
977 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
978 u32 ah_signal_type);
979 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
980 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
981
982 /* General Operation */
983 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
984 int hw_delay);
985 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
986 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
987 int column, unsigned int *writecnt);
988 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
989 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
990 u8 phy, int kbps,
991 u32 frameLen, u16 rateix, bool shortPreamble);
992 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
993 struct ath9k_channel *chan,
994 struct chan_centers *centers);
995 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
996 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
997 bool ath9k_hw_phy_disable(struct ath_hw *ah);
998 bool ath9k_hw_disable(struct ath_hw *ah);
999 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1000 void ath9k_hw_setopmode(struct ath_hw *ah);
1001 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1002 void ath9k_hw_write_associd(struct ath_hw *ah);
1003 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1004 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1005 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1006 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1007 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur);
1008 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1009 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1010 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1011 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1012 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1013 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1014 const struct ath9k_beacon_state *bs);
1015 void ath9k_hw_check_nav(struct ath_hw *ah);
1016 bool ath9k_hw_check_alive(struct ath_hw *ah);
1017
1018 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1019
1020 /* Generic hw timer primitives */
1021 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1022 void (*trigger)(void *),
1023 void (*overflow)(void *),
1024 void *arg,
1025 u8 timer_index);
1026 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1027 struct ath_gen_timer *timer,
1028 u32 timer_next,
1029 u32 timer_period);
1030 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1031
1032 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1033 void ath_gen_timer_isr(struct ath_hw *hw);
1034
1035 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1036
1037 /* PHY */
1038 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1039 u32 *coef_mantissa, u32 *coef_exponent);
1040 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1041 bool test);
1042
1043 /*
1044 * Code Specific to AR5008, AR9001 or AR9002,
1045 * we stuff these here to avoid callbacks for AR9003.
1046 */
1047 int ar9002_hw_rf_claim(struct ath_hw *ah);
1048 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1049
1050 /*
1051 * Code specific to AR9003, we stuff these here to avoid callbacks
1052 * for older families
1053 */
1054 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1055 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1056 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1057 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1058 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1059 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1060 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1061 struct ath9k_hw_cal_data *caldata,
1062 int chain);
1063 int ar9003_paprd_create_curve(struct ath_hw *ah,
1064 struct ath9k_hw_cal_data *caldata, int chain);
1065 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1066 int ar9003_paprd_init_table(struct ath_hw *ah);
1067 bool ar9003_paprd_is_done(struct ath_hw *ah);
1068 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1069 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1070
1071 /* Hardware family op attach helpers */
1072 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1073 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1074 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1075
1076 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1077 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1078
1079 int ar9002_hw_attach_ops(struct ath_hw *ah);
1080 void ar9003_hw_attach_ops(struct ath_hw *ah);
1081
1082 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1083
1084 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1085 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1086
1087 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1088 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1089 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1090
1091 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1092 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1093 {
1094 return ah->btcoex_hw.enabled;
1095 }
ath9k_hw_mci_is_enabled(struct ath_hw * ah)1096 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1097 {
1098 return ah->common.btcoex_enabled &&
1099 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1100
1101 }
1102 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1103 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1104 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1105 {
1106 return ah->btcoex_hw.scheme;
1107 }
1108 #else
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1109 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1110 {
1111 return false;
1112 }
ath9k_hw_mci_is_enabled(struct ath_hw * ah)1113 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1114 {
1115 return false;
1116 }
ath9k_hw_btcoex_enable(struct ath_hw * ah)1117 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1118 {
1119 }
1120 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1121 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1122 {
1123 return ATH_BTCOEX_CFG_NONE;
1124 }
1125 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1126
1127
1128 #ifdef CONFIG_ATH9K_WOW
1129 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1130 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1131 u8 *user_mask, int pattern_count,
1132 int pattern_len);
1133 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1134 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1135 #else
ath9k_hw_wow_event_to_string(u32 wow_event)1136 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1137 {
1138 return NULL;
1139 }
ath9k_hw_wow_apply_pattern(struct ath_hw * ah,u8 * user_pattern,u8 * user_mask,int pattern_count,int pattern_len)1140 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1141 u8 *user_pattern,
1142 u8 *user_mask,
1143 int pattern_count,
1144 int pattern_len)
1145 {
1146 }
ath9k_hw_wow_wakeup(struct ath_hw * ah)1147 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1148 {
1149 return 0;
1150 }
ath9k_hw_wow_enable(struct ath_hw * ah,u32 pattern_enable)1151 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1152 {
1153 }
1154 #endif
1155
1156 #define ATH9K_CLOCK_RATE_CCK 22
1157 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1158 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1159 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1160
1161 #endif
1162