1 /*
2 * rz Core CPG Clocks
3 *
4 * Copyright (C) 2013 Ideas On Board SPRL
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/slab.h>
18
19 struct rz_cpg {
20 struct clk_onecell_data data;
21 void __iomem *reg;
22 };
23
24 #define CPG_FRQCR 0x10
25 #define CPG_FRQCR2 0x14
26
27 /* -----------------------------------------------------------------------------
28 * Initialization
29 */
30
31 static struct clk * __init
rz_cpg_register_clock(struct device_node * np,struct rz_cpg * cpg,const char * name)32 rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
33 {
34 u32 val;
35 unsigned mult;
36 static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
37
38 if (strcmp(name, "pll") == 0) {
39 /* FIXME: cpg_mode should be read from GPIO. But no GPIO support yet */
40 unsigned cpg_mode = 0; /* hardcoded to EXTAL for now */
41 const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
42
43 mult = cpg_mode ? (32 / 4) : 30;
44
45 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
46 }
47
48 /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
49 if (!cpg->reg)
50 return ERR_PTR(-ENXIO);
51
52 /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
53 * and the constraint that always g <= i. To get the rz platform started,
54 * let them run at fixed current speed and implement the details later.
55 */
56 if (strcmp(name, "i") == 0)
57 val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
58 else if (strcmp(name, "g") == 0)
59 val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
60 else
61 return ERR_PTR(-EINVAL);
62
63 mult = frqcr_tab[val];
64 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
65 }
66
rz_cpg_clocks_init(struct device_node * np)67 static void __init rz_cpg_clocks_init(struct device_node *np)
68 {
69 struct rz_cpg *cpg;
70 struct clk **clks;
71 unsigned i;
72 int num_clks;
73
74 num_clks = of_property_count_strings(np, "clock-output-names");
75 if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
76 return;
77
78 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
79 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
80 BUG_ON(!cpg || !clks);
81
82 cpg->data.clks = clks;
83 cpg->data.clk_num = num_clks;
84
85 cpg->reg = of_iomap(np, 0);
86
87 for (i = 0; i < num_clks; ++i) {
88 const char *name;
89 struct clk *clk;
90
91 of_property_read_string_index(np, "clock-output-names", i, &name);
92
93 clk = rz_cpg_register_clock(np, cpg, name);
94 if (IS_ERR(clk))
95 pr_err("%s: failed to register %s %s clock (%ld)\n",
96 __func__, np->name, name, PTR_ERR(clk));
97 else
98 cpg->data.clks[i] = clk;
99 }
100
101 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
102 }
103 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
104