1 /*
2 * Record and handle CPU attributes.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17 #include <asm/arch_timer.h>
18 #include <asm/cachetype.h>
19 #include <asm/cpu.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
22
23 #include <linux/bitops.h>
24 #include <linux/bug.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/personality.h>
28 #include <linux/preempt.h>
29 #include <linux/printk.h>
30 #include <linux/seq_file.h>
31 #include <linux/sched.h>
32 #include <linux/smp.h>
33
34 /*
35 * In case the boot CPU is hotpluggable, we record its initial state and
36 * current state separately. Certain system registers may contain different
37 * values depending on configuration at or after reset.
38 */
39 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
40 static struct cpuinfo_arm64 boot_cpu_data;
41
42 static char *icache_policy_str[] = {
43 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
44 [ICACHE_POLICY_AIVIVT] = "AIVIVT",
45 [ICACHE_POLICY_VIPT] = "VIPT",
46 [ICACHE_POLICY_PIPT] = "PIPT",
47 };
48
49 unsigned long __icache_flags;
50
51 static const char *hwcap_str[] = {
52 "fp",
53 "asimd",
54 "evtstrm",
55 "aes",
56 "pmull",
57 "sha1",
58 "sha2",
59 "crc32",
60 "atomics",
61 NULL
62 };
63
64 #ifdef CONFIG_COMPAT
65 static const char *compat_hwcap_str[] = {
66 "swp",
67 "half",
68 "thumb",
69 "26bit",
70 "fastmult",
71 "fpa",
72 "vfp",
73 "edsp",
74 "java",
75 "iwmmxt",
76 "crunch",
77 "thumbee",
78 "neon",
79 "vfpv3",
80 "vfpv3d16",
81 "tls",
82 "vfpv4",
83 "idiva",
84 "idivt",
85 "vfpd32",
86 "lpae",
87 "evtstrm",
88 NULL
89 };
90
91 static const char *compat_hwcap2_str[] = {
92 "aes",
93 "pmull",
94 "sha1",
95 "sha2",
96 "crc32",
97 NULL
98 };
99 #endif /* CONFIG_COMPAT */
100
c_show(struct seq_file * m,void * v)101 static int c_show(struct seq_file *m, void *v)
102 {
103 int i, j;
104
105 for_each_online_cpu(i) {
106 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
107 u32 midr = cpuinfo->reg_midr;
108
109 /*
110 * glibc reads /proc/cpuinfo to determine the number of
111 * online processors, looking for lines beginning with
112 * "processor". Give glibc what it expects.
113 */
114 seq_printf(m, "processor\t: %d\n", i);
115
116 /*
117 * Dump out the common processor features in a single line.
118 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
119 * rather than attempting to parse this, but there's a body of
120 * software which does already (at least for 32-bit).
121 */
122 seq_puts(m, "Features\t:");
123 if (personality(current->personality) == PER_LINUX32) {
124 #ifdef CONFIG_COMPAT
125 for (j = 0; compat_hwcap_str[j]; j++)
126 if (compat_elf_hwcap & (1 << j))
127 seq_printf(m, " %s", compat_hwcap_str[j]);
128
129 for (j = 0; compat_hwcap2_str[j]; j++)
130 if (compat_elf_hwcap2 & (1 << j))
131 seq_printf(m, " %s", compat_hwcap2_str[j]);
132 #endif /* CONFIG_COMPAT */
133 } else {
134 for (j = 0; hwcap_str[j]; j++)
135 if (elf_hwcap & (1 << j))
136 seq_printf(m, " %s", hwcap_str[j]);
137 }
138 seq_puts(m, "\n");
139
140 seq_printf(m, "CPU implementer\t: 0x%02x\n",
141 MIDR_IMPLEMENTOR(midr));
142 seq_printf(m, "CPU architecture: 8\n");
143 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
144 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
145 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
146 }
147
148 return 0;
149 }
150
c_start(struct seq_file * m,loff_t * pos)151 static void *c_start(struct seq_file *m, loff_t *pos)
152 {
153 return *pos < 1 ? (void *)1 : NULL;
154 }
155
c_next(struct seq_file * m,void * v,loff_t * pos)156 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
157 {
158 ++*pos;
159 return NULL;
160 }
161
c_stop(struct seq_file * m,void * v)162 static void c_stop(struct seq_file *m, void *v)
163 {
164 }
165
166 const struct seq_operations cpuinfo_op = {
167 .start = c_start,
168 .next = c_next,
169 .stop = c_stop,
170 .show = c_show
171 };
172
cpuinfo_detect_icache_policy(struct cpuinfo_arm64 * info)173 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
174 {
175 unsigned int cpu = smp_processor_id();
176 u32 l1ip = CTR_L1IP(info->reg_ctr);
177
178 if (l1ip != ICACHE_POLICY_PIPT) {
179 /*
180 * VIPT caches are non-aliasing if the VA always equals the PA
181 * in all bit positions that are covered by the index. This is
182 * the case if the size of a way (# of sets * line size) does
183 * not exceed PAGE_SIZE.
184 */
185 u32 waysize = icache_get_numsets() * icache_get_linesize();
186
187 if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
188 set_bit(ICACHEF_ALIASING, &__icache_flags);
189 }
190 if (l1ip == ICACHE_POLICY_AIVIVT)
191 set_bit(ICACHEF_AIVIVT, &__icache_flags);
192
193 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
194 }
195
__cpuinfo_store_cpu(struct cpuinfo_arm64 * info)196 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
197 {
198 info->reg_cntfrq = arch_timer_get_cntfrq();
199 info->reg_ctr = read_cpuid_cachetype();
200 info->reg_dczid = read_cpuid(SYS_DCZID_EL0);
201 info->reg_midr = read_cpuid_id();
202
203 info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1);
204 info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1);
205 info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1);
206 info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1);
207 info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1);
208 info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1);
209 info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1);
210 info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1);
211 info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1);
212
213 info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1);
214 info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1);
215 info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1);
216 info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1);
217 info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1);
218 info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1);
219 info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1);
220 info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1);
221 info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1);
222 info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1);
223 info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1);
224 info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1);
225 info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1);
226
227 info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1);
228 info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1);
229 info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1);
230
231 cpuinfo_detect_icache_policy(info);
232
233 check_local_cpu_errata();
234 }
235
cpuinfo_store_cpu(void)236 void cpuinfo_store_cpu(void)
237 {
238 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
239 __cpuinfo_store_cpu(info);
240 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
241 }
242
cpuinfo_store_boot_cpu(void)243 void __init cpuinfo_store_boot_cpu(void)
244 {
245 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
246 __cpuinfo_store_cpu(info);
247
248 boot_cpu_data = *info;
249 init_cpu_features(&boot_cpu_data);
250 }
251
icache_get_ccsidr(void)252 u64 __attribute_const__ icache_get_ccsidr(void)
253 {
254 u64 ccsidr;
255
256 WARN_ON(preemptible());
257
258 /* Select L1 I-cache and read its size ID register */
259 asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
260 : "=r"(ccsidr) : "r"(1L));
261 return ccsidr;
262 }
263