1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <media/cx25840.h>
23 #include <linux/firmware.h>
24 #include <misc/altera.h>
25
26 #include "cx23885.h"
27 #include "tuner-xc2028.h"
28 #include "netup-eeprom.h"
29 #include "netup-init.h"
30 #include "altera-ci.h"
31 #include "xc4000.h"
32 #include "xc5000.h"
33 #include "cx23888-ir.h"
34
35 static unsigned int netup_card_rev = 4;
36 module_param(netup_card_rev, int, 0644);
37 MODULE_PARM_DESC(netup_card_rev,
38 "NetUP Dual DVB-T/C CI card revision");
39 static unsigned int enable_885_ir;
40 module_param(enable_885_ir, int, 0644);
41 MODULE_PARM_DESC(enable_885_ir,
42 "Enable integrated IR controller for supported\n"
43 "\t\t CX2388[57] boards that are wired for it:\n"
44 "\t\t\tHVR-1250 (reported safe)\n"
45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
46 "\t\t\tTeVii S470 (reported unsafe)\n"
47 "\t\t This can cause an interrupt storm with some cards.\n"
48 "\t\t Default: 0 [Disabled]");
49
50 /* ------------------------------------------------------------------ */
51 /* board config info */
52
53 struct cx23885_board cx23885_boards[] = {
54 [CX23885_BOARD_UNKNOWN] = {
55 .name = "UNKNOWN/GENERIC",
56 /* Ensure safe default for unknown boards */
57 .clk_freq = 0,
58 .input = {{
59 .type = CX23885_VMUX_COMPOSITE1,
60 .vmux = 0,
61 }, {
62 .type = CX23885_VMUX_COMPOSITE2,
63 .vmux = 1,
64 }, {
65 .type = CX23885_VMUX_COMPOSITE3,
66 .vmux = 2,
67 }, {
68 .type = CX23885_VMUX_COMPOSITE4,
69 .vmux = 3,
70 } },
71 },
72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
73 .name = "Hauppauge WinTV-HVR1800lp",
74 .portc = CX23885_MPEG_DVB,
75 .input = {{
76 .type = CX23885_VMUX_TELEVISION,
77 .vmux = 0,
78 .gpio0 = 0xff00,
79 }, {
80 .type = CX23885_VMUX_DEBUG,
81 .vmux = 0,
82 .gpio0 = 0xff01,
83 }, {
84 .type = CX23885_VMUX_COMPOSITE1,
85 .vmux = 1,
86 .gpio0 = 0xff02,
87 }, {
88 .type = CX23885_VMUX_SVIDEO,
89 .vmux = 2,
90 .gpio0 = 0xff02,
91 } },
92 },
93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
94 .name = "Hauppauge WinTV-HVR1800",
95 .porta = CX23885_ANALOG_VIDEO,
96 .portb = CX23885_MPEG_ENCODER,
97 .portc = CX23885_MPEG_DVB,
98 .tuner_type = TUNER_PHILIPS_TDA8290,
99 .tuner_addr = 0x42, /* 0x84 >> 1 */
100 .tuner_bus = 1,
101 .input = {{
102 .type = CX23885_VMUX_TELEVISION,
103 .vmux = CX25840_VIN7_CH3 |
104 CX25840_VIN5_CH2 |
105 CX25840_VIN2_CH1,
106 .amux = CX25840_AUDIO8,
107 .gpio0 = 0,
108 }, {
109 .type = CX23885_VMUX_COMPOSITE1,
110 .vmux = CX25840_VIN7_CH3 |
111 CX25840_VIN4_CH2 |
112 CX25840_VIN6_CH1,
113 .amux = CX25840_AUDIO7,
114 .gpio0 = 0,
115 }, {
116 .type = CX23885_VMUX_SVIDEO,
117 .vmux = CX25840_VIN7_CH3 |
118 CX25840_VIN4_CH2 |
119 CX25840_VIN8_CH1 |
120 CX25840_SVIDEO_ON,
121 .amux = CX25840_AUDIO7,
122 .gpio0 = 0,
123 } },
124 },
125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
126 .name = "Hauppauge WinTV-HVR1250",
127 .porta = CX23885_ANALOG_VIDEO,
128 .portc = CX23885_MPEG_DVB,
129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
130 .tuner_type = TUNER_PHILIPS_TDA8290,
131 .tuner_addr = 0x42, /* 0x84 >> 1 */
132 .tuner_bus = 1,
133 #endif
134 .force_bff = 1,
135 .input = {{
136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
137 .type = CX23885_VMUX_TELEVISION,
138 .vmux = CX25840_VIN7_CH3 |
139 CX25840_VIN5_CH2 |
140 CX25840_VIN2_CH1,
141 .amux = CX25840_AUDIO8,
142 .gpio0 = 0xff00,
143 }, {
144 #endif
145 .type = CX23885_VMUX_COMPOSITE1,
146 .vmux = CX25840_VIN7_CH3 |
147 CX25840_VIN4_CH2 |
148 CX25840_VIN6_CH1,
149 .amux = CX25840_AUDIO7,
150 .gpio0 = 0xff02,
151 }, {
152 .type = CX23885_VMUX_SVIDEO,
153 .vmux = CX25840_VIN7_CH3 |
154 CX25840_VIN4_CH2 |
155 CX25840_VIN8_CH1 |
156 CX25840_SVIDEO_ON,
157 .amux = CX25840_AUDIO7,
158 .gpio0 = 0xff02,
159 } },
160 },
161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
162 .name = "DViCO FusionHDTV5 Express",
163 .portb = CX23885_MPEG_DVB,
164 },
165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
166 .name = "Hauppauge WinTV-HVR1500Q",
167 .portc = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
170 .name = "Hauppauge WinTV-HVR1500",
171 .porta = CX23885_ANALOG_VIDEO,
172 .portc = CX23885_MPEG_DVB,
173 .tuner_type = TUNER_XC2028,
174 .tuner_addr = 0x61, /* 0xc2 >> 1 */
175 .input = {{
176 .type = CX23885_VMUX_TELEVISION,
177 .vmux = CX25840_VIN7_CH3 |
178 CX25840_VIN5_CH2 |
179 CX25840_VIN2_CH1,
180 .gpio0 = 0,
181 }, {
182 .type = CX23885_VMUX_COMPOSITE1,
183 .vmux = CX25840_VIN7_CH3 |
184 CX25840_VIN4_CH2 |
185 CX25840_VIN6_CH1,
186 .gpio0 = 0,
187 }, {
188 .type = CX23885_VMUX_SVIDEO,
189 .vmux = CX25840_VIN7_CH3 |
190 CX25840_VIN4_CH2 |
191 CX25840_VIN8_CH1 |
192 CX25840_SVIDEO_ON,
193 .gpio0 = 0,
194 } },
195 },
196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
197 .name = "Hauppauge WinTV-HVR1200",
198 .portc = CX23885_MPEG_DVB,
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
201 .name = "Hauppauge WinTV-HVR1700",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
205 .name = "Hauppauge WinTV-HVR1400",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
209 .name = "DViCO FusionHDTV7 Dual Express",
210 .portb = CX23885_MPEG_DVB,
211 .portc = CX23885_MPEG_DVB,
212 },
213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
214 .name = "DViCO FusionHDTV DVB-T Dual Express",
215 .portb = CX23885_MPEG_DVB,
216 .portc = CX23885_MPEG_DVB,
217 },
218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
219 .name = "Leadtek Winfast PxDVR3200 H",
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
223 .name = "Leadtek Winfast PxPVR2200",
224 .porta = CX23885_ANALOG_VIDEO,
225 .tuner_type = TUNER_XC2028,
226 .tuner_addr = 0x61,
227 .tuner_bus = 1,
228 .input = {{
229 .type = CX23885_VMUX_TELEVISION,
230 .vmux = CX25840_VIN2_CH1 |
231 CX25840_VIN5_CH2,
232 .amux = CX25840_AUDIO8,
233 .gpio0 = 0x704040,
234 }, {
235 .type = CX23885_VMUX_COMPOSITE1,
236 .vmux = CX25840_COMPOSITE1,
237 .amux = CX25840_AUDIO7,
238 .gpio0 = 0x704040,
239 }, {
240 .type = CX23885_VMUX_SVIDEO,
241 .vmux = CX25840_SVIDEO_LUMA3 |
242 CX25840_SVIDEO_CHROMA4,
243 .amux = CX25840_AUDIO7,
244 .gpio0 = 0x704040,
245 }, {
246 .type = CX23885_VMUX_COMPONENT,
247 .vmux = CX25840_VIN7_CH1 |
248 CX25840_VIN6_CH2 |
249 CX25840_VIN8_CH3 |
250 CX25840_COMPONENT_ON,
251 .amux = CX25840_AUDIO7,
252 .gpio0 = 0x704040,
253 } },
254 },
255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
256 .name = "Leadtek Winfast PxDVR3200 H XC4000",
257 .porta = CX23885_ANALOG_VIDEO,
258 .portc = CX23885_MPEG_DVB,
259 .tuner_type = TUNER_XC4000,
260 .tuner_addr = 0x61,
261 .radio_type = UNSET,
262 .radio_addr = ADDR_UNSET,
263 .input = {{
264 .type = CX23885_VMUX_TELEVISION,
265 .vmux = CX25840_VIN2_CH1 |
266 CX25840_VIN5_CH2 |
267 CX25840_NONE0_CH3,
268 }, {
269 .type = CX23885_VMUX_COMPOSITE1,
270 .vmux = CX25840_COMPOSITE1,
271 }, {
272 .type = CX23885_VMUX_SVIDEO,
273 .vmux = CX25840_SVIDEO_LUMA3 |
274 CX25840_SVIDEO_CHROMA4,
275 }, {
276 .type = CX23885_VMUX_COMPONENT,
277 .vmux = CX25840_VIN7_CH1 |
278 CX25840_VIN6_CH2 |
279 CX25840_VIN8_CH3 |
280 CX25840_COMPONENT_ON,
281 } },
282 },
283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
284 .name = "Compro VideoMate E650F",
285 .portc = CX23885_MPEG_DVB,
286 },
287 [CX23885_BOARD_TBS_6920] = {
288 .name = "TurboSight TBS 6920",
289 .portb = CX23885_MPEG_DVB,
290 },
291 [CX23885_BOARD_TBS_6980] = {
292 .name = "TurboSight TBS 6980",
293 .portb = CX23885_MPEG_DVB,
294 .portc = CX23885_MPEG_DVB,
295 },
296 [CX23885_BOARD_TBS_6981] = {
297 .name = "TurboSight TBS 6981",
298 .portb = CX23885_MPEG_DVB,
299 .portc = CX23885_MPEG_DVB,
300 },
301 [CX23885_BOARD_TEVII_S470] = {
302 .name = "TeVii S470",
303 .portb = CX23885_MPEG_DVB,
304 },
305 [CX23885_BOARD_DVBWORLD_2005] = {
306 .name = "DVBWorld DVB-S2 2005",
307 .portb = CX23885_MPEG_DVB,
308 },
309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
310 .ci_type = 1,
311 .name = "NetUP Dual DVB-S2 CI",
312 .portb = CX23885_MPEG_DVB,
313 .portc = CX23885_MPEG_DVB,
314 },
315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
316 .name = "Hauppauge WinTV-HVR1270",
317 .portc = CX23885_MPEG_DVB,
318 },
319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
320 .name = "Hauppauge WinTV-HVR1275",
321 .portc = CX23885_MPEG_DVB,
322 },
323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
324 .name = "Hauppauge WinTV-HVR1255",
325 .porta = CX23885_ANALOG_VIDEO,
326 .portc = CX23885_MPEG_DVB,
327 .tuner_type = TUNER_ABSENT,
328 .tuner_addr = 0x42, /* 0x84 >> 1 */
329 .force_bff = 1,
330 .input = {{
331 .type = CX23885_VMUX_TELEVISION,
332 .vmux = CX25840_VIN7_CH3 |
333 CX25840_VIN5_CH2 |
334 CX25840_VIN2_CH1 |
335 CX25840_DIF_ON,
336 .amux = CX25840_AUDIO8,
337 }, {
338 .type = CX23885_VMUX_COMPOSITE1,
339 .vmux = CX25840_VIN7_CH3 |
340 CX25840_VIN4_CH2 |
341 CX25840_VIN6_CH1,
342 .amux = CX25840_AUDIO7,
343 }, {
344 .type = CX23885_VMUX_SVIDEO,
345 .vmux = CX25840_VIN7_CH3 |
346 CX25840_VIN4_CH2 |
347 CX25840_VIN8_CH1 |
348 CX25840_SVIDEO_ON,
349 .amux = CX25840_AUDIO7,
350 } },
351 },
352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
353 .name = "Hauppauge WinTV-HVR1255",
354 .porta = CX23885_ANALOG_VIDEO,
355 .portc = CX23885_MPEG_DVB,
356 .tuner_type = TUNER_ABSENT,
357 .tuner_addr = 0x42, /* 0x84 >> 1 */
358 .force_bff = 1,
359 .input = {{
360 .type = CX23885_VMUX_TELEVISION,
361 .vmux = CX25840_VIN7_CH3 |
362 CX25840_VIN5_CH2 |
363 CX25840_VIN2_CH1 |
364 CX25840_DIF_ON,
365 .amux = CX25840_AUDIO8,
366 }, {
367 .type = CX23885_VMUX_SVIDEO,
368 .vmux = CX25840_VIN7_CH3 |
369 CX25840_VIN4_CH2 |
370 CX25840_VIN8_CH1 |
371 CX25840_SVIDEO_ON,
372 .amux = CX25840_AUDIO7,
373 } },
374 },
375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
376 .name = "Hauppauge WinTV-HVR1210",
377 .portc = CX23885_MPEG_DVB,
378 },
379 [CX23885_BOARD_MYGICA_X8506] = {
380 .name = "Mygica X8506 DMB-TH",
381 .tuner_type = TUNER_XC5000,
382 .tuner_addr = 0x61,
383 .tuner_bus = 1,
384 .porta = CX23885_ANALOG_VIDEO,
385 .portb = CX23885_MPEG_DVB,
386 .input = {
387 {
388 .type = CX23885_VMUX_TELEVISION,
389 .vmux = CX25840_COMPOSITE2,
390 },
391 {
392 .type = CX23885_VMUX_COMPOSITE1,
393 .vmux = CX25840_COMPOSITE8,
394 },
395 {
396 .type = CX23885_VMUX_SVIDEO,
397 .vmux = CX25840_SVIDEO_LUMA3 |
398 CX25840_SVIDEO_CHROMA4,
399 },
400 {
401 .type = CX23885_VMUX_COMPONENT,
402 .vmux = CX25840_COMPONENT_ON |
403 CX25840_VIN1_CH1 |
404 CX25840_VIN6_CH2 |
405 CX25840_VIN7_CH3,
406 },
407 },
408 },
409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
410 .name = "Magic-Pro ProHDTV Extreme 2",
411 .tuner_type = TUNER_XC5000,
412 .tuner_addr = 0x61,
413 .tuner_bus = 1,
414 .porta = CX23885_ANALOG_VIDEO,
415 .portb = CX23885_MPEG_DVB,
416 .input = {
417 {
418 .type = CX23885_VMUX_TELEVISION,
419 .vmux = CX25840_COMPOSITE2,
420 },
421 {
422 .type = CX23885_VMUX_COMPOSITE1,
423 .vmux = CX25840_COMPOSITE8,
424 },
425 {
426 .type = CX23885_VMUX_SVIDEO,
427 .vmux = CX25840_SVIDEO_LUMA3 |
428 CX25840_SVIDEO_CHROMA4,
429 },
430 {
431 .type = CX23885_VMUX_COMPONENT,
432 .vmux = CX25840_COMPONENT_ON |
433 CX25840_VIN1_CH1 |
434 CX25840_VIN6_CH2 |
435 CX25840_VIN7_CH3,
436 },
437 },
438 },
439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
440 .name = "Hauppauge WinTV-HVR1850",
441 .porta = CX23885_ANALOG_VIDEO,
442 .portb = CX23885_MPEG_ENCODER,
443 .portc = CX23885_MPEG_DVB,
444 .tuner_type = TUNER_ABSENT,
445 .tuner_addr = 0x42, /* 0x84 >> 1 */
446 .force_bff = 1,
447 .input = {{
448 .type = CX23885_VMUX_TELEVISION,
449 .vmux = CX25840_VIN7_CH3 |
450 CX25840_VIN5_CH2 |
451 CX25840_VIN2_CH1 |
452 CX25840_DIF_ON,
453 .amux = CX25840_AUDIO8,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_VIN7_CH3 |
457 CX25840_VIN4_CH2 |
458 CX25840_VIN6_CH1,
459 .amux = CX25840_AUDIO7,
460 }, {
461 .type = CX23885_VMUX_SVIDEO,
462 .vmux = CX25840_VIN7_CH3 |
463 CX25840_VIN4_CH2 |
464 CX25840_VIN8_CH1 |
465 CX25840_SVIDEO_ON,
466 .amux = CX25840_AUDIO7,
467 } },
468 },
469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
470 .name = "Compro VideoMate E800",
471 .portc = CX23885_MPEG_DVB,
472 },
473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
474 .name = "Hauppauge WinTV-HVR1290",
475 .portc = CX23885_MPEG_DVB,
476 },
477 [CX23885_BOARD_MYGICA_X8558PRO] = {
478 .name = "Mygica X8558 PRO DMB-TH",
479 .portb = CX23885_MPEG_DVB,
480 .portc = CX23885_MPEG_DVB,
481 },
482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
483 .name = "LEADTEK WinFast PxTV1200",
484 .porta = CX23885_ANALOG_VIDEO,
485 .tuner_type = TUNER_XC2028,
486 .tuner_addr = 0x61,
487 .tuner_bus = 1,
488 .input = {{
489 .type = CX23885_VMUX_TELEVISION,
490 .vmux = CX25840_VIN2_CH1 |
491 CX25840_VIN5_CH2 |
492 CX25840_NONE0_CH3,
493 }, {
494 .type = CX23885_VMUX_COMPOSITE1,
495 .vmux = CX25840_COMPOSITE1,
496 }, {
497 .type = CX23885_VMUX_SVIDEO,
498 .vmux = CX25840_SVIDEO_LUMA3 |
499 CX25840_SVIDEO_CHROMA4,
500 }, {
501 .type = CX23885_VMUX_COMPONENT,
502 .vmux = CX25840_VIN7_CH1 |
503 CX25840_VIN6_CH2 |
504 CX25840_VIN8_CH3 |
505 CX25840_COMPONENT_ON,
506 } },
507 },
508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
509 .name = "GoTView X5 3D Hybrid",
510 .tuner_type = TUNER_XC5000,
511 .tuner_addr = 0x64,
512 .tuner_bus = 1,
513 .porta = CX23885_ANALOG_VIDEO,
514 .portb = CX23885_MPEG_DVB,
515 .input = {{
516 .type = CX23885_VMUX_TELEVISION,
517 .vmux = CX25840_VIN2_CH1 |
518 CX25840_VIN5_CH2,
519 .gpio0 = 0x02,
520 }, {
521 .type = CX23885_VMUX_COMPOSITE1,
522 .vmux = CX23885_VMUX_COMPOSITE1,
523 }, {
524 .type = CX23885_VMUX_SVIDEO,
525 .vmux = CX25840_SVIDEO_LUMA3 |
526 CX25840_SVIDEO_CHROMA4,
527 } },
528 },
529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
530 .ci_type = 2,
531 .name = "NetUP Dual DVB-T/C-CI RF",
532 .porta = CX23885_ANALOG_VIDEO,
533 .portb = CX23885_MPEG_DVB,
534 .portc = CX23885_MPEG_DVB,
535 .num_fds_portb = 2,
536 .num_fds_portc = 2,
537 .tuner_type = TUNER_XC5000,
538 .tuner_addr = 0x64,
539 .input = { {
540 .type = CX23885_VMUX_TELEVISION,
541 .vmux = CX25840_COMPOSITE1,
542 } },
543 },
544 [CX23885_BOARD_MPX885] = {
545 .name = "MPX-885",
546 .porta = CX23885_ANALOG_VIDEO,
547 .input = {{
548 .type = CX23885_VMUX_COMPOSITE1,
549 .vmux = CX25840_COMPOSITE1,
550 .amux = CX25840_AUDIO6,
551 .gpio0 = 0,
552 }, {
553 .type = CX23885_VMUX_COMPOSITE2,
554 .vmux = CX25840_COMPOSITE2,
555 .amux = CX25840_AUDIO6,
556 .gpio0 = 0,
557 }, {
558 .type = CX23885_VMUX_COMPOSITE3,
559 .vmux = CX25840_COMPOSITE3,
560 .amux = CX25840_AUDIO7,
561 .gpio0 = 0,
562 }, {
563 .type = CX23885_VMUX_COMPOSITE4,
564 .vmux = CX25840_COMPOSITE4,
565 .amux = CX25840_AUDIO7,
566 .gpio0 = 0,
567 } },
568 },
569 [CX23885_BOARD_MYGICA_X8507] = {
570 .name = "Mygica X8502/X8507 ISDB-T",
571 .tuner_type = TUNER_XC5000,
572 .tuner_addr = 0x61,
573 .tuner_bus = 1,
574 .porta = CX23885_ANALOG_VIDEO,
575 .portb = CX23885_MPEG_DVB,
576 .input = {
577 {
578 .type = CX23885_VMUX_TELEVISION,
579 .vmux = CX25840_COMPOSITE2,
580 .amux = CX25840_AUDIO8,
581 },
582 {
583 .type = CX23885_VMUX_COMPOSITE1,
584 .vmux = CX25840_COMPOSITE8,
585 .amux = CX25840_AUDIO7,
586 },
587 {
588 .type = CX23885_VMUX_SVIDEO,
589 .vmux = CX25840_SVIDEO_LUMA3 |
590 CX25840_SVIDEO_CHROMA4,
591 .amux = CX25840_AUDIO7,
592 },
593 {
594 .type = CX23885_VMUX_COMPONENT,
595 .vmux = CX25840_COMPONENT_ON |
596 CX25840_VIN1_CH1 |
597 CX25840_VIN6_CH2 |
598 CX25840_VIN7_CH3,
599 .amux = CX25840_AUDIO7,
600 },
601 },
602 },
603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
604 .name = "TerraTec Cinergy T PCIe Dual",
605 .portb = CX23885_MPEG_DVB,
606 .portc = CX23885_MPEG_DVB,
607 },
608 [CX23885_BOARD_TEVII_S471] = {
609 .name = "TeVii S471",
610 .portb = CX23885_MPEG_DVB,
611 },
612 [CX23885_BOARD_PROF_8000] = {
613 .name = "Prof Revolution DVB-S2 8000",
614 .portb = CX23885_MPEG_DVB,
615 },
616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
617 .name = "Hauppauge WinTV-HVR4400/HVR5500",
618 .porta = CX23885_ANALOG_VIDEO,
619 .portb = CX23885_MPEG_DVB,
620 .portc = CX23885_MPEG_DVB,
621 .tuner_type = TUNER_NXP_TDA18271,
622 .tuner_addr = 0x60, /* 0xc0 >> 1 */
623 .tuner_bus = 1,
624 },
625 [CX23885_BOARD_HAUPPAUGE_STARBURST] = {
626 .name = "Hauppauge WinTV Starburst",
627 .portb = CX23885_MPEG_DVB,
628 },
629 [CX23885_BOARD_AVERMEDIA_HC81R] = {
630 .name = "AVerTV Hybrid Express Slim HC81R",
631 .tuner_type = TUNER_XC2028,
632 .tuner_addr = 0x61, /* 0xc2 >> 1 */
633 .tuner_bus = 1,
634 .porta = CX23885_ANALOG_VIDEO,
635 .input = {{
636 .type = CX23885_VMUX_TELEVISION,
637 .vmux = CX25840_VIN2_CH1 |
638 CX25840_VIN5_CH2 |
639 CX25840_NONE0_CH3 |
640 CX25840_NONE1_CH3,
641 .amux = CX25840_AUDIO8,
642 }, {
643 .type = CX23885_VMUX_SVIDEO,
644 .vmux = CX25840_VIN8_CH1 |
645 CX25840_NONE_CH2 |
646 CX25840_VIN7_CH3 |
647 CX25840_SVIDEO_ON,
648 .amux = CX25840_AUDIO6,
649 }, {
650 .type = CX23885_VMUX_COMPONENT,
651 .vmux = CX25840_VIN1_CH1 |
652 CX25840_NONE_CH2 |
653 CX25840_NONE0_CH3 |
654 CX25840_NONE1_CH3,
655 .amux = CX25840_AUDIO6,
656 } },
657 },
658 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
659 .name = "DViCO FusionHDTV DVB-T Dual Express2",
660 .portb = CX23885_MPEG_DVB,
661 .portc = CX23885_MPEG_DVB,
662 },
663 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
664 .name = "Hauppauge ImpactVCB-e",
665 .tuner_type = TUNER_ABSENT,
666 .porta = CX23885_ANALOG_VIDEO,
667 .input = {{
668 .type = CX23885_VMUX_COMPOSITE1,
669 .vmux = CX25840_VIN7_CH3 |
670 CX25840_VIN4_CH2 |
671 CX25840_VIN6_CH1,
672 .amux = CX25840_AUDIO7,
673 }, {
674 .type = CX23885_VMUX_SVIDEO,
675 .vmux = CX25840_VIN7_CH3 |
676 CX25840_VIN4_CH2 |
677 CX25840_VIN8_CH1 |
678 CX25840_SVIDEO_ON,
679 .amux = CX25840_AUDIO7,
680 } },
681 },
682 [CX23885_BOARD_DVBSKY_T9580] = {
683 .name = "DVBSky T9580",
684 .portb = CX23885_MPEG_DVB,
685 .portc = CX23885_MPEG_DVB,
686 },
687 };
688 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
689
690 /* ------------------------------------------------------------------ */
691 /* PCI subsystem IDs */
692
693 struct cx23885_subid cx23885_subids[] = {
694 {
695 .subvendor = 0x0070,
696 .subdevice = 0x3400,
697 .card = CX23885_BOARD_UNKNOWN,
698 }, {
699 .subvendor = 0x0070,
700 .subdevice = 0x7600,
701 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
702 }, {
703 .subvendor = 0x0070,
704 .subdevice = 0x7800,
705 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
706 }, {
707 .subvendor = 0x0070,
708 .subdevice = 0x7801,
709 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
710 }, {
711 .subvendor = 0x0070,
712 .subdevice = 0x7809,
713 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
714 }, {
715 .subvendor = 0x0070,
716 .subdevice = 0x7911,
717 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
718 }, {
719 .subvendor = 0x18ac,
720 .subdevice = 0xd500,
721 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
722 }, {
723 .subvendor = 0x0070,
724 .subdevice = 0x7790,
725 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
726 }, {
727 .subvendor = 0x0070,
728 .subdevice = 0x7797,
729 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
730 }, {
731 .subvendor = 0x0070,
732 .subdevice = 0x7710,
733 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
734 }, {
735 .subvendor = 0x0070,
736 .subdevice = 0x7717,
737 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
738 }, {
739 .subvendor = 0x0070,
740 .subdevice = 0x71d1,
741 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
742 }, {
743 .subvendor = 0x0070,
744 .subdevice = 0x71d3,
745 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
746 }, {
747 .subvendor = 0x0070,
748 .subdevice = 0x8101,
749 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
750 }, {
751 .subvendor = 0x0070,
752 .subdevice = 0x8010,
753 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
754 }, {
755 .subvendor = 0x18ac,
756 .subdevice = 0xd618,
757 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
758 }, {
759 .subvendor = 0x18ac,
760 .subdevice = 0xdb78,
761 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
762 }, {
763 .subvendor = 0x107d,
764 .subdevice = 0x6681,
765 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
766 }, {
767 .subvendor = 0x107d,
768 .subdevice = 0x6f21,
769 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
770 }, {
771 .subvendor = 0x107d,
772 .subdevice = 0x6f39,
773 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
774 }, {
775 .subvendor = 0x185b,
776 .subdevice = 0xe800,
777 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
778 }, {
779 .subvendor = 0x6920,
780 .subdevice = 0x8888,
781 .card = CX23885_BOARD_TBS_6920,
782 }, {
783 .subvendor = 0x6980,
784 .subdevice = 0x8888,
785 .card = CX23885_BOARD_TBS_6980,
786 }, {
787 .subvendor = 0x6981,
788 .subdevice = 0x8888,
789 .card = CX23885_BOARD_TBS_6981,
790 }, {
791 .subvendor = 0xd470,
792 .subdevice = 0x9022,
793 .card = CX23885_BOARD_TEVII_S470,
794 }, {
795 .subvendor = 0x0001,
796 .subdevice = 0x2005,
797 .card = CX23885_BOARD_DVBWORLD_2005,
798 }, {
799 .subvendor = 0x1b55,
800 .subdevice = 0x2a2c,
801 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
802 }, {
803 .subvendor = 0x0070,
804 .subdevice = 0x2211,
805 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
806 }, {
807 .subvendor = 0x0070,
808 .subdevice = 0x2215,
809 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
810 }, {
811 .subvendor = 0x0070,
812 .subdevice = 0x221d,
813 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
814 }, {
815 .subvendor = 0x0070,
816 .subdevice = 0x2251,
817 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
818 }, {
819 .subvendor = 0x0070,
820 .subdevice = 0x2259,
821 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
822 }, {
823 .subvendor = 0x0070,
824 .subdevice = 0x2291,
825 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
826 }, {
827 .subvendor = 0x0070,
828 .subdevice = 0x2295,
829 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
830 }, {
831 .subvendor = 0x0070,
832 .subdevice = 0x2299,
833 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
834 }, {
835 .subvendor = 0x0070,
836 .subdevice = 0x229d,
837 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
838 }, {
839 .subvendor = 0x0070,
840 .subdevice = 0x22f0,
841 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
842 }, {
843 .subvendor = 0x0070,
844 .subdevice = 0x22f1,
845 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
846 }, {
847 .subvendor = 0x0070,
848 .subdevice = 0x22f2,
849 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
850 }, {
851 .subvendor = 0x0070,
852 .subdevice = 0x22f3,
853 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
854 }, {
855 .subvendor = 0x0070,
856 .subdevice = 0x22f4,
857 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
858 }, {
859 .subvendor = 0x0070,
860 .subdevice = 0x22f5,
861 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
862 }, {
863 .subvendor = 0x14f1,
864 .subdevice = 0x8651,
865 .card = CX23885_BOARD_MYGICA_X8506,
866 }, {
867 .subvendor = 0x14f1,
868 .subdevice = 0x8657,
869 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
870 }, {
871 .subvendor = 0x0070,
872 .subdevice = 0x8541,
873 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
874 }, {
875 .subvendor = 0x1858,
876 .subdevice = 0xe800,
877 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
878 }, {
879 .subvendor = 0x0070,
880 .subdevice = 0x8551,
881 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
882 }, {
883 .subvendor = 0x14f1,
884 .subdevice = 0x8578,
885 .card = CX23885_BOARD_MYGICA_X8558PRO,
886 }, {
887 .subvendor = 0x107d,
888 .subdevice = 0x6f22,
889 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
890 }, {
891 .subvendor = 0x5654,
892 .subdevice = 0x2390,
893 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
894 }, {
895 .subvendor = 0x1b55,
896 .subdevice = 0xe2e4,
897 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
898 }, {
899 .subvendor = 0x14f1,
900 .subdevice = 0x8502,
901 .card = CX23885_BOARD_MYGICA_X8507,
902 }, {
903 .subvendor = 0x153b,
904 .subdevice = 0x117e,
905 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
906 }, {
907 .subvendor = 0xd471,
908 .subdevice = 0x9022,
909 .card = CX23885_BOARD_TEVII_S471,
910 }, {
911 .subvendor = 0x8000,
912 .subdevice = 0x3034,
913 .card = CX23885_BOARD_PROF_8000,
914 }, {
915 .subvendor = 0x0070,
916 .subdevice = 0xc108,
917 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-4400 (Model 121xxx, Hybrid DVB-T/S2, IR) */
918 }, {
919 .subvendor = 0x0070,
920 .subdevice = 0xc138,
921 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
922 }, {
923 .subvendor = 0x0070,
924 .subdevice = 0xc12a,
925 .card = CX23885_BOARD_HAUPPAUGE_STARBURST, /* Hauppauge WinTV Starburst (Model 121x00, DVB-S2, IR) */
926 }, {
927 .subvendor = 0x0070,
928 .subdevice = 0xc1f8,
929 .card = CX23885_BOARD_HAUPPAUGE_HVR4400, /* Hauppauge WinTV HVR-5500 (Model 121xxx, Hybrid DVB-T/C/S2, IR) */
930 }, {
931 .subvendor = 0x1461,
932 .subdevice = 0xd939,
933 .card = CX23885_BOARD_AVERMEDIA_HC81R,
934 }, {
935 .subvendor = 0x0070,
936 .subdevice = 0x7133,
937 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
938 }, {
939 .subvendor = 0x18ac,
940 .subdevice = 0xdb98,
941 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
942 }, {
943 .subvendor = 0x4254,
944 .subdevice = 0x9580,
945 .card = CX23885_BOARD_DVBSKY_T9580,
946 },
947 };
948 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
949
cx23885_card_list(struct cx23885_dev * dev)950 void cx23885_card_list(struct cx23885_dev *dev)
951 {
952 int i;
953
954 if (0 == dev->pci->subsystem_vendor &&
955 0 == dev->pci->subsystem_device) {
956 printk(KERN_INFO
957 "%s: Board has no valid PCIe Subsystem ID and can't\n"
958 "%s: be autodetected. Pass card=<n> insmod option\n"
959 "%s: to workaround that. Redirect complaints to the\n"
960 "%s: vendor of the TV card. Best regards,\n"
961 "%s: -- tux\n",
962 dev->name, dev->name, dev->name, dev->name, dev->name);
963 } else {
964 printk(KERN_INFO
965 "%s: Your board isn't known (yet) to the driver.\n"
966 "%s: Try to pick one of the existing card configs via\n"
967 "%s: card=<n> insmod option. Updating to the latest\n"
968 "%s: version might help as well.\n",
969 dev->name, dev->name, dev->name, dev->name);
970 }
971 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
972 dev->name);
973 for (i = 0; i < cx23885_bcount; i++)
974 printk(KERN_INFO "%s: card=%d -> %s\n",
975 dev->name, i, cx23885_boards[i].name);
976 }
977
hauppauge_eeprom(struct cx23885_dev * dev,u8 * eeprom_data)978 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
979 {
980 struct tveeprom tv;
981
982 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
983 eeprom_data);
984
985 /* Make sure we support the board model */
986 switch (tv.model) {
987 case 22001:
988 /* WinTV-HVR1270 (PCIe, Retail, half height)
989 * ATSC/QAM and basic analog, IR Blast */
990 case 22009:
991 /* WinTV-HVR1210 (PCIe, Retail, half height)
992 * DVB-T and basic analog, IR Blast */
993 case 22011:
994 /* WinTV-HVR1270 (PCIe, Retail, half height)
995 * ATSC/QAM and basic analog, IR Recv */
996 case 22019:
997 /* WinTV-HVR1210 (PCIe, Retail, half height)
998 * DVB-T and basic analog, IR Recv */
999 case 22021:
1000 /* WinTV-HVR1275 (PCIe, Retail, half height)
1001 * ATSC/QAM and basic analog, IR Recv */
1002 case 22029:
1003 /* WinTV-HVR1210 (PCIe, Retail, half height)
1004 * DVB-T and basic analog, IR Recv */
1005 case 22101:
1006 /* WinTV-HVR1270 (PCIe, Retail, full height)
1007 * ATSC/QAM and basic analog, IR Blast */
1008 case 22109:
1009 /* WinTV-HVR1210 (PCIe, Retail, full height)
1010 * DVB-T and basic analog, IR Blast */
1011 case 22111:
1012 /* WinTV-HVR1270 (PCIe, Retail, full height)
1013 * ATSC/QAM and basic analog, IR Recv */
1014 case 22119:
1015 /* WinTV-HVR1210 (PCIe, Retail, full height)
1016 * DVB-T and basic analog, IR Recv */
1017 case 22121:
1018 /* WinTV-HVR1275 (PCIe, Retail, full height)
1019 * ATSC/QAM and basic analog, IR Recv */
1020 case 22129:
1021 /* WinTV-HVR1210 (PCIe, Retail, full height)
1022 * DVB-T and basic analog, IR Recv */
1023 case 71009:
1024 /* WinTV-HVR1200 (PCIe, Retail, full height)
1025 * DVB-T and basic analog */
1026 case 71100:
1027 /* WinTV-ImpactVCB-e (PCIe, Retail, half height)
1028 * Basic analog */
1029 case 71359:
1030 /* WinTV-HVR1200 (PCIe, OEM, half height)
1031 * DVB-T and basic analog */
1032 case 71439:
1033 /* WinTV-HVR1200 (PCIe, OEM, half height)
1034 * DVB-T and basic analog */
1035 case 71449:
1036 /* WinTV-HVR1200 (PCIe, OEM, full height)
1037 * DVB-T and basic analog */
1038 case 71939:
1039 /* WinTV-HVR1200 (PCIe, OEM, half height)
1040 * DVB-T and basic analog */
1041 case 71949:
1042 /* WinTV-HVR1200 (PCIe, OEM, full height)
1043 * DVB-T and basic analog */
1044 case 71959:
1045 /* WinTV-HVR1200 (PCIe, OEM, full height)
1046 * DVB-T and basic analog */
1047 case 71979:
1048 /* WinTV-HVR1200 (PCIe, OEM, half height)
1049 * DVB-T and basic analog */
1050 case 71999:
1051 /* WinTV-HVR1200 (PCIe, OEM, full height)
1052 * DVB-T and basic analog */
1053 case 76601:
1054 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1055 channel ATSC and MPEG2 HW Encoder */
1056 case 77001:
1057 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1058 and Basic analog */
1059 case 77011:
1060 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1061 and Basic analog */
1062 case 77041:
1063 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1064 and Basic analog */
1065 case 77051:
1066 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1067 and Basic analog */
1068 case 78011:
1069 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1070 Dual channel ATSC and MPEG2 HW Encoder */
1071 case 78501:
1072 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1073 Dual channel ATSC and MPEG2 HW Encoder */
1074 case 78521:
1075 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1076 Dual channel ATSC and MPEG2 HW Encoder */
1077 case 78531:
1078 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1079 Dual channel ATSC and MPEG2 HW Encoder */
1080 case 78631:
1081 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1082 Dual channel ATSC and MPEG2 HW Encoder */
1083 case 79001:
1084 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1085 ATSC and Basic analog */
1086 case 79101:
1087 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1088 ATSC and Basic analog */
1089 case 79501:
1090 /* WinTV-HVR1250 (PCIe, No IR, half height,
1091 ATSC [at least] and Basic analog) */
1092 case 79561:
1093 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1094 ATSC and Basic analog */
1095 case 79571:
1096 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1097 ATSC and Basic analog */
1098 case 79671:
1099 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1100 ATSC and Basic analog */
1101 case 80019:
1102 /* WinTV-HVR1400 (Express Card, Retail, IR,
1103 * DVB-T and Basic analog */
1104 case 81509:
1105 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1106 * DVB-T and MPEG2 HW Encoder */
1107 case 81519:
1108 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1109 * DVB-T and MPEG2 HW Encoder */
1110 break;
1111 case 85021:
1112 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1113 Dual channel ATSC and MPEG2 HW Encoder */
1114 break;
1115 case 85721:
1116 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1117 Dual channel ATSC and Basic analog */
1118 break;
1119 default:
1120 printk(KERN_WARNING "%s: warning: "
1121 "unknown hauppauge model #%d\n",
1122 dev->name, tv.model);
1123 break;
1124 }
1125
1126 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
1127 dev->name, tv.model);
1128 }
1129
1130 /* Some TBS cards require initing a chip using a bitbanged SPI attached
1131 to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1132 doesn't respond to any command. */
tbs_card_init(struct cx23885_dev * dev)1133 static void tbs_card_init(struct cx23885_dev *dev)
1134 {
1135 int i;
1136 const u8 buf[] = {
1137 0xe0, 0x06, 0x66, 0x33, 0x65,
1138 0x01, 0x17, 0x06, 0xde};
1139
1140 switch (dev->board) {
1141 case CX23885_BOARD_TBS_6980:
1142 case CX23885_BOARD_TBS_6981:
1143 cx_set(GP0_IO, 0x00070007);
1144 usleep_range(1000, 10000);
1145 cx_clear(GP0_IO, 2);
1146 usleep_range(1000, 10000);
1147 for (i = 0; i < 9 * 8; i++) {
1148 cx_clear(GP0_IO, 7);
1149 usleep_range(1000, 10000);
1150 cx_set(GP0_IO,
1151 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1152 usleep_range(1000, 10000);
1153 }
1154 cx_set(GP0_IO, 7);
1155 break;
1156 }
1157 }
1158
cx23885_tuner_callback(void * priv,int component,int command,int arg)1159 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1160 {
1161 struct cx23885_tsport *port = priv;
1162 struct cx23885_dev *dev = port->dev;
1163 u32 bitmask = 0;
1164
1165 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1166 return 0;
1167
1168 if (command != 0) {
1169 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
1170 __func__, command);
1171 return -EINVAL;
1172 }
1173
1174 switch (dev->board) {
1175 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1176 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1177 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1178 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1179 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1180 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1181 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1182 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1183 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1184 /* Tuner Reset Command */
1185 bitmask = 0x04;
1186 break;
1187 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1188 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1189 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1190 /* Two identical tuners on two different i2c buses,
1191 * we need to reset the correct gpio. */
1192 if (port->nr == 1)
1193 bitmask = 0x01;
1194 else if (port->nr == 2)
1195 bitmask = 0x04;
1196 break;
1197 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1198 /* Tuner Reset Command */
1199 bitmask = 0x02;
1200 break;
1201 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1202 altera_ci_tuner_reset(dev, port->nr);
1203 break;
1204 case CX23885_BOARD_AVERMEDIA_HC81R:
1205 /* XC3028L Reset Command */
1206 bitmask = 1 << 2;
1207 break;
1208 }
1209
1210 if (bitmask) {
1211 /* Drive the tuner into reset and back out */
1212 cx_clear(GP0_IO, bitmask);
1213 mdelay(200);
1214 cx_set(GP0_IO, bitmask);
1215 }
1216
1217 return 0;
1218 }
1219
cx23885_gpio_setup(struct cx23885_dev * dev)1220 void cx23885_gpio_setup(struct cx23885_dev *dev)
1221 {
1222 switch (dev->board) {
1223 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1224 /* GPIO-0 cx24227 demodulator reset */
1225 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1226 break;
1227 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1228 /* GPIO-0 cx24227 demodulator */
1229 /* GPIO-2 xc3028 tuner */
1230
1231 /* Put the parts into reset */
1232 cx_set(GP0_IO, 0x00050000);
1233 cx_clear(GP0_IO, 0x00000005);
1234 msleep(5);
1235
1236 /* Bring the parts out of reset */
1237 cx_set(GP0_IO, 0x00050005);
1238 break;
1239 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1240 /* GPIO-0 cx24227 demodulator reset */
1241 /* GPIO-2 xc5000 tuner reset */
1242 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1243 break;
1244 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1245 /* GPIO-0 656_CLK */
1246 /* GPIO-1 656_D0 */
1247 /* GPIO-2 8295A Reset */
1248 /* GPIO-3-10 cx23417 data0-7 */
1249 /* GPIO-11-14 cx23417 addr0-3 */
1250 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1251 /* GPIO-19 IR_RX */
1252
1253 /* CX23417 GPIO's */
1254 /* EIO15 Zilog Reset */
1255 /* EIO14 S5H1409/CX24227 Reset */
1256 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1257
1258 /* Put the demod into reset and protect the eeprom */
1259 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1260 mdelay(100);
1261
1262 /* Bring the demod and blaster out of reset */
1263 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1264 mdelay(100);
1265
1266 /* Force the TDA8295A into reset and back */
1267 cx23885_gpio_enable(dev, GPIO_2, 1);
1268 cx23885_gpio_set(dev, GPIO_2);
1269 mdelay(20);
1270 cx23885_gpio_clear(dev, GPIO_2);
1271 mdelay(20);
1272 cx23885_gpio_set(dev, GPIO_2);
1273 mdelay(20);
1274 break;
1275 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1276 /* GPIO-0 tda10048 demodulator reset */
1277 /* GPIO-2 tda18271 tuner reset */
1278
1279 /* Put the parts into reset and back */
1280 cx_set(GP0_IO, 0x00050000);
1281 mdelay(20);
1282 cx_clear(GP0_IO, 0x00000005);
1283 mdelay(20);
1284 cx_set(GP0_IO, 0x00050005);
1285 break;
1286 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1287 /* GPIO-0 TDA10048 demodulator reset */
1288 /* GPIO-2 TDA8295A Reset */
1289 /* GPIO-3-10 cx23417 data0-7 */
1290 /* GPIO-11-14 cx23417 addr0-3 */
1291 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1292
1293 /* The following GPIO's are on the interna AVCore (cx25840) */
1294 /* GPIO-19 IR_RX */
1295 /* GPIO-20 IR_TX 416/DVBT Select */
1296 /* GPIO-21 IIS DAT */
1297 /* GPIO-22 IIS WCLK */
1298 /* GPIO-23 IIS BCLK */
1299
1300 /* Put the parts into reset and back */
1301 cx_set(GP0_IO, 0x00050000);
1302 mdelay(20);
1303 cx_clear(GP0_IO, 0x00000005);
1304 mdelay(20);
1305 cx_set(GP0_IO, 0x00050005);
1306 break;
1307 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1308 /* GPIO-0 Dibcom7000p demodulator reset */
1309 /* GPIO-2 xc3028L tuner reset */
1310 /* GPIO-13 LED */
1311
1312 /* Put the parts into reset and back */
1313 cx_set(GP0_IO, 0x00050000);
1314 mdelay(20);
1315 cx_clear(GP0_IO, 0x00000005);
1316 mdelay(20);
1317 cx_set(GP0_IO, 0x00050005);
1318 break;
1319 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1320 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1321 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1322 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1323 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1324
1325 /* Put the parts into reset and back */
1326 cx_set(GP0_IO, 0x000f0000);
1327 mdelay(20);
1328 cx_clear(GP0_IO, 0x0000000f);
1329 mdelay(20);
1330 cx_set(GP0_IO, 0x000f000f);
1331 break;
1332 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1333 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1334 /* GPIO-0 portb xc3028 reset */
1335 /* GPIO-1 portb zl10353 reset */
1336 /* GPIO-2 portc xc3028 reset */
1337 /* GPIO-3 portc zl10353 reset */
1338
1339 /* Put the parts into reset and back */
1340 cx_set(GP0_IO, 0x000f0000);
1341 mdelay(20);
1342 cx_clear(GP0_IO, 0x0000000f);
1343 mdelay(20);
1344 cx_set(GP0_IO, 0x000f000f);
1345 break;
1346 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1347 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1348 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1349 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1350 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1351 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1352 /* GPIO-2 xc3028 tuner reset */
1353
1354 /* The following GPIO's are on the internal AVCore (cx25840) */
1355 /* GPIO-? zl10353 demod reset */
1356
1357 /* Put the parts into reset and back */
1358 cx_set(GP0_IO, 0x00040000);
1359 mdelay(20);
1360 cx_clear(GP0_IO, 0x00000004);
1361 mdelay(20);
1362 cx_set(GP0_IO, 0x00040004);
1363 break;
1364 case CX23885_BOARD_TBS_6920:
1365 case CX23885_BOARD_TBS_6980:
1366 case CX23885_BOARD_TBS_6981:
1367 case CX23885_BOARD_PROF_8000:
1368 cx_write(MC417_CTL, 0x00000036);
1369 cx_write(MC417_OEN, 0x00001000);
1370 cx_set(MC417_RWD, 0x00000002);
1371 mdelay(200);
1372 cx_clear(MC417_RWD, 0x00000800);
1373 mdelay(200);
1374 cx_set(MC417_RWD, 0x00000800);
1375 mdelay(200);
1376 break;
1377 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1378 /* GPIO-0 INTA from CiMax1
1379 GPIO-1 INTB from CiMax2
1380 GPIO-2 reset chips
1381 GPIO-3 to GPIO-10 data/addr for CA
1382 GPIO-11 ~CS0 to CiMax1
1383 GPIO-12 ~CS1 to CiMax2
1384 GPIO-13 ADL0 load LSB addr
1385 GPIO-14 ADL1 load MSB addr
1386 GPIO-15 ~RDY from CiMax
1387 GPIO-17 ~RD to CiMax
1388 GPIO-18 ~WR to CiMax
1389 */
1390 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1391 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1392 cx_clear(GP0_IO, 0x00030004);
1393 mdelay(100);/* reset delay */
1394 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1395 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1396 /* GPIO-15 IN as ~ACK, rest as OUT */
1397 cx_write(MC417_OEN, 0x00001000);
1398 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1399 cx_write(MC417_RWD, 0x0000c300);
1400 /* enable irq */
1401 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1402 break;
1403 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1404 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1405 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1406 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1407 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1408 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1409 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1410 /* GPIO-9 Demod reset */
1411
1412 /* Put the parts into reset and back */
1413 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1414 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1415 cx23885_gpio_clear(dev, GPIO_9);
1416 mdelay(20);
1417 cx23885_gpio_set(dev, GPIO_9);
1418 break;
1419 case CX23885_BOARD_MYGICA_X8506:
1420 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1421 case CX23885_BOARD_MYGICA_X8507:
1422 /* GPIO-0 (0)Analog / (1)Digital TV */
1423 /* GPIO-1 reset XC5000 */
1424 /* GPIO-2 demod reset */
1425 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1426 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1427 mdelay(100);
1428 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1429 mdelay(100);
1430 break;
1431 case CX23885_BOARD_MYGICA_X8558PRO:
1432 /* GPIO-0 reset first ATBM8830 */
1433 /* GPIO-1 reset second ATBM8830 */
1434 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1435 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1436 mdelay(100);
1437 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1438 mdelay(100);
1439 break;
1440 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1441 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1442 /* GPIO-0 656_CLK */
1443 /* GPIO-1 656_D0 */
1444 /* GPIO-2 Wake# */
1445 /* GPIO-3-10 cx23417 data0-7 */
1446 /* GPIO-11-14 cx23417 addr0-3 */
1447 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1448 /* GPIO-19 IR_RX */
1449 /* GPIO-20 C_IR_TX */
1450 /* GPIO-21 I2S DAT */
1451 /* GPIO-22 I2S WCLK */
1452 /* GPIO-23 I2S BCLK */
1453 /* ALT GPIO: EXP GPIO LATCH */
1454
1455 /* CX23417 GPIO's */
1456 /* GPIO-14 S5H1411/CX24228 Reset */
1457 /* GPIO-13 EEPROM write protect */
1458 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1459
1460 /* Put the demod into reset and protect the eeprom */
1461 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1462 mdelay(100);
1463
1464 /* Bring the demod out of reset */
1465 mc417_gpio_set(dev, GPIO_14);
1466 mdelay(100);
1467
1468 /* CX24228 GPIO */
1469 /* Connected to IF / Mux */
1470 break;
1471 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1472 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1473 break;
1474 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1475 /* GPIO-0 ~INT in
1476 GPIO-1 TMS out
1477 GPIO-2 ~reset chips out
1478 GPIO-3 to GPIO-10 data/addr for CA in/out
1479 GPIO-11 ~CS out
1480 GPIO-12 ADDR out
1481 GPIO-13 ~WR out
1482 GPIO-14 ~RD out
1483 GPIO-15 ~RDY in
1484 GPIO-16 TCK out
1485 GPIO-17 TDO in
1486 GPIO-18 TDI out
1487 */
1488 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1489 /* GPIO-0 as INT, reset & TMS low */
1490 cx_clear(GP0_IO, 0x00010006);
1491 mdelay(100);/* reset delay */
1492 cx_set(GP0_IO, 0x00000004); /* reset high */
1493 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1494 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1495 cx_write(MC417_OEN, 0x00005000);
1496 /* ~RD, ~WR high; ADDR low; ~CS high */
1497 cx_write(MC417_RWD, 0x00000d00);
1498 /* enable irq */
1499 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1500 break;
1501 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1502 case CX23885_BOARD_HAUPPAUGE_STARBURST:
1503 /* GPIO-8 tda10071 demod reset */
1504 /* GPIO-9 si2165 demod reset (only HVR4400/HVR5500)*/
1505
1506 /* Put the parts into reset and back */
1507 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1508
1509 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1510 mdelay(100);
1511 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1512 mdelay(100);
1513
1514 break;
1515 case CX23885_BOARD_AVERMEDIA_HC81R:
1516 cx_clear(MC417_CTL, 1);
1517 /* GPIO-0,1,2 setup direction as output */
1518 cx_set(GP0_IO, 0x00070000);
1519 mdelay(10);
1520 /* AF9013 demod reset */
1521 cx_set(GP0_IO, 0x00010001);
1522 mdelay(10);
1523 cx_clear(GP0_IO, 0x00010001);
1524 mdelay(10);
1525 cx_set(GP0_IO, 0x00010001);
1526 mdelay(10);
1527 /* demod tune? */
1528 cx_clear(GP0_IO, 0x00030003);
1529 mdelay(10);
1530 cx_set(GP0_IO, 0x00020002);
1531 mdelay(10);
1532 cx_set(GP0_IO, 0x00010001);
1533 mdelay(10);
1534 cx_clear(GP0_IO, 0x00020002);
1535 /* XC3028L tuner reset */
1536 cx_set(GP0_IO, 0x00040004);
1537 cx_clear(GP0_IO, 0x00040004);
1538 cx_set(GP0_IO, 0x00040004);
1539 mdelay(60);
1540 break;
1541 case CX23885_BOARD_DVBSKY_T9580:
1542 /* enable GPIO3-18 pins */
1543 cx_write(MC417_CTL, 0x00000037);
1544 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
1545 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
1546 mdelay(100);
1547 cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
1548 break;
1549 }
1550 }
1551
cx23885_ir_init(struct cx23885_dev * dev)1552 int cx23885_ir_init(struct cx23885_dev *dev)
1553 {
1554 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1555 {
1556 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1557 .pin = CX23885_PIN_IR_RX_GPIO19,
1558 .function = CX23885_PAD_IR_RX,
1559 .value = 0,
1560 .strength = CX25840_PIN_DRIVE_MEDIUM,
1561 }, {
1562 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1563 .pin = CX23885_PIN_IR_TX_GPIO20,
1564 .function = CX23885_PAD_IR_TX,
1565 .value = 0,
1566 .strength = CX25840_PIN_DRIVE_MEDIUM,
1567 }
1568 };
1569 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1570
1571 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1572 {
1573 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1574 .pin = CX23885_PIN_IR_RX_GPIO19,
1575 .function = CX23885_PAD_IR_RX,
1576 .value = 0,
1577 .strength = CX25840_PIN_DRIVE_MEDIUM,
1578 }
1579 };
1580 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1581
1582 struct v4l2_subdev_ir_parameters params;
1583 int ret = 0;
1584 switch (dev->board) {
1585 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1586 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1587 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1588 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1589 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1590 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1591 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1592 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1593 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1594 /* FIXME: Implement me */
1595 break;
1596 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1597 ret = cx23888_ir_probe(dev);
1598 if (ret)
1599 break;
1600 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1601 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1602 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1603 break;
1604 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1605 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1606 ret = cx23888_ir_probe(dev);
1607 if (ret)
1608 break;
1609 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1610 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1611 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1612 /*
1613 * For these boards we need to invert the Tx output via the
1614 * IR controller to have the LED off while idle
1615 */
1616 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms);
1617 params.enable = false;
1618 params.shutdown = false;
1619 params.invert_level = true;
1620 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
1621 params.shutdown = true;
1622 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms);
1623 break;
1624 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1625 case CX23885_BOARD_TEVII_S470:
1626 case CX23885_BOARD_MYGICA_X8507:
1627 case CX23885_BOARD_TBS_6980:
1628 case CX23885_BOARD_TBS_6981:
1629 if (!enable_885_ir)
1630 break;
1631 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1632 if (dev->sd_ir == NULL) {
1633 ret = -ENODEV;
1634 break;
1635 }
1636 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1637 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1638 break;
1639 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1640 if (!enable_885_ir)
1641 break;
1642 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1643 if (dev->sd_ir == NULL) {
1644 ret = -ENODEV;
1645 break;
1646 }
1647 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1648 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1649 break;
1650 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1651 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1652 request_module("ir-kbd-i2c");
1653 break;
1654 }
1655
1656 return ret;
1657 }
1658
cx23885_ir_fini(struct cx23885_dev * dev)1659 void cx23885_ir_fini(struct cx23885_dev *dev)
1660 {
1661 switch (dev->board) {
1662 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1663 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1664 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1665 cx23885_irq_remove(dev, PCI_MSK_IR);
1666 cx23888_ir_remove(dev);
1667 dev->sd_ir = NULL;
1668 break;
1669 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1670 case CX23885_BOARD_TEVII_S470:
1671 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1672 case CX23885_BOARD_MYGICA_X8507:
1673 case CX23885_BOARD_TBS_6980:
1674 case CX23885_BOARD_TBS_6981:
1675 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1676 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1677 dev->sd_ir = NULL;
1678 break;
1679 }
1680 }
1681
netup_jtag_io(void * device,int tms,int tdi,int read_tdo)1682 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1683 {
1684 int data;
1685 int tdo = 0;
1686 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1687 /*TMS*/
1688 data = ((cx_read(GP0_IO)) & (~0x00000002));
1689 data |= (tms ? 0x00020002 : 0x00020000);
1690 cx_write(GP0_IO, data);
1691
1692 /*TDI*/
1693 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1694 data |= (tdi ? 0x00008000 : 0);
1695 cx_write(MC417_RWD, data);
1696 if (read_tdo)
1697 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1698
1699 cx_write(MC417_RWD, data | 0x00002000);
1700 udelay(1);
1701 /*TCK*/
1702 cx_write(MC417_RWD, data);
1703
1704 return tdo;
1705 }
1706
cx23885_ir_pci_int_enable(struct cx23885_dev * dev)1707 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1708 {
1709 switch (dev->board) {
1710 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1711 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1712 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1713 if (dev->sd_ir)
1714 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1715 break;
1716 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1717 case CX23885_BOARD_TEVII_S470:
1718 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1719 case CX23885_BOARD_MYGICA_X8507:
1720 case CX23885_BOARD_TBS_6980:
1721 case CX23885_BOARD_TBS_6981:
1722 if (dev->sd_ir)
1723 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1724 break;
1725 }
1726 }
1727
cx23885_card_setup(struct cx23885_dev * dev)1728 void cx23885_card_setup(struct cx23885_dev *dev)
1729 {
1730 struct cx23885_tsport *ts1 = &dev->ts1;
1731 struct cx23885_tsport *ts2 = &dev->ts2;
1732
1733 static u8 eeprom[256];
1734
1735 if (dev->i2c_bus[0].i2c_rc == 0) {
1736 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1737 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1738 eeprom, sizeof(eeprom));
1739 }
1740
1741 switch (dev->board) {
1742 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1743 if (dev->i2c_bus[0].i2c_rc == 0) {
1744 if (eeprom[0x80] != 0x84)
1745 hauppauge_eeprom(dev, eeprom+0xc0);
1746 else
1747 hauppauge_eeprom(dev, eeprom+0x80);
1748 }
1749 break;
1750 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1751 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1752 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1753 if (dev->i2c_bus[0].i2c_rc == 0)
1754 hauppauge_eeprom(dev, eeprom+0x80);
1755 break;
1756 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1757 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1758 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1759 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1760 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1761 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1762 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1763 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1764 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1765 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1766 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1767 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1768 case CX23885_BOARD_HAUPPAUGE_STARBURST:
1769 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
1770 if (dev->i2c_bus[0].i2c_rc == 0)
1771 hauppauge_eeprom(dev, eeprom+0xc0);
1772 break;
1773 }
1774
1775 switch (dev->board) {
1776 case CX23885_BOARD_AVERMEDIA_HC81R:
1777 /* Defaults for VID B */
1778 ts1->gen_ctrl_val = 0x4; /* Parallel */
1779 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1780 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1781 /* Defaults for VID C */
1782 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1783 ts2->gen_ctrl_val = 0x10e;
1784 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1785 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1786 break;
1787 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1788 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1789 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1790 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1791 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1792 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1793 /* break omitted intentionally */
1794 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1795 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1796 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1797 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1798 break;
1799 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1800 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1801 /* Defaults for VID B - Analog encoder */
1802 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1803 ts1->gen_ctrl_val = 0x10e;
1804 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1805 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1806
1807 /* APB_TSVALERR_POL (active low)*/
1808 ts1->vld_misc_val = 0x2000;
1809 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1810 cx_write(0x130184, 0xc);
1811
1812 /* Defaults for VID C */
1813 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1814 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1815 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1816 break;
1817 case CX23885_BOARD_TBS_6920:
1818 ts1->gen_ctrl_val = 0x4; /* Parallel */
1819 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1820 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1821 break;
1822 case CX23885_BOARD_TEVII_S470:
1823 case CX23885_BOARD_TEVII_S471:
1824 case CX23885_BOARD_DVBWORLD_2005:
1825 case CX23885_BOARD_PROF_8000:
1826 ts1->gen_ctrl_val = 0x5; /* Parallel */
1827 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1828 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1829 break;
1830 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1831 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1832 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1833 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1834 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1835 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1836 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1837 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1838 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1839 break;
1840 case CX23885_BOARD_TBS_6980:
1841 case CX23885_BOARD_TBS_6981:
1842 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1843 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1844 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1845 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1846 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1847 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1848 tbs_card_init(dev);
1849 break;
1850 case CX23885_BOARD_MYGICA_X8506:
1851 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1852 case CX23885_BOARD_MYGICA_X8507:
1853 ts1->gen_ctrl_val = 0x5; /* Parallel */
1854 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1855 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1856 break;
1857 case CX23885_BOARD_MYGICA_X8558PRO:
1858 ts1->gen_ctrl_val = 0x5; /* Parallel */
1859 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1860 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1861 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1862 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1863 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1864 break;
1865 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1866 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1867 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1868 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1869 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1870 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1871 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1872 break;
1873 case CX23885_BOARD_HAUPPAUGE_STARBURST:
1874 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1875 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1876 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1877 break;
1878 case CX23885_BOARD_DVBSKY_T9580:
1879 ts1->gen_ctrl_val = 0x5; /* Parallel */
1880 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1881 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1882 ts2->gen_ctrl_val = 0x8; /* Serial bus */
1883 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1884 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1885 break;
1886 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1887 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1888 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1889 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1890 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1891 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1892 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1893 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
1894 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1895 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1896 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1897 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1898 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1899 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1900 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1901 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1902 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1903 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1904 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1905 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1906 default:
1907 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1908 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1909 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1910 }
1911
1912 /* Certain boards support analog, or require the avcore to be
1913 * loaded, ensure this happens.
1914 */
1915 switch (dev->board) {
1916 case CX23885_BOARD_TEVII_S470:
1917 /* Currently only enabled for the integrated IR controller */
1918 if (!enable_885_ir)
1919 break;
1920 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1921 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1922 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
1923 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1924 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1925 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1926 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1927 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1928 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1929 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1930 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1931 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1932 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1933 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1934 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1935 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1936 case CX23885_BOARD_MYGICA_X8506:
1937 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1938 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1939 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1940 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1941 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1942 case CX23885_BOARD_MPX885:
1943 case CX23885_BOARD_MYGICA_X8507:
1944 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1945 case CX23885_BOARD_AVERMEDIA_HC81R:
1946 case CX23885_BOARD_TBS_6980:
1947 case CX23885_BOARD_TBS_6981:
1948 case CX23885_BOARD_DVBSKY_T9580:
1949 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1950 &dev->i2c_bus[2].i2c_adap,
1951 "cx25840", 0x88 >> 1, NULL);
1952 if (dev->sd_cx25840) {
1953 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1954 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1955 }
1956 break;
1957 }
1958
1959 /* AUX-PLL 27MHz CLK */
1960 switch (dev->board) {
1961 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1962 netup_initialize(dev);
1963 break;
1964 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1965 int ret;
1966 const struct firmware *fw;
1967 const char *filename = "dvb-netup-altera-01.fw";
1968 char *action = "configure";
1969 static struct netup_card_info cinfo;
1970 struct altera_config netup_config = {
1971 .dev = dev,
1972 .action = action,
1973 .jtag_io = netup_jtag_io,
1974 };
1975
1976 netup_initialize(dev);
1977
1978 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1979 if (netup_card_rev)
1980 cinfo.rev = netup_card_rev;
1981
1982 switch (cinfo.rev) {
1983 case 0x4:
1984 filename = "dvb-netup-altera-04.fw";
1985 break;
1986 default:
1987 filename = "dvb-netup-altera-01.fw";
1988 break;
1989 }
1990 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1991 cinfo.rev, filename);
1992
1993 ret = request_firmware(&fw, filename, &dev->pci->dev);
1994 if (ret != 0)
1995 printk(KERN_ERR "did not find the firmware file. (%s) "
1996 "Please see linux/Documentation/dvb/ for more details "
1997 "on firmware-problems.", filename);
1998 else
1999 altera_init(&netup_config, fw);
2000
2001 release_firmware(fw);
2002 break;
2003 }
2004 }
2005 }
2006