1 /*
2 * DBAu1300 init and platform device setup.
3 *
4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/gpio.h>
10 #include <linux/gpio_keys.h>
11 #include <linux/init.h>
12 #include <linux/input.h> /* KEY_* codes */
13 #include <linux/i2c.h>
14 #include <linux/io.h>
15 #include <linux/leds.h>
16 #include <linux/ata_platform.h>
17 #include <linux/mmc/host.h>
18 #include <linux/module.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
23 #include <linux/smsc911x.h>
24 #include <linux/wm97xx.h>
25
26 #include <asm/mach-au1x00/au1000.h>
27 #include <asm/mach-au1x00/au1100_mmc.h>
28 #include <asm/mach-au1x00/au1200fb.h>
29 #include <asm/mach-au1x00/au1xxx_dbdma.h>
30 #include <asm/mach-au1x00/au1xxx_psc.h>
31 #include <asm/mach-db1x00/bcsr.h>
32 #include <asm/mach-au1x00/prom.h>
33
34 #include "platform.h"
35
36 /* FPGA (external mux) interrupt sources */
37 #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
38 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
39 #define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
40 #define DB1300_CF_INT (DB1300_FIRST_INT + 2)
41 #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
42 #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
43 #define DB1300_DC_INT (DB1300_FIRST_INT + 6)
44 #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
45 #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
46 #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
47 #define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
48 #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
49 #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
50 #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
51 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
52 #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
53 #define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
54
55 /* SMSC9210 CS */
56 #define DB1300_ETH_PHYS_ADDR 0x19000000
57 #define DB1300_ETH_PHYS_END 0x197fffff
58
59 /* ATA CS */
60 #define DB1300_IDE_PHYS_ADDR 0x18800000
61 #define DB1300_IDE_REG_SHIFT 5
62 #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
63
64 /* NAND CS */
65 #define DB1300_NAND_PHYS_ADDR 0x20000000
66 #define DB1300_NAND_PHYS_END 0x20000fff
67
68
69 static struct i2c_board_info db1300_i2c_devs[] __initdata = {
70 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
71 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
72 };
73
74 /* multifunction pins to assign to GPIO controller */
75 static int db1300_gpio_pins[] __initdata = {
76 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
77 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
78 AU1300_PIN_EXTCLK1,
79 -1, /* terminator */
80 };
81
82 /* multifunction pins to assign to device functions */
83 static int db1300_dev_pins[] __initdata = {
84 /* wake-from-str pins 0-3 */
85 AU1300_PIN_WAKE0,
86 /* external clock sources for PSC0 */
87 AU1300_PIN_EXTCLK0,
88 /* 8bit MMC interface on SD0: 6-9 */
89 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
90 AU1300_PIN_SD0DAT7,
91 /* UART1 pins: 11-18 */
92 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
93 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
94 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
95 /* UART0 pins: 19-24 */
96 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
97 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
98 /* UART2: 25-26 */
99 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
100 /* UART3: 27-28 */
101 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
102 /* LCD controller PWMs, ext pixclock: 30-31 */
103 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
104 /* SD1 interface: 32-37 */
105 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
106 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
107 /* SD2 interface: 38-43 */
108 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
109 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
110 /* PSC0/1 clocks: 44-45 */
111 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
112 /* PSCs: 46-49/50-53/54-57/58-61 */
113 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
114 AU1300_PIN_PSC0D1,
115 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
116 AU1300_PIN_PSC1D1,
117 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0,
118 AU1300_PIN_PSC2D1,
119 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
120 AU1300_PIN_PSC3D1,
121 /* PCMCIA interface: 62-70 */
122 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
123 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
124 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
125 /* camera interface H/V sync inputs: 71-72 */
126 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
127 /* PSC2/3 clocks: 73-74 */
128 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
129 -1, /* terminator */
130 };
131
db1300_gpio_config(void)132 static void __init db1300_gpio_config(void)
133 {
134 int *i;
135
136 i = &db1300_dev_pins[0];
137 while (*i != -1)
138 au1300_pinfunc_to_dev(*i++);
139
140 i = &db1300_gpio_pins[0];
141 while (*i != -1)
142 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
143
144 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
145 }
146
147 /**********************************************************************/
148
au1300_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)149 static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
150 unsigned int ctrl)
151 {
152 struct nand_chip *this = mtd->priv;
153 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
154
155 ioaddr &= 0xffffff00;
156
157 if (ctrl & NAND_CLE) {
158 ioaddr += MEM_STNAND_CMD;
159 } else if (ctrl & NAND_ALE) {
160 ioaddr += MEM_STNAND_ADDR;
161 } else {
162 /* assume we want to r/w real data by default */
163 ioaddr += MEM_STNAND_DATA;
164 }
165 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
166 if (cmd != NAND_CMD_NONE) {
167 __raw_writeb(cmd, this->IO_ADDR_W);
168 wmb();
169 }
170 }
171
au1300_nand_device_ready(struct mtd_info * mtd)172 static int au1300_nand_device_ready(struct mtd_info *mtd)
173 {
174 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
175 }
176
177 static struct mtd_partition db1300_nand_parts[] = {
178 {
179 .name = "NAND FS 0",
180 .offset = 0,
181 .size = 8 * 1024 * 1024,
182 },
183 {
184 .name = "NAND FS 1",
185 .offset = MTDPART_OFS_APPEND,
186 .size = MTDPART_SIZ_FULL
187 },
188 };
189
190 struct platform_nand_data db1300_nand_platdata = {
191 .chip = {
192 .nr_chips = 1,
193 .chip_offset = 0,
194 .nr_partitions = ARRAY_SIZE(db1300_nand_parts),
195 .partitions = db1300_nand_parts,
196 .chip_delay = 20,
197 },
198 .ctrl = {
199 .dev_ready = au1300_nand_device_ready,
200 .cmd_ctrl = au1300_nand_cmd_ctrl,
201 },
202 };
203
204 static struct resource db1300_nand_res[] = {
205 [0] = {
206 .start = DB1300_NAND_PHYS_ADDR,
207 .end = DB1300_NAND_PHYS_ADDR + 0xff,
208 .flags = IORESOURCE_MEM,
209 },
210 };
211
212 static struct platform_device db1300_nand_dev = {
213 .name = "gen_nand",
214 .num_resources = ARRAY_SIZE(db1300_nand_res),
215 .resource = db1300_nand_res,
216 .id = -1,
217 .dev = {
218 .platform_data = &db1300_nand_platdata,
219 }
220 };
221
222 /**********************************************************************/
223
224 static struct resource db1300_eth_res[] = {
225 [0] = {
226 .start = DB1300_ETH_PHYS_ADDR,
227 .end = DB1300_ETH_PHYS_END,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = DB1300_ETH_INT,
232 .end = DB1300_ETH_INT,
233 .flags = IORESOURCE_IRQ,
234 },
235 };
236
237 static struct smsc911x_platform_config db1300_eth_config = {
238 .phy_interface = PHY_INTERFACE_MODE_MII,
239 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
240 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
241 .flags = SMSC911X_USE_32BIT,
242 };
243
244 static struct platform_device db1300_eth_dev = {
245 .name = "smsc911x",
246 .id = -1,
247 .num_resources = ARRAY_SIZE(db1300_eth_res),
248 .resource = db1300_eth_res,
249 .dev = {
250 .platform_data = &db1300_eth_config,
251 },
252 };
253
254 /**********************************************************************/
255
256 static struct resource au1300_psc1_res[] = {
257 [0] = {
258 .start = AU1300_PSC1_PHYS_ADDR,
259 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff,
260 .flags = IORESOURCE_MEM,
261 },
262 [1] = {
263 .start = AU1300_PSC1_INT,
264 .end = AU1300_PSC1_INT,
265 .flags = IORESOURCE_IRQ,
266 },
267 [2] = {
268 .start = AU1300_DSCR_CMD0_PSC1_TX,
269 .end = AU1300_DSCR_CMD0_PSC1_TX,
270 .flags = IORESOURCE_DMA,
271 },
272 [3] = {
273 .start = AU1300_DSCR_CMD0_PSC1_RX,
274 .end = AU1300_DSCR_CMD0_PSC1_RX,
275 .flags = IORESOURCE_DMA,
276 },
277 };
278
279 static struct platform_device db1300_ac97_dev = {
280 .name = "au1xpsc_ac97",
281 .id = 1, /* PSC ID. match with AC97 codec ID! */
282 .num_resources = ARRAY_SIZE(au1300_psc1_res),
283 .resource = au1300_psc1_res,
284 };
285
286 /**********************************************************************/
287
288 static struct resource au1300_psc2_res[] = {
289 [0] = {
290 .start = AU1300_PSC2_PHYS_ADDR,
291 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = AU1300_PSC2_INT,
296 .end = AU1300_PSC2_INT,
297 .flags = IORESOURCE_IRQ,
298 },
299 [2] = {
300 .start = AU1300_DSCR_CMD0_PSC2_TX,
301 .end = AU1300_DSCR_CMD0_PSC2_TX,
302 .flags = IORESOURCE_DMA,
303 },
304 [3] = {
305 .start = AU1300_DSCR_CMD0_PSC2_RX,
306 .end = AU1300_DSCR_CMD0_PSC2_RX,
307 .flags = IORESOURCE_DMA,
308 },
309 };
310
311 static struct platform_device db1300_i2s_dev = {
312 .name = "au1xpsc_i2s",
313 .id = 2, /* PSC ID */
314 .num_resources = ARRAY_SIZE(au1300_psc2_res),
315 .resource = au1300_psc2_res,
316 };
317
318 /**********************************************************************/
319
320 static struct resource au1300_psc3_res[] = {
321 [0] = {
322 .start = AU1300_PSC3_PHYS_ADDR,
323 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff,
324 .flags = IORESOURCE_MEM,
325 },
326 [1] = {
327 .start = AU1300_PSC3_INT,
328 .end = AU1300_PSC3_INT,
329 .flags = IORESOURCE_IRQ,
330 },
331 [2] = {
332 .start = AU1300_DSCR_CMD0_PSC3_TX,
333 .end = AU1300_DSCR_CMD0_PSC3_TX,
334 .flags = IORESOURCE_DMA,
335 },
336 [3] = {
337 .start = AU1300_DSCR_CMD0_PSC3_RX,
338 .end = AU1300_DSCR_CMD0_PSC3_RX,
339 .flags = IORESOURCE_DMA,
340 },
341 };
342
343 static struct platform_device db1300_i2c_dev = {
344 .name = "au1xpsc_smbus",
345 .id = 0, /* bus number */
346 .num_resources = ARRAY_SIZE(au1300_psc3_res),
347 .resource = au1300_psc3_res,
348 };
349
350 /**********************************************************************/
351
352 /* proper key assignments when facing the LCD panel. For key assignments
353 * according to the schematics swap up with down and left with right.
354 * I chose to use it to emulate the arrow keys of a keyboard.
355 */
356 static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
357 {
358 .code = KEY_DOWN,
359 .gpio = AU1300_PIN_LCDPWM0,
360 .type = EV_KEY,
361 .debounce_interval = 1,
362 .active_low = 1,
363 .desc = "5waysw-down",
364 },
365 {
366 .code = KEY_UP,
367 .gpio = AU1300_PIN_PSC2SYNC1,
368 .type = EV_KEY,
369 .debounce_interval = 1,
370 .active_low = 1,
371 .desc = "5waysw-up",
372 },
373 {
374 .code = KEY_RIGHT,
375 .gpio = AU1300_PIN_WAKE3,
376 .type = EV_KEY,
377 .debounce_interval = 1,
378 .active_low = 1,
379 .desc = "5waysw-right",
380 },
381 {
382 .code = KEY_LEFT,
383 .gpio = AU1300_PIN_WAKE2,
384 .type = EV_KEY,
385 .debounce_interval = 1,
386 .active_low = 1,
387 .desc = "5waysw-left",
388 },
389 {
390 .code = KEY_ENTER,
391 .gpio = AU1300_PIN_WAKE1,
392 .type = EV_KEY,
393 .debounce_interval = 1,
394 .active_low = 1,
395 .desc = "5waysw-push",
396 },
397 };
398
399 static struct gpio_keys_platform_data db1300_5waysw_data = {
400 .buttons = db1300_5waysw_arrowkeys,
401 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys),
402 .rep = 1,
403 .name = "db1300-5wayswitch",
404 };
405
406 static struct platform_device db1300_5waysw_dev = {
407 .name = "gpio-keys",
408 .dev = {
409 .platform_data = &db1300_5waysw_data,
410 },
411 };
412
413 /**********************************************************************/
414
415 static struct pata_platform_info db1300_ide_info = {
416 .ioport_shift = DB1300_IDE_REG_SHIFT,
417 };
418
419 #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT)
420 static struct resource db1300_ide_res[] = {
421 [0] = {
422 .start = DB1300_IDE_PHYS_ADDR,
423 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
424 .flags = IORESOURCE_MEM,
425 },
426 [1] = {
427 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
428 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
429 .flags = IORESOURCE_MEM,
430 },
431 [2] = {
432 .start = DB1300_IDE_INT,
433 .end = DB1300_IDE_INT,
434 .flags = IORESOURCE_IRQ,
435 },
436 };
437
438 static struct platform_device db1300_ide_dev = {
439 .dev = {
440 .platform_data = &db1300_ide_info,
441 },
442 .name = "pata_platform",
443 .resource = db1300_ide_res,
444 .num_resources = ARRAY_SIZE(db1300_ide_res),
445 };
446
447 /**********************************************************************/
448
db1300_mmc_cd(int irq,void * ptr)449 static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
450 {
451 void(*mmc_cd)(struct mmc_host *, unsigned long);
452
453 /* disable the one currently screaming. No other way to shut it up */
454 if (irq == DB1300_SD1_INSERT_INT) {
455 disable_irq_nosync(DB1300_SD1_INSERT_INT);
456 enable_irq(DB1300_SD1_EJECT_INT);
457 } else {
458 disable_irq_nosync(DB1300_SD1_EJECT_INT);
459 enable_irq(DB1300_SD1_INSERT_INT);
460 }
461
462 /* link against CONFIG_MMC=m. We can only be called once MMC core has
463 * initialized the controller, so symbol_get() should always succeed.
464 */
465 mmc_cd = symbol_get(mmc_detect_change);
466 mmc_cd(ptr, msecs_to_jiffies(500));
467 symbol_put(mmc_detect_change);
468
469 return IRQ_HANDLED;
470 }
471
db1300_mmc_card_readonly(void * mmc_host)472 static int db1300_mmc_card_readonly(void *mmc_host)
473 {
474 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
475 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
476 }
477
db1300_mmc_card_inserted(void * mmc_host)478 static int db1300_mmc_card_inserted(void *mmc_host)
479 {
480 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
481 }
482
db1300_mmc_cd_setup(void * mmc_host,int en)483 static int db1300_mmc_cd_setup(void *mmc_host, int en)
484 {
485 int ret;
486
487 if (en) {
488 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
489 "sd_insert", mmc_host);
490 if (ret)
491 goto out;
492
493 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
494 "sd_eject", mmc_host);
495 if (ret) {
496 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
497 goto out;
498 }
499
500 if (db1300_mmc_card_inserted(mmc_host))
501 enable_irq(DB1300_SD1_EJECT_INT);
502 else
503 enable_irq(DB1300_SD1_INSERT_INT);
504
505 } else {
506 free_irq(DB1300_SD1_INSERT_INT, mmc_host);
507 free_irq(DB1300_SD1_EJECT_INT, mmc_host);
508 }
509 ret = 0;
510 out:
511 return ret;
512 }
513
db1300_mmcled_set(struct led_classdev * led,enum led_brightness brightness)514 static void db1300_mmcled_set(struct led_classdev *led,
515 enum led_brightness brightness)
516 {
517 if (brightness != LED_OFF)
518 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
519 else
520 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
521 }
522
523 static struct led_classdev db1300_mmc_led = {
524 .brightness_set = db1300_mmcled_set,
525 };
526
527 struct au1xmmc_platform_data db1300_sd1_platdata = {
528 .cd_setup = db1300_mmc_cd_setup,
529 .card_inserted = db1300_mmc_card_inserted,
530 .card_readonly = db1300_mmc_card_readonly,
531 .led = &db1300_mmc_led,
532 };
533
534 static struct resource au1300_sd1_res[] = {
535 [0] = {
536 .start = AU1300_SD1_PHYS_ADDR,
537 .end = AU1300_SD1_PHYS_ADDR,
538 .flags = IORESOURCE_MEM,
539 },
540 [1] = {
541 .start = AU1300_SD1_INT,
542 .end = AU1300_SD1_INT,
543 .flags = IORESOURCE_IRQ,
544 },
545 [2] = {
546 .start = AU1300_DSCR_CMD0_SDMS_TX1,
547 .end = AU1300_DSCR_CMD0_SDMS_TX1,
548 .flags = IORESOURCE_DMA,
549 },
550 [3] = {
551 .start = AU1300_DSCR_CMD0_SDMS_RX1,
552 .end = AU1300_DSCR_CMD0_SDMS_RX1,
553 .flags = IORESOURCE_DMA,
554 },
555 };
556
557 static struct platform_device db1300_sd1_dev = {
558 .dev = {
559 .platform_data = &db1300_sd1_platdata,
560 },
561 .name = "au1xxx-mmc",
562 .id = 1,
563 .resource = au1300_sd1_res,
564 .num_resources = ARRAY_SIZE(au1300_sd1_res),
565 };
566
567 /**********************************************************************/
568
db1300_movinand_inserted(void * mmc_host)569 static int db1300_movinand_inserted(void *mmc_host)
570 {
571 return 0; /* disable for now, it doesn't work yet */
572 }
573
db1300_movinand_readonly(void * mmc_host)574 static int db1300_movinand_readonly(void *mmc_host)
575 {
576 return 0;
577 }
578
db1300_movinand_led_set(struct led_classdev * led,enum led_brightness brightness)579 static void db1300_movinand_led_set(struct led_classdev *led,
580 enum led_brightness brightness)
581 {
582 if (brightness != LED_OFF)
583 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
584 else
585 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
586 }
587
588 static struct led_classdev db1300_movinand_led = {
589 .brightness_set = db1300_movinand_led_set,
590 };
591
592 struct au1xmmc_platform_data db1300_sd0_platdata = {
593 .card_inserted = db1300_movinand_inserted,
594 .card_readonly = db1300_movinand_readonly,
595 .led = &db1300_movinand_led,
596 .mask_host_caps = MMC_CAP_NEEDS_POLL,
597 };
598
599 static struct resource au1300_sd0_res[] = {
600 [0] = {
601 .start = AU1100_SD0_PHYS_ADDR,
602 .end = AU1100_SD0_PHYS_ADDR,
603 .flags = IORESOURCE_MEM,
604 },
605 [1] = {
606 .start = AU1300_SD0_INT,
607 .end = AU1300_SD0_INT,
608 .flags = IORESOURCE_IRQ,
609 },
610 [2] = {
611 .start = AU1300_DSCR_CMD0_SDMS_TX0,
612 .end = AU1300_DSCR_CMD0_SDMS_TX0,
613 .flags = IORESOURCE_DMA,
614 },
615 [3] = {
616 .start = AU1300_DSCR_CMD0_SDMS_RX0,
617 .end = AU1300_DSCR_CMD0_SDMS_RX0,
618 .flags = IORESOURCE_DMA,
619 },
620 };
621
622 static struct platform_device db1300_sd0_dev = {
623 .dev = {
624 .platform_data = &db1300_sd0_platdata,
625 },
626 .name = "au1xxx-mmc",
627 .id = 0,
628 .resource = au1300_sd0_res,
629 .num_resources = ARRAY_SIZE(au1300_sd0_res),
630 };
631
632 /**********************************************************************/
633
634 static struct platform_device db1300_wm9715_dev = {
635 .name = "wm9712-codec",
636 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */
637 };
638
639 static struct platform_device db1300_ac97dma_dev = {
640 .name = "au1xpsc-pcm",
641 .id = 1, /* PSC ID */
642 };
643
644 static struct platform_device db1300_i2sdma_dev = {
645 .name = "au1xpsc-pcm",
646 .id = 2, /* PSC ID */
647 };
648
649 static struct platform_device db1300_sndac97_dev = {
650 .name = "db1300-ac97",
651 };
652
653 static struct platform_device db1300_sndi2s_dev = {
654 .name = "db1300-i2s",
655 };
656
657 /**********************************************************************/
658
db1300fb_panel_index(void)659 static int db1300fb_panel_index(void)
660 {
661 return 9; /* DB1300_800x480 */
662 }
663
db1300fb_panel_init(void)664 static int db1300fb_panel_init(void)
665 {
666 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
667 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
668 BCSR_BOARD_LCDBL);
669 return 0;
670 }
671
db1300fb_panel_shutdown(void)672 static int db1300fb_panel_shutdown(void)
673 {
674 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
675 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
676 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
677 return 0;
678 }
679
680 static struct au1200fb_platdata db1300fb_pd = {
681 .panel_index = db1300fb_panel_index,
682 .panel_init = db1300fb_panel_init,
683 .panel_shutdown = db1300fb_panel_shutdown,
684 };
685
686 static struct resource au1300_lcd_res[] = {
687 [0] = {
688 .start = AU1200_LCD_PHYS_ADDR,
689 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
690 .flags = IORESOURCE_MEM,
691 },
692 [1] = {
693 .start = AU1300_LCD_INT,
694 .end = AU1300_LCD_INT,
695 .flags = IORESOURCE_IRQ,
696 }
697 };
698
699 static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
700
701 static struct platform_device db1300_lcd_dev = {
702 .name = "au1200-lcd",
703 .id = 0,
704 .dev = {
705 .dma_mask = &au1300_lcd_dmamask,
706 .coherent_dma_mask = DMA_BIT_MASK(32),
707 .platform_data = &db1300fb_pd,
708 },
709 .num_resources = ARRAY_SIZE(au1300_lcd_res),
710 .resource = au1300_lcd_res,
711 };
712
713 /**********************************************************************/
714
db1300_wm97xx_irqen(struct wm97xx * wm,int enable)715 static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable)
716 {
717 if (enable)
718 enable_irq(DB1300_AC97_PEN_INT);
719 else
720 disable_irq_nosync(DB1300_AC97_PEN_INT);
721 }
722
723 static struct wm97xx_mach_ops db1300_wm97xx_ops = {
724 .irq_enable = db1300_wm97xx_irqen,
725 .irq_gpio = WM97XX_GPIO_3,
726 };
727
db1300_wm97xx_probe(struct platform_device * pdev)728 static int db1300_wm97xx_probe(struct platform_device *pdev)
729 {
730 struct wm97xx *wm = platform_get_drvdata(pdev);
731
732 /* external pendown indicator */
733 wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN,
734 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY,
735 WM97XX_GPIO_WAKE);
736
737 /* internal "virtual" pendown gpio */
738 wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT,
739 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY,
740 WM97XX_GPIO_NOWAKE);
741
742 wm->pen_irq = DB1300_AC97_PEN_INT;
743
744 return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops);
745 }
746
747 static struct platform_driver db1300_wm97xx_driver = {
748 .driver.name = "wm97xx-touch",
749 .driver.owner = THIS_MODULE,
750 .probe = db1300_wm97xx_probe,
751 };
752
753 /**********************************************************************/
754
755 static struct platform_device *db1300_dev[] __initdata = {
756 &db1300_eth_dev,
757 &db1300_i2c_dev,
758 &db1300_5waysw_dev,
759 &db1300_nand_dev,
760 &db1300_ide_dev,
761 &db1300_sd0_dev,
762 &db1300_sd1_dev,
763 &db1300_lcd_dev,
764 &db1300_ac97_dev,
765 &db1300_i2s_dev,
766 &db1300_wm9715_dev,
767 &db1300_ac97dma_dev,
768 &db1300_i2sdma_dev,
769 &db1300_sndac97_dev,
770 &db1300_sndi2s_dev,
771 };
772
db1300_dev_setup(void)773 int __init db1300_dev_setup(void)
774 {
775 int swapped, cpldirq;
776 struct clk *c;
777
778 /* setup CPLD IRQ muxer */
779 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
780 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
781 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
782
783 /* insert/eject IRQs: one always triggers so don't enable them
784 * when doing request_irq() on them. DB1200 has this bug too.
785 */
786 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
787 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
788 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
789 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
790
791 /*
792 * setup board
793 */
794 prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
795
796 i2c_register_board_info(0, db1300_i2c_devs,
797 ARRAY_SIZE(db1300_i2c_devs));
798
799 if (platform_driver_register(&db1300_wm97xx_driver))
800 pr_warn("DB1300: failed to init touch pen irq support!\n");
801
802 /* Audio PSC clock is supplied by codecs (PSC1, 2) */
803 __raw_writel(PSC_SEL_CLK_SERCLK,
804 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
805 wmb();
806 __raw_writel(PSC_SEL_CLK_SERCLK,
807 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
808 wmb();
809 /* I2C driver wants 50MHz, get as close as possible */
810 c = clk_get(NULL, "psc3_intclk");
811 if (!IS_ERR(c)) {
812 clk_set_rate(c, 50000000);
813 clk_prepare_enable(c);
814 clk_put(c);
815 }
816 __raw_writel(PSC_SEL_CLK_INTCLK,
817 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
818 wmb();
819
820 /* enable power to USB ports */
821 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
822
823 /* although it is socket #0, it uses the CPLD bits which previous boards
824 * have used for socket #1.
825 */
826 db1x_register_pcmcia_socket(
827 AU1000_PCMCIA_ATTR_PHYS_ADDR,
828 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
829 AU1000_PCMCIA_MEM_PHYS_ADDR,
830 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1,
831 AU1000_PCMCIA_IO_PHYS_ADDR,
832 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1,
833 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
834
835 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
836 db1x_register_norflash(64 << 20, 2, swapped);
837
838 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
839 }
840
841
db1300_board_setup(void)842 int __init db1300_board_setup(void)
843 {
844 unsigned short whoami;
845
846 bcsr_init(DB1300_BCSR_PHYS_ADDR,
847 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
848
849 whoami = bcsr_read(BCSR_WHOAMI);
850 if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300)
851 return -ENODEV;
852
853 db1300_gpio_config();
854
855 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
856 "BoardID %d CPLD Rev %d DaughtercardID %d\n",
857 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
858 BCSR_WHOAMI_DCID(whoami));
859
860 /* enable UARTs, YAMON only enables #2 */
861 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
862 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
863 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
864
865 return 0;
866 }
867