1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 /* Linux PRO/1000 Ethernet Driver main header file */
23
24 #ifndef _E1000_H_
25 #define _E1000_H_
26
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
31 #include <linux/io.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
43 #include "hw.h"
44
45 struct e1000_info;
46
47 #define e_dbg(format, arg...) \
48 netdev_dbg(hw->adapter->netdev, format, ## arg)
49 #define e_err(format, arg...) \
50 netdev_err(adapter->netdev, format, ## arg)
51 #define e_info(format, arg...) \
52 netdev_info(adapter->netdev, format, ## arg)
53 #define e_warn(format, arg...) \
54 netdev_warn(adapter->netdev, format, ## arg)
55 #define e_notice(format, arg...) \
56 netdev_notice(adapter->netdev, format, ## arg)
57
58 /* Interrupt modes, as used by the IntMode parameter */
59 #define E1000E_INT_MODE_LEGACY 0
60 #define E1000E_INT_MODE_MSI 1
61 #define E1000E_INT_MODE_MSIX 2
62
63 /* Tx/Rx descriptor defines */
64 #define E1000_DEFAULT_TXD 256
65 #define E1000_MAX_TXD 4096
66 #define E1000_MIN_TXD 64
67
68 #define E1000_DEFAULT_RXD 256
69 #define E1000_MAX_RXD 4096
70 #define E1000_MIN_RXD 64
71
72 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
73 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
74
75 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
76
77 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
78 /* How many Rx Buffers do we bundle into one write to the hardware ? */
79 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
80
81 #define AUTO_ALL_MODES 0
82 #define E1000_EEPROM_APME 0x0400
83
84 #define E1000_MNG_VLAN_NONE (-1)
85
86 #define DEFAULT_JUMBO 9234
87
88 /* Time to wait before putting the device into D3 if there's no link (in ms). */
89 #define LINK_TIMEOUT 100
90
91 /* Count for polling __E1000_RESET condition every 10-20msec.
92 * Experimentation has shown the reset can take approximately 210msec.
93 */
94 #define E1000_CHECK_RESET_COUNT 25
95
96 #define DEFAULT_RDTR 0
97 #define DEFAULT_RADV 8
98 #define BURST_RDTR 0x20
99 #define BURST_RADV 0x20
100
101 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
103 * WTHRESH=4, so a setting of 5 gives the most efficient bus
104 * utilization but to avoid possible Tx stalls, set it to 1
105 */
106 #define E1000_TXDCTL_DMA_BURST_ENABLE \
107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
108 E1000_TXDCTL_COUNT_DESC | \
109 (1 << 16) | /* wthresh must be +1 more than desired */\
110 (1 << 8) | /* hthresh */ \
111 0x1f) /* pthresh */
112
113 #define E1000_RXDCTL_DMA_BURST_ENABLE \
114 (0x01000000 | /* set descriptor granularity */ \
115 (4 << 16) | /* set writeback threshold */ \
116 (4 << 8) | /* set prefetch threshold */ \
117 0x20) /* set hthresh */
118
119 #define E1000_TIDV_FPD (1 << 31)
120 #define E1000_RDTR_FPD (1 << 31)
121
122 enum e1000_boards {
123 board_82571,
124 board_82572,
125 board_82573,
126 board_82574,
127 board_82583,
128 board_80003es2lan,
129 board_ich8lan,
130 board_ich9lan,
131 board_ich10lan,
132 board_pchlan,
133 board_pch2lan,
134 board_pch_lpt,
135 };
136
137 struct e1000_ps_page {
138 struct page *page;
139 u64 dma; /* must be u64 - written to hw */
140 };
141
142 /* wrappers around a pointer to a socket buffer,
143 * so a DMA handle can be stored along with the buffer
144 */
145 struct e1000_buffer {
146 dma_addr_t dma;
147 struct sk_buff *skb;
148 union {
149 /* Tx */
150 struct {
151 unsigned long time_stamp;
152 u16 length;
153 u16 next_to_watch;
154 unsigned int segs;
155 unsigned int bytecount;
156 u16 mapped_as_page;
157 };
158 /* Rx */
159 struct {
160 /* arrays of page information for packet split */
161 struct e1000_ps_page *ps_pages;
162 struct page *page;
163 };
164 };
165 };
166
167 struct e1000_ring {
168 struct e1000_adapter *adapter; /* back pointer to adapter */
169 void *desc; /* pointer to ring memory */
170 dma_addr_t dma; /* phys address of ring */
171 unsigned int size; /* length of ring in bytes */
172 unsigned int count; /* number of desc. in ring */
173
174 u16 next_to_use;
175 u16 next_to_clean;
176
177 void __iomem *head;
178 void __iomem *tail;
179
180 /* array of buffer information structs */
181 struct e1000_buffer *buffer_info;
182
183 char name[IFNAMSIZ + 5];
184 u32 ims_val;
185 u32 itr_val;
186 void __iomem *itr_register;
187 int set_itr;
188
189 struct sk_buff *rx_skb_top;
190 };
191
192 /* PHY register snapshot values */
193 struct e1000_phy_regs {
194 u16 bmcr; /* basic mode control register */
195 u16 bmsr; /* basic mode status register */
196 u16 advertise; /* auto-negotiation advertisement */
197 u16 lpa; /* link partner ability register */
198 u16 expansion; /* auto-negotiation expansion reg */
199 u16 ctrl1000; /* 1000BASE-T control register */
200 u16 stat1000; /* 1000BASE-T status register */
201 u16 estatus; /* extended status register */
202 };
203
204 /* board specific private data structure */
205 struct e1000_adapter {
206 struct timer_list watchdog_timer;
207 struct timer_list phy_info_timer;
208 struct timer_list blink_timer;
209
210 struct work_struct reset_task;
211 struct work_struct watchdog_task;
212
213 const struct e1000_info *ei;
214
215 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
216 u32 bd_number;
217 u32 rx_buffer_len;
218 u16 mng_vlan_id;
219 u16 link_speed;
220 u16 link_duplex;
221 u16 eeprom_vers;
222
223 /* track device up/down/testing state */
224 unsigned long state;
225
226 /* Interrupt Throttle Rate */
227 u32 itr;
228 u32 itr_setting;
229 u16 tx_itr;
230 u16 rx_itr;
231
232 /* Tx - one ring per active queue */
233 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
234 u32 tx_fifo_limit;
235
236 struct napi_struct napi;
237
238 unsigned int uncorr_errors; /* uncorrectable ECC errors */
239 unsigned int corr_errors; /* correctable ECC errors */
240 unsigned int restart_queue;
241 u32 txd_cmd;
242
243 bool detect_tx_hung;
244 bool tx_hang_recheck;
245 u8 tx_timeout_factor;
246
247 u32 tx_int_delay;
248 u32 tx_abs_int_delay;
249
250 unsigned int total_tx_bytes;
251 unsigned int total_tx_packets;
252 unsigned int total_rx_bytes;
253 unsigned int total_rx_packets;
254
255 /* Tx stats */
256 u64 tpt_old;
257 u64 colc_old;
258 u32 gotc;
259 u64 gotc_old;
260 u32 tx_timeout_count;
261 u32 tx_fifo_head;
262 u32 tx_head_addr;
263 u32 tx_fifo_size;
264 u32 tx_dma_failed;
265 u32 tx_hwtstamp_timeouts;
266
267 /* Rx */
268 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
269 int work_to_do) ____cacheline_aligned_in_smp;
270 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
271 gfp_t gfp);
272 struct e1000_ring *rx_ring;
273
274 u32 rx_int_delay;
275 u32 rx_abs_int_delay;
276
277 /* Rx stats */
278 u64 hw_csum_err;
279 u64 hw_csum_good;
280 u64 rx_hdr_split;
281 u32 gorc;
282 u64 gorc_old;
283 u32 alloc_rx_buff_failed;
284 u32 rx_dma_failed;
285 u32 rx_hwtstamp_cleared;
286
287 unsigned int rx_ps_pages;
288 u16 rx_ps_bsize0;
289 u32 max_frame_size;
290 u32 min_frame_size;
291
292 /* OS defined structs */
293 struct net_device *netdev;
294 struct pci_dev *pdev;
295
296 /* structs defined in e1000_hw.h */
297 struct e1000_hw hw;
298
299 spinlock_t stats64_lock; /* protects statistics counters */
300 struct e1000_hw_stats stats;
301 struct e1000_phy_info phy_info;
302 struct e1000_phy_stats phy_stats;
303
304 /* Snapshot of PHY registers */
305 struct e1000_phy_regs phy_regs;
306
307 struct e1000_ring test_tx_ring;
308 struct e1000_ring test_rx_ring;
309 u32 test_icr;
310
311 u32 msg_enable;
312 unsigned int num_vectors;
313 struct msix_entry *msix_entries;
314 int int_mode;
315 u32 eiac_mask;
316
317 u32 eeprom_wol;
318 u32 wol;
319 u32 pba;
320 u32 max_hw_frame_size;
321
322 bool fc_autoneg;
323
324 unsigned int flags;
325 unsigned int flags2;
326 struct work_struct downshift_task;
327 struct work_struct update_phy_task;
328 struct work_struct print_hang_task;
329
330 int phy_hang_count;
331
332 u16 tx_ring_count;
333 u16 rx_ring_count;
334
335 struct hwtstamp_config hwtstamp_config;
336 struct delayed_work systim_overflow_work;
337 struct sk_buff *tx_hwtstamp_skb;
338 unsigned long tx_hwtstamp_start;
339 struct work_struct tx_hwtstamp_work;
340 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
341 struct cyclecounter cc;
342 struct timecounter tc;
343 struct ptp_clock *ptp_clock;
344 struct ptp_clock_info ptp_clock_info;
345
346 u16 eee_advert;
347 };
348
349 struct e1000_info {
350 enum e1000_mac_type mac;
351 unsigned int flags;
352 unsigned int flags2;
353 u32 pba;
354 u32 max_hw_frame_size;
355 s32 (*get_variants)(struct e1000_adapter *);
356 const struct e1000_mac_operations *mac_ops;
357 const struct e1000_phy_operations *phy_ops;
358 const struct e1000_nvm_operations *nvm_ops;
359 };
360
361 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
362
363 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
364 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
365 * its resolution) is based on the contents of the TIMINCA register - it
366 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
367 * For the best accuracy, the incperiod should be as small as possible. The
368 * incvalue is scaled by a factor as large as possible (while still fitting
369 * in bits 23:0) so that relatively small clock corrections can be made.
370 *
371 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
372 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
373 * bits to count nanoseconds leaving the rest for fractional nonseconds.
374 */
375 #define INCVALUE_96MHz 125
376 #define INCVALUE_SHIFT_96MHz 17
377 #define INCPERIOD_SHIFT_96MHz 2
378 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
379
380 #define INCVALUE_25MHz 40
381 #define INCVALUE_SHIFT_25MHz 18
382 #define INCPERIOD_25MHz 1
383
384 /* Another drawback of scaling the incvalue by a large factor is the
385 * 64-bit SYSTIM register overflows more quickly. This is dealt with
386 * by simply reading the clock before it overflows.
387 *
388 * Clock ns bits Overflows after
389 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
390 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
391 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
392 */
393 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
394 #define E1000_MAX_82574_SYSTIM_REREADS 50
395 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
396
397 /* hardware capability, feature, and workaround flags */
398 #define FLAG_HAS_AMT (1 << 0)
399 #define FLAG_HAS_FLASH (1 << 1)
400 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
401 #define FLAG_HAS_WOL (1 << 3)
402 /* reserved bit4 */
403 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
404 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
405 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
406 #define FLAG_READ_ONLY_NVM (1 << 8)
407 #define FLAG_IS_ICH (1 << 9)
408 #define FLAG_HAS_MSIX (1 << 10)
409 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
410 #define FLAG_IS_QUAD_PORT_A (1 << 12)
411 #define FLAG_IS_QUAD_PORT (1 << 13)
412 #define FLAG_HAS_HW_TIMESTAMP (1 << 14)
413 #define FLAG_APME_IN_WUC (1 << 15)
414 #define FLAG_APME_IN_CTRL3 (1 << 16)
415 #define FLAG_APME_CHECK_PORT_B (1 << 17)
416 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
417 #define FLAG_NO_WAKE_UCAST (1 << 19)
418 #define FLAG_MNG_PT_ENABLED (1 << 20)
419 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
420 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
421 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
422 #define FLAG_RX_NEEDS_RESTART (1 << 24)
423 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
424 #define FLAG_SMART_POWER_DOWN (1 << 26)
425 #define FLAG_MSI_ENABLED (1 << 27)
426 /* reserved (1 << 28) */
427 #define FLAG_TSO_FORCE (1 << 29)
428 #define FLAG_RESTART_NOW (1 << 30)
429 #define FLAG_MSI_TEST_FAILED (1 << 31)
430
431 #define FLAG2_CRC_STRIPPING (1 << 0)
432 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
433 #define FLAG2_IS_DISCARDING (1 << 2)
434 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
435 #define FLAG2_HAS_PHY_STATS (1 << 4)
436 #define FLAG2_HAS_EEE (1 << 5)
437 #define FLAG2_DMA_BURST (1 << 6)
438 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
439 #define FLAG2_DISABLE_AIM (1 << 8)
440 #define FLAG2_CHECK_PHY_HANG (1 << 9)
441 #define FLAG2_NO_DISABLE_RX (1 << 10)
442 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
443 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
444 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
445
446 #define E1000_RX_DESC_PS(R, i) \
447 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
448 #define E1000_RX_DESC_EXT(R, i) \
449 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
450 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
451 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
452 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
453
454 enum e1000_state_t {
455 __E1000_TESTING,
456 __E1000_RESETTING,
457 __E1000_ACCESS_SHARED_RESOURCE,
458 __E1000_DOWN
459 };
460
461 enum latency_range {
462 lowest_latency = 0,
463 low_latency = 1,
464 bulk_latency = 2,
465 latency_invalid = 255
466 };
467
468 extern char e1000e_driver_name[];
469 extern const char e1000e_driver_version[];
470
471 void e1000e_check_options(struct e1000_adapter *adapter);
472 void e1000e_set_ethtool_ops(struct net_device *netdev);
473
474 int e1000e_up(struct e1000_adapter *adapter);
475 void e1000e_down(struct e1000_adapter *adapter, bool reset);
476 void e1000e_reinit_locked(struct e1000_adapter *adapter);
477 void e1000e_reset(struct e1000_adapter *adapter);
478 void e1000e_power_up_phy(struct e1000_adapter *adapter);
479 int e1000e_setup_rx_resources(struct e1000_ring *ring);
480 int e1000e_setup_tx_resources(struct e1000_ring *ring);
481 void e1000e_free_rx_resources(struct e1000_ring *ring);
482 void e1000e_free_tx_resources(struct e1000_ring *ring);
483 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
484 struct rtnl_link_stats64 *stats);
485 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
486 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
487 void e1000e_get_hw_control(struct e1000_adapter *adapter);
488 void e1000e_release_hw_control(struct e1000_adapter *adapter);
489 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
490
491 extern unsigned int copybreak;
492
493 extern const struct e1000_info e1000_82571_info;
494 extern const struct e1000_info e1000_82572_info;
495 extern const struct e1000_info e1000_82573_info;
496 extern const struct e1000_info e1000_82574_info;
497 extern const struct e1000_info e1000_82583_info;
498 extern const struct e1000_info e1000_ich8_info;
499 extern const struct e1000_info e1000_ich9_info;
500 extern const struct e1000_info e1000_ich10_info;
501 extern const struct e1000_info e1000_pch_info;
502 extern const struct e1000_info e1000_pch2_info;
503 extern const struct e1000_info e1000_pch_lpt_info;
504 extern const struct e1000_info e1000_es2_info;
505
506 void e1000e_ptp_init(struct e1000_adapter *adapter);
507 void e1000e_ptp_remove(struct e1000_adapter *adapter);
508
e1000_phy_hw_reset(struct e1000_hw * hw)509 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
510 {
511 return hw->phy.ops.reset(hw);
512 }
513
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)514 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
515 {
516 return hw->phy.ops.read_reg(hw, offset, data);
517 }
518
e1e_rphy_locked(struct e1000_hw * hw,u32 offset,u16 * data)519 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
520 {
521 return hw->phy.ops.read_reg_locked(hw, offset, data);
522 }
523
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)524 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
525 {
526 return hw->phy.ops.write_reg(hw, offset, data);
527 }
528
e1e_wphy_locked(struct e1000_hw * hw,u32 offset,u16 data)529 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
530 {
531 return hw->phy.ops.write_reg_locked(hw, offset, data);
532 }
533
534 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
535
e1000e_read_mac_addr(struct e1000_hw * hw)536 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
537 {
538 if (hw->mac.ops.read_mac_addr)
539 return hw->mac.ops.read_mac_addr(hw);
540
541 return e1000_read_mac_addr_generic(hw);
542 }
543
e1000_validate_nvm_checksum(struct e1000_hw * hw)544 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
545 {
546 return hw->nvm.ops.validate(hw);
547 }
548
e1000e_update_nvm_checksum(struct e1000_hw * hw)549 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
550 {
551 return hw->nvm.ops.update(hw);
552 }
553
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)554 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
555 u16 *data)
556 {
557 return hw->nvm.ops.read(hw, offset, words, data);
558 }
559
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)560 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
561 u16 *data)
562 {
563 return hw->nvm.ops.write(hw, offset, words, data);
564 }
565
e1000_get_phy_info(struct e1000_hw * hw)566 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
567 {
568 return hw->phy.ops.get_info(hw);
569 }
570
__er32(struct e1000_hw * hw,unsigned long reg)571 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
572 {
573 return readl(hw->hw_addr + reg);
574 }
575
576 #define er32(reg) __er32(hw, E1000_##reg)
577
578 s32 __ew32_prepare(struct e1000_hw *hw);
579 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
580
581 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
582
583 #define e1e_flush() er32(STATUS)
584
585 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
586 (__ew32((a), (reg + ((offset) << 2)), (value)))
587
588 #define E1000_READ_REG_ARRAY(a, reg, offset) \
589 (readl((a)->hw_addr + reg + ((offset) << 2)))
590
591 #endif /* _E1000_H_ */
592