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1 /*
2  * OMAP4 specific common source file.
3  *
4  * Copyright (C) 2010 Texas Instruments, Inc.
5  * Author:
6  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7  *
8  *
9  * This program is free software,you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/platform_device.h>
20 #include <linux/memblock.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/export.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/irqchip/irq-crossbar.h>
26 #include <linux/of_address.h>
27 #include <linux/reboot.h>
28 #include <linux/genalloc.h>
29 
30 #include <asm/hardware/cache-l2x0.h>
31 #include <asm/mach/map.h>
32 #include <asm/memblock.h>
33 #include <asm/smp_twd.h>
34 
35 #include "omap-wakeupgen.h"
36 #include "soc.h"
37 #include "iomap.h"
38 #include "common.h"
39 #include "mmc.h"
40 #include "prminst44xx.h"
41 #include "prcm_mpu44xx.h"
42 #include "omap4-sar-layout.h"
43 #include "omap-secure.h"
44 #include "sram.h"
45 
46 #ifdef CONFIG_CACHE_L2X0
47 static void __iomem *l2cache_base;
48 #endif
49 
50 static void __iomem *sar_ram_base;
51 static void __iomem *gic_dist_base_addr;
52 static void __iomem *twd_base;
53 
54 #define IRQ_LOCALTIMER		29
55 
56 #ifdef CONFIG_OMAP4_ERRATA_I688
57 /* Used to implement memory barrier on DRAM path */
58 #define OMAP4_DRAM_BARRIER_VA			0xfe600000
59 
60 void __iomem *dram_sync, *sram_sync;
61 
62 static phys_addr_t paddr;
63 static u32 size;
64 
omap_bus_sync(void)65 void omap_bus_sync(void)
66 {
67 	if (dram_sync && sram_sync) {
68 		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
69 		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
70 		isb();
71 	}
72 }
73 EXPORT_SYMBOL(omap_bus_sync);
74 
omap4_sram_init(void)75 static int __init omap4_sram_init(void)
76 {
77 	struct device_node *np;
78 	struct gen_pool *sram_pool;
79 
80 	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
81 	if (!np)
82 		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
83 			__func__);
84 	sram_pool = of_get_named_gen_pool(np, "sram", 0);
85 	if (!sram_pool)
86 		pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
87 			__func__);
88 	else
89 		sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
90 
91 	return 0;
92 }
93 omap_arch_initcall(omap4_sram_init);
94 
95 /* Steal one page physical memory for barrier implementation */
omap_barrier_reserve_memblock(void)96 int __init omap_barrier_reserve_memblock(void)
97 {
98 
99 	size = ALIGN(PAGE_SIZE, SZ_1M);
100 	paddr = arm_memblock_steal(size, SZ_1M);
101 
102 	return 0;
103 }
104 
omap_barriers_init(void)105 void __init omap_barriers_init(void)
106 {
107 	struct map_desc dram_io_desc[1];
108 
109 	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
110 	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
111 	dram_io_desc[0].length = size;
112 	dram_io_desc[0].type = MT_MEMORY_RW_SO;
113 	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
114 	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
115 
116 	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
117 		(long long) paddr, dram_io_desc[0].virtual);
118 
119 }
120 #else
omap_barriers_init(void)121 void __init omap_barriers_init(void)
122 {}
123 #endif
124 
gic_dist_disable(void)125 void gic_dist_disable(void)
126 {
127 	if (gic_dist_base_addr)
128 		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
129 }
130 
gic_dist_enable(void)131 void gic_dist_enable(void)
132 {
133 	if (gic_dist_base_addr)
134 		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
135 }
136 
gic_dist_disabled(void)137 bool gic_dist_disabled(void)
138 {
139 	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
140 }
141 
gic_timer_retrigger(void)142 void gic_timer_retrigger(void)
143 {
144 	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
145 	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
146 	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
147 
148 	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
149 		/*
150 		 * The local timer interrupt got lost while the distributor was
151 		 * disabled.  Ack the pending interrupt, and retrigger it.
152 		 */
153 		pr_warn("%s: lost localtimer interrupt\n", __func__);
154 		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
155 		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
156 			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
157 			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
158 			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
159 		}
160 	}
161 }
162 
163 #ifdef CONFIG_CACHE_L2X0
164 
omap4_get_l2cache_base(void)165 void __iomem *omap4_get_l2cache_base(void)
166 {
167 	return l2cache_base;
168 }
169 
omap4_l2c310_write_sec(unsigned long val,unsigned reg)170 static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
171 {
172 	unsigned smc_op;
173 
174 	switch (reg) {
175 	case L2X0_CTRL:
176 		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
177 		break;
178 
179 	case L2X0_AUX_CTRL:
180 		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
181 		break;
182 
183 	case L2X0_DEBUG_CTRL:
184 		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
185 		break;
186 
187 	case L310_PREFETCH_CTRL:
188 		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
189 		break;
190 
191 	case L310_POWER_CTRL:
192 		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
193 		return;
194 
195 	default:
196 		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
197 		return;
198 	}
199 
200 	omap_smc1(smc_op, val);
201 }
202 
omap_l2_cache_init(void)203 int __init omap_l2_cache_init(void)
204 {
205 	u32 aux_ctrl;
206 
207 	/* Static mapping, never released */
208 	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
209 	if (WARN_ON(!l2cache_base))
210 		return -ENOMEM;
211 
212 	/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
213 	aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
214 		   L310_AUX_CTRL_DATA_PREFETCH |
215 		   L310_AUX_CTRL_INSTR_PREFETCH;
216 
217 	outer_cache.write_sec = omap4_l2c310_write_sec;
218 	if (of_have_populated_dt())
219 		l2x0_of_init(aux_ctrl, 0xcf9fffff);
220 	else
221 		l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
222 
223 	return 0;
224 }
225 #endif
226 
omap4_get_sar_ram_base(void)227 void __iomem *omap4_get_sar_ram_base(void)
228 {
229 	return sar_ram_base;
230 }
231 
232 /*
233  * SAR RAM used to save and restore the HW
234  * context in low power modes
235  */
omap4_sar_ram_init(void)236 static int __init omap4_sar_ram_init(void)
237 {
238 	unsigned long sar_base;
239 
240 	/*
241 	 * To avoid code running on other OMAPs in
242 	 * multi-omap builds
243 	 */
244 	if (cpu_is_omap44xx())
245 		sar_base = OMAP44XX_SAR_RAM_BASE;
246 	else if (soc_is_omap54xx())
247 		sar_base = OMAP54XX_SAR_RAM_BASE;
248 	else
249 		return -ENOMEM;
250 
251 	/* Static mapping, never released */
252 	sar_ram_base = ioremap(sar_base, SZ_16K);
253 	if (WARN_ON(!sar_ram_base))
254 		return -ENOMEM;
255 
256 	return 0;
257 }
258 omap_early_initcall(omap4_sar_ram_init);
259 
omap_gic_of_init(void)260 void __init omap_gic_of_init(void)
261 {
262 	struct device_node *np;
263 
264 	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
265 	if (!cpu_is_omap446x())
266 		goto skip_errata_init;
267 
268 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
269 	gic_dist_base_addr = of_iomap(np, 0);
270 	WARN_ON(!gic_dist_base_addr);
271 
272 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
273 	twd_base = of_iomap(np, 0);
274 	WARN_ON(!twd_base);
275 
276 skip_errata_init:
277 	omap_wakeupgen_init();
278 #ifdef CONFIG_IRQ_CROSSBAR
279 	irqcrossbar_init();
280 #endif
281 	irqchip_init();
282 }
283