1 /**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27 #include <linux/module.h>
28 #include <linux/console.h>
29
30 #include <drm/drmP.h>
31 #include "vmwgfx_drv.h"
32 #include <drm/ttm/ttm_placement.h>
33 #include <drm/ttm/ttm_bo_driver.h>
34 #include <drm/ttm/ttm_object.h>
35 #include <drm/ttm/ttm_module.h>
36 #include <linux/dma_remapping.h>
37
38 #define VMWGFX_DRIVER_NAME "vmwgfx"
39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
40 #define VMWGFX_CHIP_SVGAII 0
41 #define VMW_FB_RESERVATION 0
42
43 #define VMW_MIN_INITIAL_WIDTH 800
44 #define VMW_MIN_INITIAL_HEIGHT 600
45
46
47 /**
48 * Fully encoded drm commands. Might move to vmw_drm.h
49 */
50
51 #define DRM_IOCTL_VMW_GET_PARAM \
52 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
53 struct drm_vmw_getparam_arg)
54 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
55 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
56 union drm_vmw_alloc_dmabuf_arg)
57 #define DRM_IOCTL_VMW_UNREF_DMABUF \
58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
59 struct drm_vmw_unref_dmabuf_arg)
60 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
61 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
62 struct drm_vmw_cursor_bypass_arg)
63
64 #define DRM_IOCTL_VMW_CONTROL_STREAM \
65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
66 struct drm_vmw_control_stream_arg)
67 #define DRM_IOCTL_VMW_CLAIM_STREAM \
68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
69 struct drm_vmw_stream_arg)
70 #define DRM_IOCTL_VMW_UNREF_STREAM \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
72 struct drm_vmw_stream_arg)
73
74 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
76 struct drm_vmw_context_arg)
77 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
79 struct drm_vmw_context_arg)
80 #define DRM_IOCTL_VMW_CREATE_SURFACE \
81 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
82 union drm_vmw_surface_create_arg)
83 #define DRM_IOCTL_VMW_UNREF_SURFACE \
84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
85 struct drm_vmw_surface_arg)
86 #define DRM_IOCTL_VMW_REF_SURFACE \
87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
88 union drm_vmw_surface_reference_arg)
89 #define DRM_IOCTL_VMW_EXECBUF \
90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
91 struct drm_vmw_execbuf_arg)
92 #define DRM_IOCTL_VMW_GET_3D_CAP \
93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
94 struct drm_vmw_get_3d_cap_arg)
95 #define DRM_IOCTL_VMW_FENCE_WAIT \
96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
97 struct drm_vmw_fence_wait_arg)
98 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
100 struct drm_vmw_fence_signaled_arg)
101 #define DRM_IOCTL_VMW_FENCE_UNREF \
102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
103 struct drm_vmw_fence_arg)
104 #define DRM_IOCTL_VMW_FENCE_EVENT \
105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
106 struct drm_vmw_fence_event_arg)
107 #define DRM_IOCTL_VMW_PRESENT \
108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
109 struct drm_vmw_present_arg)
110 #define DRM_IOCTL_VMW_PRESENT_READBACK \
111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
112 struct drm_vmw_present_readback_arg)
113 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
115 struct drm_vmw_update_layout_arg)
116 #define DRM_IOCTL_VMW_CREATE_SHADER \
117 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
118 struct drm_vmw_shader_create_arg)
119 #define DRM_IOCTL_VMW_UNREF_SHADER \
120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
121 struct drm_vmw_shader_arg)
122 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
124 union drm_vmw_gb_surface_create_arg)
125 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
126 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
127 union drm_vmw_gb_surface_reference_arg)
128 #define DRM_IOCTL_VMW_SYNCCPU \
129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
130 struct drm_vmw_synccpu_arg)
131
132 /**
133 * The core DRM version of this macro doesn't account for
134 * DRM_COMMAND_BASE.
135 */
136
137 #define VMW_IOCTL_DEF(ioctl, func, flags) \
138 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
139
140 /**
141 * Ioctl definitions.
142 */
143
144 static const struct drm_ioctl_desc vmw_ioctls[] = {
145 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
146 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
147 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
148 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
149 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
150 DRM_UNLOCKED | DRM_RENDER_ALLOW),
151 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
152 vmw_kms_cursor_bypass_ioctl,
153 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
154
155 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
156 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
157 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
158 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
159 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
160 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
161
162 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
163 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
164 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
165 DRM_UNLOCKED | DRM_RENDER_ALLOW),
166 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
167 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
168 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
169 DRM_UNLOCKED | DRM_RENDER_ALLOW),
170 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
171 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
172 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
173 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
174 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
175 DRM_UNLOCKED | DRM_RENDER_ALLOW),
176 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
177 vmw_fence_obj_signaled_ioctl,
178 DRM_UNLOCKED | DRM_RENDER_ALLOW),
179 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
180 DRM_UNLOCKED | DRM_RENDER_ALLOW),
181 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
182 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
183 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
184 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
185
186 /* these allow direct access to the framebuffers mark as master only */
187 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
188 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
189 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
190 vmw_present_readback_ioctl,
191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
192 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
193 vmw_kms_update_layout_ioctl,
194 DRM_MASTER | DRM_UNLOCKED),
195 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
196 vmw_shader_define_ioctl,
197 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
198 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
199 vmw_shader_destroy_ioctl,
200 DRM_UNLOCKED | DRM_RENDER_ALLOW),
201 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
202 vmw_gb_surface_define_ioctl,
203 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
204 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
205 vmw_gb_surface_reference_ioctl,
206 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
207 VMW_IOCTL_DEF(VMW_SYNCCPU,
208 vmw_user_dmabuf_synccpu_ioctl,
209 DRM_UNLOCKED | DRM_RENDER_ALLOW),
210 };
211
212 static struct pci_device_id vmw_pci_id_list[] = {
213 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
214 {0, 0, 0}
215 };
216 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
217
218 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
219 static int vmw_force_iommu;
220 static int vmw_restrict_iommu;
221 static int vmw_force_coherent;
222 static int vmw_restrict_dma_mask;
223
224 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
225 static void vmw_master_init(struct vmw_master *);
226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
227 void *ptr);
228
229 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
230 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
231 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
232 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
233 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
234 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
235 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
236 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
237 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
238 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
239
240
vmw_print_capabilities(uint32_t capabilities)241 static void vmw_print_capabilities(uint32_t capabilities)
242 {
243 DRM_INFO("Capabilities:\n");
244 if (capabilities & SVGA_CAP_RECT_COPY)
245 DRM_INFO(" Rect copy.\n");
246 if (capabilities & SVGA_CAP_CURSOR)
247 DRM_INFO(" Cursor.\n");
248 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
249 DRM_INFO(" Cursor bypass.\n");
250 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
251 DRM_INFO(" Cursor bypass 2.\n");
252 if (capabilities & SVGA_CAP_8BIT_EMULATION)
253 DRM_INFO(" 8bit emulation.\n");
254 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
255 DRM_INFO(" Alpha cursor.\n");
256 if (capabilities & SVGA_CAP_3D)
257 DRM_INFO(" 3D.\n");
258 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
259 DRM_INFO(" Extended Fifo.\n");
260 if (capabilities & SVGA_CAP_MULTIMON)
261 DRM_INFO(" Multimon.\n");
262 if (capabilities & SVGA_CAP_PITCHLOCK)
263 DRM_INFO(" Pitchlock.\n");
264 if (capabilities & SVGA_CAP_IRQMASK)
265 DRM_INFO(" Irq mask.\n");
266 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
267 DRM_INFO(" Display Topology.\n");
268 if (capabilities & SVGA_CAP_GMR)
269 DRM_INFO(" GMR.\n");
270 if (capabilities & SVGA_CAP_TRACES)
271 DRM_INFO(" Traces.\n");
272 if (capabilities & SVGA_CAP_GMR2)
273 DRM_INFO(" GMR2.\n");
274 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
275 DRM_INFO(" Screen Object 2.\n");
276 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
277 DRM_INFO(" Command Buffers.\n");
278 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
279 DRM_INFO(" Command Buffers 2.\n");
280 if (capabilities & SVGA_CAP_GBOBJECTS)
281 DRM_INFO(" Guest Backed Resources.\n");
282 }
283
284 /**
285 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
286 *
287 * @dev_priv: A device private structure.
288 *
289 * This function creates a small buffer object that holds the query
290 * result for dummy queries emitted as query barriers.
291 * The function will then map the first page and initialize a pending
292 * occlusion query result structure, Finally it will unmap the buffer.
293 * No interruptible waits are done within this function.
294 *
295 * Returns an error if bo creation or initialization fails.
296 */
vmw_dummy_query_bo_create(struct vmw_private * dev_priv)297 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
298 {
299 int ret;
300 struct ttm_buffer_object *bo;
301 struct ttm_bo_kmap_obj map;
302 volatile SVGA3dQueryResult *result;
303 bool dummy;
304
305 /*
306 * Create the bo as pinned, so that a tryreserve will
307 * immediately succeed. This is because we're the only
308 * user of the bo currently.
309 */
310 ret = ttm_bo_create(&dev_priv->bdev,
311 PAGE_SIZE,
312 ttm_bo_type_device,
313 &vmw_sys_ne_placement,
314 0, false, NULL,
315 &bo);
316
317 if (unlikely(ret != 0))
318 return ret;
319
320 ret = ttm_bo_reserve(bo, false, true, false, NULL);
321 BUG_ON(ret != 0);
322
323 ret = ttm_bo_kmap(bo, 0, 1, &map);
324 if (likely(ret == 0)) {
325 result = ttm_kmap_obj_virtual(&map, &dummy);
326 result->totalSize = sizeof(*result);
327 result->state = SVGA3D_QUERYSTATE_PENDING;
328 result->result32 = 0xff;
329 ttm_bo_kunmap(&map);
330 }
331 vmw_bo_pin(bo, false);
332 ttm_bo_unreserve(bo);
333
334 if (unlikely(ret != 0)) {
335 DRM_ERROR("Dummy query buffer map failed.\n");
336 ttm_bo_unref(&bo);
337 } else
338 dev_priv->dummy_query_bo = bo;
339
340 return ret;
341 }
342
vmw_request_device(struct vmw_private * dev_priv)343 static int vmw_request_device(struct vmw_private *dev_priv)
344 {
345 int ret;
346
347 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
348 if (unlikely(ret != 0)) {
349 DRM_ERROR("Unable to initialize FIFO.\n");
350 return ret;
351 }
352 vmw_fence_fifo_up(dev_priv->fman);
353 if (dev_priv->has_mob) {
354 ret = vmw_otables_setup(dev_priv);
355 if (unlikely(ret != 0)) {
356 DRM_ERROR("Unable to initialize "
357 "guest Memory OBjects.\n");
358 goto out_no_mob;
359 }
360 }
361 ret = vmw_dummy_query_bo_create(dev_priv);
362 if (unlikely(ret != 0))
363 goto out_no_query_bo;
364
365 return 0;
366
367 out_no_query_bo:
368 if (dev_priv->has_mob)
369 vmw_otables_takedown(dev_priv);
370 out_no_mob:
371 vmw_fence_fifo_down(dev_priv->fman);
372 vmw_fifo_release(dev_priv, &dev_priv->fifo);
373 return ret;
374 }
375
vmw_release_device(struct vmw_private * dev_priv)376 static void vmw_release_device(struct vmw_private *dev_priv)
377 {
378 /*
379 * Previous destructions should've released
380 * the pinned bo.
381 */
382
383 BUG_ON(dev_priv->pinned_bo != NULL);
384
385 ttm_bo_unref(&dev_priv->dummy_query_bo);
386 if (dev_priv->has_mob)
387 vmw_otables_takedown(dev_priv);
388 vmw_fence_fifo_down(dev_priv->fman);
389 vmw_fifo_release(dev_priv, &dev_priv->fifo);
390 }
391
392
393 /**
394 * Increase the 3d resource refcount.
395 * If the count was prevously zero, initialize the fifo, switching to svga
396 * mode. Note that the master holds a ref as well, and may request an
397 * explicit switch to svga mode if fb is not running, using @unhide_svga.
398 */
vmw_3d_resource_inc(struct vmw_private * dev_priv,bool unhide_svga)399 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
400 bool unhide_svga)
401 {
402 int ret = 0;
403
404 mutex_lock(&dev_priv->release_mutex);
405 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
406 ret = vmw_request_device(dev_priv);
407 if (unlikely(ret != 0))
408 --dev_priv->num_3d_resources;
409 } else if (unhide_svga) {
410 vmw_write(dev_priv, SVGA_REG_ENABLE,
411 vmw_read(dev_priv, SVGA_REG_ENABLE) &
412 ~SVGA_REG_ENABLE_HIDE);
413 }
414
415 mutex_unlock(&dev_priv->release_mutex);
416 return ret;
417 }
418
419 /**
420 * Decrease the 3d resource refcount.
421 * If the count reaches zero, disable the fifo, switching to vga mode.
422 * Note that the master holds a refcount as well, and may request an
423 * explicit switch to vga mode when it releases its refcount to account
424 * for the situation of an X server vt switch to VGA with 3d resources
425 * active.
426 */
vmw_3d_resource_dec(struct vmw_private * dev_priv,bool hide_svga)427 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
428 bool hide_svga)
429 {
430 int32_t n3d;
431
432 mutex_lock(&dev_priv->release_mutex);
433 if (unlikely(--dev_priv->num_3d_resources == 0))
434 vmw_release_device(dev_priv);
435 else if (hide_svga)
436 vmw_write(dev_priv, SVGA_REG_ENABLE,
437 vmw_read(dev_priv, SVGA_REG_ENABLE) |
438 SVGA_REG_ENABLE_HIDE);
439
440 n3d = (int32_t) dev_priv->num_3d_resources;
441 mutex_unlock(&dev_priv->release_mutex);
442
443 BUG_ON(n3d < 0);
444 }
445
446 /**
447 * Sets the initial_[width|height] fields on the given vmw_private.
448 *
449 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
450 * clamping the value to fb_max_[width|height] fields and the
451 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
452 * If the values appear to be invalid, set them to
453 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
454 */
vmw_get_initial_size(struct vmw_private * dev_priv)455 static void vmw_get_initial_size(struct vmw_private *dev_priv)
456 {
457 uint32_t width;
458 uint32_t height;
459
460 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
461 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
462
463 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
464 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
465
466 if (width > dev_priv->fb_max_width ||
467 height > dev_priv->fb_max_height) {
468
469 /*
470 * This is a host error and shouldn't occur.
471 */
472
473 width = VMW_MIN_INITIAL_WIDTH;
474 height = VMW_MIN_INITIAL_HEIGHT;
475 }
476
477 dev_priv->initial_width = width;
478 dev_priv->initial_height = height;
479 }
480
481 /**
482 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
483 * system.
484 *
485 * @dev_priv: Pointer to a struct vmw_private
486 *
487 * This functions tries to determine the IOMMU setup and what actions
488 * need to be taken by the driver to make system pages visible to the
489 * device.
490 * If this function decides that DMA is not possible, it returns -EINVAL.
491 * The driver may then try to disable features of the device that require
492 * DMA.
493 */
vmw_dma_select_mode(struct vmw_private * dev_priv)494 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
495 {
496 static const char *names[vmw_dma_map_max] = {
497 [vmw_dma_phys] = "Using physical TTM page addresses.",
498 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
499 [vmw_dma_map_populate] = "Keeping DMA mappings.",
500 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
501 #ifdef CONFIG_X86
502 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
503
504 #ifdef CONFIG_INTEL_IOMMU
505 if (intel_iommu_enabled) {
506 dev_priv->map_mode = vmw_dma_map_populate;
507 goto out_fixup;
508 }
509 #endif
510
511 if (!(vmw_force_iommu || vmw_force_coherent)) {
512 dev_priv->map_mode = vmw_dma_phys;
513 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
514 return 0;
515 }
516
517 dev_priv->map_mode = vmw_dma_map_populate;
518
519 if (dma_ops->sync_single_for_cpu)
520 dev_priv->map_mode = vmw_dma_alloc_coherent;
521 #ifdef CONFIG_SWIOTLB
522 if (swiotlb_nr_tbl() == 0)
523 dev_priv->map_mode = vmw_dma_map_populate;
524 #endif
525
526 #ifdef CONFIG_INTEL_IOMMU
527 out_fixup:
528 #endif
529 if (dev_priv->map_mode == vmw_dma_map_populate &&
530 vmw_restrict_iommu)
531 dev_priv->map_mode = vmw_dma_map_bind;
532
533 if (vmw_force_coherent)
534 dev_priv->map_mode = vmw_dma_alloc_coherent;
535
536 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
537 /*
538 * No coherent page pool
539 */
540 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
541 return -EINVAL;
542 #endif
543
544 #else /* CONFIG_X86 */
545 dev_priv->map_mode = vmw_dma_map_populate;
546 #endif /* CONFIG_X86 */
547
548 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
549
550 return 0;
551 }
552
553 /**
554 * vmw_dma_masks - set required page- and dma masks
555 *
556 * @dev: Pointer to struct drm-device
557 *
558 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
559 * restriction also for 64-bit systems.
560 */
561 #ifdef CONFIG_INTEL_IOMMU
vmw_dma_masks(struct vmw_private * dev_priv)562 static int vmw_dma_masks(struct vmw_private *dev_priv)
563 {
564 struct drm_device *dev = dev_priv->dev;
565
566 if (intel_iommu_enabled &&
567 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
568 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
569 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
570 }
571 return 0;
572 }
573 #else
vmw_dma_masks(struct vmw_private * dev_priv)574 static int vmw_dma_masks(struct vmw_private *dev_priv)
575 {
576 return 0;
577 }
578 #endif
579
vmw_driver_load(struct drm_device * dev,unsigned long chipset)580 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
581 {
582 struct vmw_private *dev_priv;
583 int ret;
584 uint32_t svga_id;
585 enum vmw_res_type i;
586 bool refuse_dma = false;
587
588 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
589 if (unlikely(dev_priv == NULL)) {
590 DRM_ERROR("Failed allocating a device private struct.\n");
591 return -ENOMEM;
592 }
593
594 pci_set_master(dev->pdev);
595
596 dev_priv->dev = dev;
597 dev_priv->vmw_chipset = chipset;
598 dev_priv->last_read_seqno = (uint32_t) -100;
599 mutex_init(&dev_priv->cmdbuf_mutex);
600 mutex_init(&dev_priv->release_mutex);
601 mutex_init(&dev_priv->binding_mutex);
602 rwlock_init(&dev_priv->resource_lock);
603 ttm_lock_init(&dev_priv->reservation_sem);
604 spin_lock_init(&dev_priv->hw_lock);
605 spin_lock_init(&dev_priv->waiter_lock);
606 spin_lock_init(&dev_priv->cap_lock);
607
608 for (i = vmw_res_context; i < vmw_res_max; ++i) {
609 idr_init(&dev_priv->res_idr[i]);
610 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
611 }
612
613 mutex_init(&dev_priv->init_mutex);
614 init_waitqueue_head(&dev_priv->fence_queue);
615 init_waitqueue_head(&dev_priv->fifo_queue);
616 dev_priv->fence_queue_waiters = 0;
617 atomic_set(&dev_priv->fifo_queue_waiters, 0);
618
619 dev_priv->used_memory_size = 0;
620
621 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
622 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
623 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
624
625 dev_priv->enable_fb = enable_fbdev;
626
627 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
628 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
629 if (svga_id != SVGA_ID_2) {
630 ret = -ENOSYS;
631 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
632 goto out_err0;
633 }
634
635 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
636 ret = vmw_dma_select_mode(dev_priv);
637 if (unlikely(ret != 0)) {
638 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
639 refuse_dma = true;
640 }
641
642 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
643 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
644 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
645 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
646
647 vmw_get_initial_size(dev_priv);
648
649 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
650 dev_priv->max_gmr_ids =
651 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
652 dev_priv->max_gmr_pages =
653 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
654 dev_priv->memory_size =
655 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
656 dev_priv->memory_size -= dev_priv->vram_size;
657 } else {
658 /*
659 * An arbitrary limit of 512MiB on surface
660 * memory. But all HWV8 hardware supports GMR2.
661 */
662 dev_priv->memory_size = 512*1024*1024;
663 }
664 dev_priv->max_mob_pages = 0;
665 dev_priv->max_mob_size = 0;
666 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
667 uint64_t mem_size =
668 vmw_read(dev_priv,
669 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
670
671 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
672 dev_priv->prim_bb_mem =
673 vmw_read(dev_priv,
674 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
675 dev_priv->max_mob_size =
676 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
677 } else
678 dev_priv->prim_bb_mem = dev_priv->vram_size;
679
680 ret = vmw_dma_masks(dev_priv);
681 if (unlikely(ret != 0))
682 goto out_err0;
683
684 /*
685 * Limit back buffer size to VRAM size. Remove this once
686 * screen targets are implemented.
687 */
688 if (dev_priv->prim_bb_mem > dev_priv->vram_size)
689 dev_priv->prim_bb_mem = dev_priv->vram_size;
690
691 vmw_print_capabilities(dev_priv->capabilities);
692
693 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
694 DRM_INFO("Max GMR ids is %u\n",
695 (unsigned)dev_priv->max_gmr_ids);
696 DRM_INFO("Max number of GMR pages is %u\n",
697 (unsigned)dev_priv->max_gmr_pages);
698 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
699 (unsigned)dev_priv->memory_size / 1024);
700 }
701 DRM_INFO("Maximum display memory size is %u kiB\n",
702 dev_priv->prim_bb_mem / 1024);
703 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
704 dev_priv->vram_start, dev_priv->vram_size / 1024);
705 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
706 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
707
708 ret = vmw_ttm_global_init(dev_priv);
709 if (unlikely(ret != 0))
710 goto out_err0;
711
712
713 vmw_master_init(&dev_priv->fbdev_master);
714 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
715 dev_priv->active_master = &dev_priv->fbdev_master;
716
717
718 ret = ttm_bo_device_init(&dev_priv->bdev,
719 dev_priv->bo_global_ref.ref.object,
720 &vmw_bo_driver,
721 dev->anon_inode->i_mapping,
722 VMWGFX_FILE_PAGE_OFFSET,
723 false);
724 if (unlikely(ret != 0)) {
725 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
726 goto out_err1;
727 }
728
729 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
730 dev_priv->mmio_size);
731
732 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
733 dev_priv->mmio_size);
734
735 if (unlikely(dev_priv->mmio_virt == NULL)) {
736 ret = -ENOMEM;
737 DRM_ERROR("Failed mapping MMIO.\n");
738 goto out_err3;
739 }
740
741 /* Need mmio memory to check for fifo pitchlock cap. */
742 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
743 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
744 !vmw_fifo_have_pitchlock(dev_priv)) {
745 ret = -ENOSYS;
746 DRM_ERROR("Hardware has no pitchlock\n");
747 goto out_err4;
748 }
749
750 dev_priv->tdev = ttm_object_device_init
751 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
752
753 if (unlikely(dev_priv->tdev == NULL)) {
754 DRM_ERROR("Unable to initialize TTM object management.\n");
755 ret = -ENOMEM;
756 goto out_err4;
757 }
758
759 dev->dev_private = dev_priv;
760
761 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
762 dev_priv->stealth = (ret != 0);
763 if (dev_priv->stealth) {
764 /**
765 * Request at least the mmio PCI resource.
766 */
767
768 DRM_INFO("It appears like vesafb is loaded. "
769 "Ignore above error if any.\n");
770 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
771 if (unlikely(ret != 0)) {
772 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
773 goto out_no_device;
774 }
775 }
776
777 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
778 ret = drm_irq_install(dev, dev->pdev->irq);
779 if (ret != 0) {
780 DRM_ERROR("Failed installing irq: %d\n", ret);
781 goto out_no_irq;
782 }
783 }
784
785 dev_priv->fman = vmw_fence_manager_init(dev_priv);
786 if (unlikely(dev_priv->fman == NULL)) {
787 ret = -ENOMEM;
788 goto out_no_fman;
789 }
790
791
792 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
793 (dev_priv->vram_size >> PAGE_SHIFT));
794 if (unlikely(ret != 0)) {
795 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
796 goto out_no_vram;
797 }
798
799 dev_priv->has_gmr = true;
800 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
801 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
802 VMW_PL_GMR) != 0) {
803 DRM_INFO("No GMR memory available. "
804 "Graphics memory resources are very limited.\n");
805 dev_priv->has_gmr = false;
806 }
807
808 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
809 dev_priv->has_mob = true;
810 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
811 VMW_PL_MOB) != 0) {
812 DRM_INFO("No MOB memory available. "
813 "3D will be disabled.\n");
814 dev_priv->has_mob = false;
815 }
816 }
817
818 vmw_kms_save_vga(dev_priv);
819
820 /* Start kms and overlay systems, needs fifo. */
821 ret = vmw_kms_init(dev_priv);
822 if (unlikely(ret != 0))
823 goto out_no_kms;
824 vmw_overlay_init(dev_priv);
825
826 if (dev_priv->enable_fb) {
827 ret = vmw_3d_resource_inc(dev_priv, true);
828 if (unlikely(ret != 0))
829 goto out_no_fifo;
830 vmw_fb_init(dev_priv);
831 }
832
833 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
834 register_pm_notifier(&dev_priv->pm_nb);
835
836 return 0;
837
838 out_no_fifo:
839 vmw_overlay_close(dev_priv);
840 vmw_kms_close(dev_priv);
841 out_no_kms:
842 vmw_kms_restore_vga(dev_priv);
843 if (dev_priv->has_mob)
844 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
845 if (dev_priv->has_gmr)
846 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
847 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
848 out_no_vram:
849 vmw_fence_manager_takedown(dev_priv->fman);
850 out_no_fman:
851 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
852 drm_irq_uninstall(dev_priv->dev);
853 out_no_irq:
854 if (dev_priv->stealth)
855 pci_release_region(dev->pdev, 2);
856 else
857 pci_release_regions(dev->pdev);
858 out_no_device:
859 ttm_object_device_release(&dev_priv->tdev);
860 out_err4:
861 iounmap(dev_priv->mmio_virt);
862 out_err3:
863 arch_phys_wc_del(dev_priv->mmio_mtrr);
864 (void)ttm_bo_device_release(&dev_priv->bdev);
865 out_err1:
866 vmw_ttm_global_release(dev_priv);
867 out_err0:
868 for (i = vmw_res_context; i < vmw_res_max; ++i)
869 idr_destroy(&dev_priv->res_idr[i]);
870
871 kfree(dev_priv);
872 return ret;
873 }
874
vmw_driver_unload(struct drm_device * dev)875 static int vmw_driver_unload(struct drm_device *dev)
876 {
877 struct vmw_private *dev_priv = vmw_priv(dev);
878 enum vmw_res_type i;
879
880 unregister_pm_notifier(&dev_priv->pm_nb);
881
882 if (dev_priv->ctx.res_ht_initialized)
883 drm_ht_remove(&dev_priv->ctx.res_ht);
884 if (dev_priv->ctx.cmd_bounce)
885 vfree(dev_priv->ctx.cmd_bounce);
886 if (dev_priv->enable_fb) {
887 vmw_fb_close(dev_priv);
888 vmw_kms_restore_vga(dev_priv);
889 vmw_3d_resource_dec(dev_priv, false);
890 }
891 vmw_kms_close(dev_priv);
892 vmw_overlay_close(dev_priv);
893
894 if (dev_priv->has_mob)
895 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
896 if (dev_priv->has_gmr)
897 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
898 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
899
900 vmw_fence_manager_takedown(dev_priv->fman);
901 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
902 drm_irq_uninstall(dev_priv->dev);
903 if (dev_priv->stealth)
904 pci_release_region(dev->pdev, 2);
905 else
906 pci_release_regions(dev->pdev);
907
908 ttm_object_device_release(&dev_priv->tdev);
909 iounmap(dev_priv->mmio_virt);
910 arch_phys_wc_del(dev_priv->mmio_mtrr);
911 (void)ttm_bo_device_release(&dev_priv->bdev);
912 vmw_ttm_global_release(dev_priv);
913
914 for (i = vmw_res_context; i < vmw_res_max; ++i)
915 idr_destroy(&dev_priv->res_idr[i]);
916
917 kfree(dev_priv);
918
919 return 0;
920 }
921
vmw_preclose(struct drm_device * dev,struct drm_file * file_priv)922 static void vmw_preclose(struct drm_device *dev,
923 struct drm_file *file_priv)
924 {
925 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
926 struct vmw_private *dev_priv = vmw_priv(dev);
927
928 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
929 }
930
vmw_postclose(struct drm_device * dev,struct drm_file * file_priv)931 static void vmw_postclose(struct drm_device *dev,
932 struct drm_file *file_priv)
933 {
934 struct vmw_fpriv *vmw_fp;
935
936 vmw_fp = vmw_fpriv(file_priv);
937
938 if (vmw_fp->locked_master) {
939 struct vmw_master *vmaster =
940 vmw_master(vmw_fp->locked_master);
941
942 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
943 ttm_vt_unlock(&vmaster->lock);
944 drm_master_put(&vmw_fp->locked_master);
945 }
946
947 ttm_object_file_release(&vmw_fp->tfile);
948 kfree(vmw_fp);
949 }
950
vmw_driver_open(struct drm_device * dev,struct drm_file * file_priv)951 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
952 {
953 struct vmw_private *dev_priv = vmw_priv(dev);
954 struct vmw_fpriv *vmw_fp;
955 int ret = -ENOMEM;
956
957 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
958 if (unlikely(vmw_fp == NULL))
959 return ret;
960
961 INIT_LIST_HEAD(&vmw_fp->fence_events);
962 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
963 if (unlikely(vmw_fp->tfile == NULL))
964 goto out_no_tfile;
965
966 file_priv->driver_priv = vmw_fp;
967
968 return 0;
969
970 out_no_tfile:
971 kfree(vmw_fp);
972 return ret;
973 }
974
vmw_master_check(struct drm_device * dev,struct drm_file * file_priv,unsigned int flags)975 static struct vmw_master *vmw_master_check(struct drm_device *dev,
976 struct drm_file *file_priv,
977 unsigned int flags)
978 {
979 int ret;
980 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
981 struct vmw_master *vmaster;
982
983 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
984 !(flags & DRM_AUTH))
985 return NULL;
986
987 ret = mutex_lock_interruptible(&dev->master_mutex);
988 if (unlikely(ret != 0))
989 return ERR_PTR(-ERESTARTSYS);
990
991 if (file_priv->is_master) {
992 mutex_unlock(&dev->master_mutex);
993 return NULL;
994 }
995
996 /*
997 * Check if we were previously master, but now dropped.
998 */
999 if (vmw_fp->locked_master) {
1000 mutex_unlock(&dev->master_mutex);
1001 DRM_ERROR("Dropped master trying to access ioctl that "
1002 "requires authentication.\n");
1003 return ERR_PTR(-EACCES);
1004 }
1005 mutex_unlock(&dev->master_mutex);
1006
1007 /*
1008 * Taking the drm_global_mutex after the TTM lock might deadlock
1009 */
1010 if (!(flags & DRM_UNLOCKED)) {
1011 DRM_ERROR("Refusing locked ioctl access.\n");
1012 return ERR_PTR(-EDEADLK);
1013 }
1014
1015 /*
1016 * Take the TTM lock. Possibly sleep waiting for the authenticating
1017 * master to become master again, or for a SIGTERM if the
1018 * authenticating master exits.
1019 */
1020 vmaster = vmw_master(file_priv->master);
1021 ret = ttm_read_lock(&vmaster->lock, true);
1022 if (unlikely(ret != 0))
1023 vmaster = ERR_PTR(ret);
1024
1025 return vmaster;
1026 }
1027
vmw_generic_ioctl(struct file * filp,unsigned int cmd,unsigned long arg,long (* ioctl_func)(struct file *,unsigned int,unsigned long))1028 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1029 unsigned long arg,
1030 long (*ioctl_func)(struct file *, unsigned int,
1031 unsigned long))
1032 {
1033 struct drm_file *file_priv = filp->private_data;
1034 struct drm_device *dev = file_priv->minor->dev;
1035 unsigned int nr = DRM_IOCTL_NR(cmd);
1036 struct vmw_master *vmaster;
1037 unsigned int flags;
1038 long ret;
1039
1040 /*
1041 * Do extra checking on driver private ioctls.
1042 */
1043
1044 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1045 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1046 const struct drm_ioctl_desc *ioctl =
1047 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1048
1049 if (unlikely(ioctl->cmd_drv != cmd)) {
1050 DRM_ERROR("Invalid command format, ioctl %d\n",
1051 nr - DRM_COMMAND_BASE);
1052 return -EINVAL;
1053 }
1054 flags = ioctl->flags;
1055 } else if (!drm_ioctl_flags(nr, &flags))
1056 return -EINVAL;
1057
1058 vmaster = vmw_master_check(dev, file_priv, flags);
1059 if (unlikely(IS_ERR(vmaster))) {
1060 ret = PTR_ERR(vmaster);
1061
1062 if (ret != -ERESTARTSYS)
1063 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1064 nr, ret);
1065 return ret;
1066 }
1067
1068 ret = ioctl_func(filp, cmd, arg);
1069 if (vmaster)
1070 ttm_read_unlock(&vmaster->lock);
1071
1072 return ret;
1073 }
1074
vmw_unlocked_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1075 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1076 unsigned long arg)
1077 {
1078 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1079 }
1080
1081 #ifdef CONFIG_COMPAT
vmw_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)1082 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1083 unsigned long arg)
1084 {
1085 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1086 }
1087 #endif
1088
vmw_lastclose(struct drm_device * dev)1089 static void vmw_lastclose(struct drm_device *dev)
1090 {
1091 struct drm_crtc *crtc;
1092 struct drm_mode_set set;
1093 int ret;
1094
1095 set.x = 0;
1096 set.y = 0;
1097 set.fb = NULL;
1098 set.mode = NULL;
1099 set.connectors = NULL;
1100 set.num_connectors = 0;
1101
1102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1103 set.crtc = crtc;
1104 ret = drm_mode_set_config_internal(&set);
1105 WARN_ON(ret != 0);
1106 }
1107
1108 }
1109
vmw_master_init(struct vmw_master * vmaster)1110 static void vmw_master_init(struct vmw_master *vmaster)
1111 {
1112 ttm_lock_init(&vmaster->lock);
1113 INIT_LIST_HEAD(&vmaster->fb_surf);
1114 mutex_init(&vmaster->fb_surf_mutex);
1115 }
1116
vmw_master_create(struct drm_device * dev,struct drm_master * master)1117 static int vmw_master_create(struct drm_device *dev,
1118 struct drm_master *master)
1119 {
1120 struct vmw_master *vmaster;
1121
1122 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1123 if (unlikely(vmaster == NULL))
1124 return -ENOMEM;
1125
1126 vmw_master_init(vmaster);
1127 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1128 master->driver_priv = vmaster;
1129
1130 return 0;
1131 }
1132
vmw_master_destroy(struct drm_device * dev,struct drm_master * master)1133 static void vmw_master_destroy(struct drm_device *dev,
1134 struct drm_master *master)
1135 {
1136 struct vmw_master *vmaster = vmw_master(master);
1137
1138 master->driver_priv = NULL;
1139 kfree(vmaster);
1140 }
1141
1142
vmw_master_set(struct drm_device * dev,struct drm_file * file_priv,bool from_open)1143 static int vmw_master_set(struct drm_device *dev,
1144 struct drm_file *file_priv,
1145 bool from_open)
1146 {
1147 struct vmw_private *dev_priv = vmw_priv(dev);
1148 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1149 struct vmw_master *active = dev_priv->active_master;
1150 struct vmw_master *vmaster = vmw_master(file_priv->master);
1151 int ret = 0;
1152
1153 if (!dev_priv->enable_fb) {
1154 ret = vmw_3d_resource_inc(dev_priv, true);
1155 if (unlikely(ret != 0))
1156 return ret;
1157 vmw_kms_save_vga(dev_priv);
1158 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1159 }
1160
1161 if (active) {
1162 BUG_ON(active != &dev_priv->fbdev_master);
1163 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1164 if (unlikely(ret != 0))
1165 goto out_no_active_lock;
1166
1167 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1168 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1169 if (unlikely(ret != 0)) {
1170 DRM_ERROR("Unable to clean VRAM on "
1171 "master drop.\n");
1172 }
1173
1174 dev_priv->active_master = NULL;
1175 }
1176
1177 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1178 if (!from_open) {
1179 ttm_vt_unlock(&vmaster->lock);
1180 BUG_ON(vmw_fp->locked_master != file_priv->master);
1181 drm_master_put(&vmw_fp->locked_master);
1182 }
1183
1184 dev_priv->active_master = vmaster;
1185
1186 return 0;
1187
1188 out_no_active_lock:
1189 if (!dev_priv->enable_fb) {
1190 vmw_kms_restore_vga(dev_priv);
1191 vmw_3d_resource_dec(dev_priv, true);
1192 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1193 }
1194 return ret;
1195 }
1196
vmw_master_drop(struct drm_device * dev,struct drm_file * file_priv,bool from_release)1197 static void vmw_master_drop(struct drm_device *dev,
1198 struct drm_file *file_priv,
1199 bool from_release)
1200 {
1201 struct vmw_private *dev_priv = vmw_priv(dev);
1202 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1203 struct vmw_master *vmaster = vmw_master(file_priv->master);
1204 int ret;
1205
1206 /**
1207 * Make sure the master doesn't disappear while we have
1208 * it locked.
1209 */
1210
1211 vmw_fp->locked_master = drm_master_get(file_priv->master);
1212 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1213 if (unlikely((ret != 0))) {
1214 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1215 drm_master_put(&vmw_fp->locked_master);
1216 }
1217
1218 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1219 vmw_execbuf_release_pinned_bo(dev_priv);
1220
1221 if (!dev_priv->enable_fb) {
1222 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1223 if (unlikely(ret != 0))
1224 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1225 vmw_kms_restore_vga(dev_priv);
1226 vmw_3d_resource_dec(dev_priv, true);
1227 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1228 }
1229
1230 dev_priv->active_master = &dev_priv->fbdev_master;
1231 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1232 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1233
1234 if (dev_priv->enable_fb)
1235 vmw_fb_on(dev_priv);
1236 }
1237
1238
vmw_remove(struct pci_dev * pdev)1239 static void vmw_remove(struct pci_dev *pdev)
1240 {
1241 struct drm_device *dev = pci_get_drvdata(pdev);
1242
1243 drm_put_dev(dev);
1244 }
1245
vmwgfx_pm_notifier(struct notifier_block * nb,unsigned long val,void * ptr)1246 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1247 void *ptr)
1248 {
1249 struct vmw_private *dev_priv =
1250 container_of(nb, struct vmw_private, pm_nb);
1251
1252 switch (val) {
1253 case PM_HIBERNATION_PREPARE:
1254 case PM_SUSPEND_PREPARE:
1255 ttm_suspend_lock(&dev_priv->reservation_sem);
1256
1257 /**
1258 * This empties VRAM and unbinds all GMR bindings.
1259 * Buffer contents is moved to swappable memory.
1260 */
1261 vmw_execbuf_release_pinned_bo(dev_priv);
1262 vmw_resource_evict_all(dev_priv);
1263 ttm_bo_swapout_all(&dev_priv->bdev);
1264
1265 break;
1266 case PM_POST_HIBERNATION:
1267 case PM_POST_SUSPEND:
1268 case PM_POST_RESTORE:
1269 ttm_suspend_unlock(&dev_priv->reservation_sem);
1270
1271 break;
1272 case PM_RESTORE_PREPARE:
1273 break;
1274 default:
1275 break;
1276 }
1277 return 0;
1278 }
1279
1280 /**
1281 * These might not be needed with the virtual SVGA device.
1282 */
1283
vmw_pci_suspend(struct pci_dev * pdev,pm_message_t state)1284 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1285 {
1286 struct drm_device *dev = pci_get_drvdata(pdev);
1287 struct vmw_private *dev_priv = vmw_priv(dev);
1288
1289 if (dev_priv->num_3d_resources != 0) {
1290 DRM_INFO("Can't suspend or hibernate "
1291 "while 3D resources are active.\n");
1292 return -EBUSY;
1293 }
1294
1295 pci_save_state(pdev);
1296 pci_disable_device(pdev);
1297 pci_set_power_state(pdev, PCI_D3hot);
1298 return 0;
1299 }
1300
vmw_pci_resume(struct pci_dev * pdev)1301 static int vmw_pci_resume(struct pci_dev *pdev)
1302 {
1303 pci_set_power_state(pdev, PCI_D0);
1304 pci_restore_state(pdev);
1305 return pci_enable_device(pdev);
1306 }
1307
vmw_pm_suspend(struct device * kdev)1308 static int vmw_pm_suspend(struct device *kdev)
1309 {
1310 struct pci_dev *pdev = to_pci_dev(kdev);
1311 struct pm_message dummy;
1312
1313 dummy.event = 0;
1314
1315 return vmw_pci_suspend(pdev, dummy);
1316 }
1317
vmw_pm_resume(struct device * kdev)1318 static int vmw_pm_resume(struct device *kdev)
1319 {
1320 struct pci_dev *pdev = to_pci_dev(kdev);
1321
1322 return vmw_pci_resume(pdev);
1323 }
1324
vmw_pm_prepare(struct device * kdev)1325 static int vmw_pm_prepare(struct device *kdev)
1326 {
1327 struct pci_dev *pdev = to_pci_dev(kdev);
1328 struct drm_device *dev = pci_get_drvdata(pdev);
1329 struct vmw_private *dev_priv = vmw_priv(dev);
1330
1331 /**
1332 * Release 3d reference held by fbdev and potentially
1333 * stop fifo.
1334 */
1335 dev_priv->suspended = true;
1336 if (dev_priv->enable_fb)
1337 vmw_3d_resource_dec(dev_priv, true);
1338
1339 if (dev_priv->num_3d_resources != 0) {
1340
1341 DRM_INFO("Can't suspend or hibernate "
1342 "while 3D resources are active.\n");
1343
1344 if (dev_priv->enable_fb)
1345 vmw_3d_resource_inc(dev_priv, true);
1346 dev_priv->suspended = false;
1347 return -EBUSY;
1348 }
1349
1350 return 0;
1351 }
1352
vmw_pm_complete(struct device * kdev)1353 static void vmw_pm_complete(struct device *kdev)
1354 {
1355 struct pci_dev *pdev = to_pci_dev(kdev);
1356 struct drm_device *dev = pci_get_drvdata(pdev);
1357 struct vmw_private *dev_priv = vmw_priv(dev);
1358
1359 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1360 (void) vmw_read(dev_priv, SVGA_REG_ID);
1361
1362 /**
1363 * Reclaim 3d reference held by fbdev and potentially
1364 * start fifo.
1365 */
1366 if (dev_priv->enable_fb)
1367 vmw_3d_resource_inc(dev_priv, false);
1368
1369 dev_priv->suspended = false;
1370 }
1371
1372 static const struct dev_pm_ops vmw_pm_ops = {
1373 .prepare = vmw_pm_prepare,
1374 .complete = vmw_pm_complete,
1375 .suspend = vmw_pm_suspend,
1376 .resume = vmw_pm_resume,
1377 };
1378
1379 static const struct file_operations vmwgfx_driver_fops = {
1380 .owner = THIS_MODULE,
1381 .open = drm_open,
1382 .release = drm_release,
1383 .unlocked_ioctl = vmw_unlocked_ioctl,
1384 .mmap = vmw_mmap,
1385 .poll = vmw_fops_poll,
1386 .read = vmw_fops_read,
1387 #if defined(CONFIG_COMPAT)
1388 .compat_ioctl = vmw_compat_ioctl,
1389 #endif
1390 .llseek = noop_llseek,
1391 };
1392
1393 static struct drm_driver driver = {
1394 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1395 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1396 .load = vmw_driver_load,
1397 .unload = vmw_driver_unload,
1398 .lastclose = vmw_lastclose,
1399 .irq_preinstall = vmw_irq_preinstall,
1400 .irq_postinstall = vmw_irq_postinstall,
1401 .irq_uninstall = vmw_irq_uninstall,
1402 .irq_handler = vmw_irq_handler,
1403 .get_vblank_counter = vmw_get_vblank_counter,
1404 .enable_vblank = vmw_enable_vblank,
1405 .disable_vblank = vmw_disable_vblank,
1406 .ioctls = vmw_ioctls,
1407 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1408 .master_create = vmw_master_create,
1409 .master_destroy = vmw_master_destroy,
1410 .master_set = vmw_master_set,
1411 .master_drop = vmw_master_drop,
1412 .open = vmw_driver_open,
1413 .preclose = vmw_preclose,
1414 .postclose = vmw_postclose,
1415 .set_busid = drm_pci_set_busid,
1416
1417 .dumb_create = vmw_dumb_create,
1418 .dumb_map_offset = vmw_dumb_map_offset,
1419 .dumb_destroy = vmw_dumb_destroy,
1420
1421 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1422 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1423
1424 .fops = &vmwgfx_driver_fops,
1425 .name = VMWGFX_DRIVER_NAME,
1426 .desc = VMWGFX_DRIVER_DESC,
1427 .date = VMWGFX_DRIVER_DATE,
1428 .major = VMWGFX_DRIVER_MAJOR,
1429 .minor = VMWGFX_DRIVER_MINOR,
1430 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1431 };
1432
1433 static struct pci_driver vmw_pci_driver = {
1434 .name = VMWGFX_DRIVER_NAME,
1435 .id_table = vmw_pci_id_list,
1436 .probe = vmw_probe,
1437 .remove = vmw_remove,
1438 .driver = {
1439 .pm = &vmw_pm_ops
1440 }
1441 };
1442
vmw_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1443 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1444 {
1445 return drm_get_pci_dev(pdev, ent, &driver);
1446 }
1447
vmwgfx_init(void)1448 static int __init vmwgfx_init(void)
1449 {
1450 int ret;
1451
1452 #ifdef CONFIG_VGA_CONSOLE
1453 if (vgacon_text_force())
1454 return -EINVAL;
1455 #endif
1456
1457 ret = drm_pci_init(&driver, &vmw_pci_driver);
1458 if (ret)
1459 DRM_ERROR("Failed initializing DRM.\n");
1460 return ret;
1461 }
1462
vmwgfx_exit(void)1463 static void __exit vmwgfx_exit(void)
1464 {
1465 drm_pci_exit(&driver, &vmw_pci_driver);
1466 }
1467
1468 module_init(vmwgfx_init);
1469 module_exit(vmwgfx_exit);
1470
1471 MODULE_AUTHOR("VMware Inc. and others");
1472 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1473 MODULE_LICENSE("GPL and additional rights");
1474 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1475 __stringify(VMWGFX_DRIVER_MINOR) "."
1476 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1477 "0");
1478