1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include <linux/string.h>
29 #include <linux/bitops.h>
30 #include <drm/drmP.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33
34 /** @file i915_gem_tiling.c
35 *
36 * Support for managing tiling state of buffer objects.
37 *
38 * The idea behind tiling is to increase cache hit rates by rearranging
39 * pixel data so that a group of pixel accesses are in the same cacheline.
40 * Performance improvement from doing this on the back/depth buffer are on
41 * the order of 30%.
42 *
43 * Intel architectures make this somewhat more complicated, though, by
44 * adjustments made to addressing of data when the memory is in interleaved
45 * mode (matched pairs of DIMMS) to improve memory bandwidth.
46 * For interleaved memory, the CPU sends every sequential 64 bytes
47 * to an alternate memory channel so it can get the bandwidth from both.
48 *
49 * The GPU also rearranges its accesses for increased bandwidth to interleaved
50 * memory, and it matches what the CPU does for non-tiled. However, when tiled
51 * it does it a little differently, since one walks addresses not just in the
52 * X direction but also Y. So, along with alternating channels when bit
53 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
54 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
55 * are common to both the 915 and 965-class hardware.
56 *
57 * The CPU also sometimes XORs in higher bits as well, to improve
58 * bandwidth doing strided access like we do so frequently in graphics. This
59 * is called "Channel XOR Randomization" in the MCH documentation. The result
60 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
61 * decode.
62 *
63 * All of this bit 6 XORing has an effect on our memory management,
64 * as we need to make sure that the 3d driver can correctly address object
65 * contents.
66 *
67 * If we don't have interleaved memory, all tiling is safe and no swizzling is
68 * required.
69 *
70 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
71 * 17 is not just a page offset, so as we page an objet out and back in,
72 * individual pages in it will have different bit 17 addresses, resulting in
73 * each 64 bytes being swapped with its neighbor!
74 *
75 * Otherwise, if interleaved, we have to tell the 3d driver what the address
76 * swizzling it needs to do is, since it's writing with the CPU to the pages
77 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
78 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
79 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
80 * to match what the GPU expects.
81 */
82
83 /**
84 * Detects bit 6 swizzling of address lookup between IGD access and CPU
85 * access through main memory.
86 */
87 void
i915_gem_detect_bit_6_swizzle(struct drm_device * dev)88 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
89 {
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
92 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
93
94 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
95 /*
96 * On BDW+, swizzling is not used. We leave the CPU memory
97 * controller in charge of optimizing memory accesses without
98 * the extra address manipulation GPU side.
99 *
100 * VLV and CHV don't have GPU swizzling.
101 */
102 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
103 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
104 } else if (INTEL_INFO(dev)->gen >= 6) {
105 uint32_t dimm_c0, dimm_c1;
106 dimm_c0 = I915_READ(MAD_DIMM_C0);
107 dimm_c1 = I915_READ(MAD_DIMM_C1);
108 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
109 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
110 /* Enable swizzling when the channels are populated with
111 * identically sized dimms. We don't need to check the 3rd
112 * channel because no cpu with gpu attached ships in that
113 * configuration. Also, swizzling only makes sense for 2
114 * channels anyway. */
115 if (dimm_c0 == dimm_c1) {
116 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
117 swizzle_y = I915_BIT_6_SWIZZLE_9;
118 } else {
119 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
120 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
121 }
122 } else if (IS_GEN5(dev)) {
123 /* On Ironlake whatever DRAM config, GPU always do
124 * same swizzling setup.
125 */
126 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
127 swizzle_y = I915_BIT_6_SWIZZLE_9;
128 } else if (IS_GEN2(dev)) {
129 /* As far as we know, the 865 doesn't have these bit 6
130 * swizzling issues.
131 */
132 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
133 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
134 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
135 uint32_t dcc;
136
137 /* On 9xx chipsets, channel interleave by the CPU is
138 * determined by DCC. For single-channel, neither the CPU
139 * nor the GPU do swizzling. For dual channel interleaved,
140 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
141 * 9 for Y tiled. The CPU's interleave is independent, and
142 * can be based on either bit 11 (haven't seen this yet) or
143 * bit 17 (common).
144 */
145 dcc = I915_READ(DCC);
146 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
147 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
148 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
149 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
150 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
151 break;
152 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
153 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
154 /* This is the base swizzling by the GPU for
155 * tiled buffers.
156 */
157 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
158 swizzle_y = I915_BIT_6_SWIZZLE_9;
159 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
160 /* Bit 11 swizzling by the CPU in addition. */
161 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
162 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
163 } else {
164 /* Bit 17 swizzling by the CPU in addition. */
165 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
166 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
167 }
168 break;
169 }
170 if (dcc == 0xffffffff) {
171 DRM_ERROR("Couldn't read from MCHBAR. "
172 "Disabling tiling.\n");
173 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
174 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
175 }
176 } else {
177 /* The 965, G33, and newer, have a very flexible memory
178 * configuration. It will enable dual-channel mode
179 * (interleaving) on as much memory as it can, and the GPU
180 * will additionally sometimes enable different bit 6
181 * swizzling for tiled objects from the CPU.
182 *
183 * Here's what I found on the G965:
184 * slot fill memory size swizzling
185 * 0A 0B 1A 1B 1-ch 2-ch
186 * 512 0 0 0 512 0 O
187 * 512 0 512 0 16 1008 X
188 * 512 0 0 512 16 1008 X
189 * 0 512 0 512 16 1008 X
190 * 1024 1024 1024 0 2048 1024 O
191 *
192 * We could probably detect this based on either the DRB
193 * matching, which was the case for the swizzling required in
194 * the table above, or from the 1-ch value being less than
195 * the minimum size of a rank.
196 */
197 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
198 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
199 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
200 } else {
201 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
202 swizzle_y = I915_BIT_6_SWIZZLE_9;
203 }
204 }
205
206 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
207 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
208 }
209
210 /* Check pitch constriants for all chips & tiling formats */
211 static bool
i915_tiling_ok(struct drm_device * dev,int stride,int size,int tiling_mode)212 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
213 {
214 int tile_width;
215
216 /* Linear is always fine */
217 if (tiling_mode == I915_TILING_NONE)
218 return true;
219
220 if (IS_GEN2(dev) ||
221 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
222 tile_width = 128;
223 else
224 tile_width = 512;
225
226 /* check maximum stride & object size */
227 /* i965+ stores the end address of the gtt mapping in the fence
228 * reg, so dont bother to check the size */
229 if (INTEL_INFO(dev)->gen >= 7) {
230 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
231 return false;
232 } else if (INTEL_INFO(dev)->gen >= 4) {
233 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
234 return false;
235 } else {
236 if (stride > 8192)
237 return false;
238
239 if (IS_GEN3(dev)) {
240 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
241 return false;
242 } else {
243 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
244 return false;
245 }
246 }
247
248 if (stride < tile_width)
249 return false;
250
251 /* 965+ just needs multiples of tile width */
252 if (INTEL_INFO(dev)->gen >= 4) {
253 if (stride & (tile_width - 1))
254 return false;
255 return true;
256 }
257
258 /* Pre-965 needs power of two tile widths */
259 if (stride & (stride - 1))
260 return false;
261
262 return true;
263 }
264
265 /* Is the current GTT allocation valid for the change in tiling? */
266 static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object * obj,int tiling_mode)267 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
268 {
269 u32 size;
270
271 if (tiling_mode == I915_TILING_NONE)
272 return true;
273
274 if (INTEL_INFO(obj->base.dev)->gen >= 4)
275 return true;
276
277 if (INTEL_INFO(obj->base.dev)->gen == 3) {
278 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
279 return false;
280 } else {
281 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
282 return false;
283 }
284
285 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
286 if (i915_gem_obj_ggtt_size(obj) != size)
287 return false;
288
289 if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
290 return false;
291
292 return true;
293 }
294
295 /**
296 * Sets the tiling mode of an object, returning the required swizzling of
297 * bit 6 of addresses in the object.
298 */
299 int
i915_gem_set_tiling(struct drm_device * dev,void * data,struct drm_file * file)300 i915_gem_set_tiling(struct drm_device *dev, void *data,
301 struct drm_file *file)
302 {
303 struct drm_i915_gem_set_tiling *args = data;
304 struct drm_i915_private *dev_priv = dev->dev_private;
305 struct drm_i915_gem_object *obj;
306 int ret = 0;
307
308 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
309 if (&obj->base == NULL)
310 return -ENOENT;
311
312 if (!i915_tiling_ok(dev,
313 args->stride, obj->base.size, args->tiling_mode)) {
314 drm_gem_object_unreference_unlocked(&obj->base);
315 return -EINVAL;
316 }
317
318 mutex_lock(&dev->struct_mutex);
319 if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
320 ret = -EBUSY;
321 goto err;
322 }
323
324 if (args->tiling_mode == I915_TILING_NONE) {
325 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
326 args->stride = 0;
327 } else {
328 if (args->tiling_mode == I915_TILING_X)
329 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
330 else
331 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
332
333 /* Hide bit 17 swizzling from the user. This prevents old Mesa
334 * from aborting the application on sw fallbacks to bit 17,
335 * and we use the pread/pwrite bit17 paths to swizzle for it.
336 * If there was a user that was relying on the swizzle
337 * information for drm_intel_bo_map()ed reads/writes this would
338 * break it, but we don't have any of those.
339 */
340 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
341 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
342 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
343 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
344
345 /* If we can't handle the swizzling, make it untiled. */
346 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
347 args->tiling_mode = I915_TILING_NONE;
348 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
349 args->stride = 0;
350 }
351 }
352
353 if (args->tiling_mode != obj->tiling_mode ||
354 args->stride != obj->stride) {
355 /* We need to rebind the object if its current allocation
356 * no longer meets the alignment restrictions for its new
357 * tiling mode. Otherwise we can just leave it alone, but
358 * need to ensure that any fence register is updated before
359 * the next fenced (either through the GTT or by the BLT unit
360 * on older GPUs) access.
361 *
362 * After updating the tiling parameters, we then flag whether
363 * we need to update an associated fence register. Note this
364 * has to also include the unfenced register the GPU uses
365 * whilst executing a fenced command for an untiled object.
366 */
367 if (obj->map_and_fenceable &&
368 !i915_gem_object_fence_ok(obj, args->tiling_mode))
369 ret = i915_gem_object_ggtt_unbind(obj);
370
371 if (ret == 0) {
372 obj->fence_dirty =
373 obj->last_fenced_seqno ||
374 obj->fence_reg != I915_FENCE_REG_NONE;
375
376 obj->tiling_mode = args->tiling_mode;
377 obj->stride = args->stride;
378
379 /* Force the fence to be reacquired for GTT access */
380 i915_gem_release_mmap(obj);
381 }
382 }
383 /* we have to maintain this existing ABI... */
384 args->stride = obj->stride;
385 args->tiling_mode = obj->tiling_mode;
386
387 /* Try to preallocate memory required to save swizzling on put-pages */
388 if (i915_gem_object_needs_bit17_swizzle(obj)) {
389 if (obj->bit_17 == NULL) {
390 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
391 sizeof(long), GFP_KERNEL);
392 }
393 } else {
394 kfree(obj->bit_17);
395 obj->bit_17 = NULL;
396 }
397
398 err:
399 drm_gem_object_unreference(&obj->base);
400 mutex_unlock(&dev->struct_mutex);
401
402 return ret;
403 }
404
405 /**
406 * Returns the current tiling mode and required bit 6 swizzling for the object.
407 */
408 int
i915_gem_get_tiling(struct drm_device * dev,void * data,struct drm_file * file)409 i915_gem_get_tiling(struct drm_device *dev, void *data,
410 struct drm_file *file)
411 {
412 struct drm_i915_gem_get_tiling *args = data;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 struct drm_i915_gem_object *obj;
415
416 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
417 if (&obj->base == NULL)
418 return -ENOENT;
419
420 mutex_lock(&dev->struct_mutex);
421
422 args->tiling_mode = obj->tiling_mode;
423 switch (obj->tiling_mode) {
424 case I915_TILING_X:
425 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
426 break;
427 case I915_TILING_Y:
428 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
429 break;
430 case I915_TILING_NONE:
431 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
432 break;
433 default:
434 DRM_ERROR("unknown tiling mode\n");
435 }
436
437 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
438 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
439 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
440 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
441 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
442
443 drm_gem_object_unreference(&obj->base);
444 mutex_unlock(&dev->struct_mutex);
445
446 return 0;
447 }
448
449 /**
450 * Swap every 64 bytes of this page around, to account for it having a new
451 * bit 17 of its physical address and therefore being interpreted differently
452 * by the GPU.
453 */
454 static void
i915_gem_swizzle_page(struct page * page)455 i915_gem_swizzle_page(struct page *page)
456 {
457 char temp[64];
458 char *vaddr;
459 int i;
460
461 vaddr = kmap(page);
462
463 for (i = 0; i < PAGE_SIZE; i += 128) {
464 memcpy(temp, &vaddr[i], 64);
465 memcpy(&vaddr[i], &vaddr[i + 64], 64);
466 memcpy(&vaddr[i + 64], temp, 64);
467 }
468
469 kunmap(page);
470 }
471
472 void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object * obj)473 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
474 {
475 struct sg_page_iter sg_iter;
476 int i;
477
478 if (obj->bit_17 == NULL)
479 return;
480
481 i = 0;
482 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
483 struct page *page = sg_page_iter_page(&sg_iter);
484 char new_bit_17 = page_to_phys(page) >> 17;
485 if ((new_bit_17 & 0x1) !=
486 (test_bit(i, obj->bit_17) != 0)) {
487 i915_gem_swizzle_page(page);
488 set_page_dirty(page);
489 }
490 i++;
491 }
492 }
493
494 void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object * obj)495 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
496 {
497 struct sg_page_iter sg_iter;
498 int page_count = obj->base.size >> PAGE_SHIFT;
499 int i;
500
501 if (obj->bit_17 == NULL) {
502 obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
503 sizeof(long), GFP_KERNEL);
504 if (obj->bit_17 == NULL) {
505 DRM_ERROR("Failed to allocate memory for bit 17 "
506 "record\n");
507 return;
508 }
509 }
510
511 i = 0;
512 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
513 if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
514 __set_bit(i, obj->bit_17);
515 else
516 __clear_bit(i, obj->bit_17);
517 i++;
518 }
519 }
520