1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kprobes.h>
12 #include <linux/kgdb.h>
13 #include <linux/smp.h>
14 #include <linux/io.h>
15
16 #include <asm/stackprotector.h>
17 #include <asm/perf_event.h>
18 #include <asm/mmu_context.h>
19 #include <asm/archrandom.h>
20 #include <asm/hypervisor.h>
21 #include <asm/processor.h>
22 #include <asm/tlbflush.h>
23 #include <asm/debugreg.h>
24 #include <asm/sections.h>
25 #include <asm/vsyscall.h>
26 #include <linux/topology.h>
27 #include <linux/cpumask.h>
28 #include <asm/pgtable.h>
29 #include <linux/atomic.h>
30 #include <asm/proto.h>
31 #include <asm/setup.h>
32 #include <asm/apic.h>
33 #include <asm/desc.h>
34 #include <asm/i387.h>
35 #include <asm/fpu-internal.h>
36 #include <asm/mtrr.h>
37 #include <linux/numa.h>
38 #include <asm/asm.h>
39 #include <asm/cpu.h>
40 #include <asm/mce.h>
41 #include <asm/msr.h>
42 #include <asm/pat.h>
43 #include <asm/microcode.h>
44 #include <asm/microcode_intel.h>
45
46 #ifdef CONFIG_X86_LOCAL_APIC
47 #include <asm/uv/uv.h>
48 #endif
49
50 #include "cpu.h"
51
52 /* all of these masks are initialized in setup_cpu_local_masks() */
53 cpumask_var_t cpu_initialized_mask;
54 cpumask_var_t cpu_callout_mask;
55 cpumask_var_t cpu_callin_mask;
56
57 /* representing cpus for which sibling maps can be computed */
58 cpumask_var_t cpu_sibling_setup_mask;
59
60 /* correctly size the local cpu masks */
setup_cpu_local_masks(void)61 void __init setup_cpu_local_masks(void)
62 {
63 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
64 alloc_bootmem_cpumask_var(&cpu_callin_mask);
65 alloc_bootmem_cpumask_var(&cpu_callout_mask);
66 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
67 }
68
default_init(struct cpuinfo_x86 * c)69 static void default_init(struct cpuinfo_x86 *c)
70 {
71 #ifdef CONFIG_X86_64
72 cpu_detect_cache_sizes(c);
73 #else
74 /* Not much we can do here... */
75 /* Check if at least it has cpuid */
76 if (c->cpuid_level == -1) {
77 /* No cpuid. It must be an ancient CPU */
78 if (c->x86 == 4)
79 strcpy(c->x86_model_id, "486");
80 else if (c->x86 == 3)
81 strcpy(c->x86_model_id, "386");
82 }
83 #endif
84 }
85
86 static const struct cpu_dev default_cpu = {
87 .c_init = default_init,
88 .c_vendor = "Unknown",
89 .c_x86_vendor = X86_VENDOR_UNKNOWN,
90 };
91
92 static const struct cpu_dev *this_cpu = &default_cpu;
93
94 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
95 #ifdef CONFIG_X86_64
96 /*
97 * We need valid kernel segments for data and code in long mode too
98 * IRET will check the segment types kkeil 2000/10/28
99 * Also sysret mandates a special GDT layout
100 *
101 * TLS descriptors are currently at a different place compared to i386.
102 * Hopefully nobody expects them at a fixed place (Wine?)
103 */
104 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
106 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
108 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
109 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
110 #else
111 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
112 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
113 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
114 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
115 /*
116 * Segments used for calling PnP BIOS have byte granularity.
117 * They code segments and data segments have fixed 64k limits,
118 * the transfer segment sizes are set at run time.
119 */
120 /* 32-bit code */
121 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
122 /* 16-bit code */
123 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
124 /* 16-bit data */
125 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
126 /* 16-bit data */
127 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
128 /* 16-bit data */
129 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
130 /*
131 * The APM segments have byte granularity and their bases
132 * are set at run time. All have 64k limits.
133 */
134 /* 32-bit code */
135 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
136 /* 16-bit code */
137 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
138 /* data */
139 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
140
141 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
142 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143 GDT_STACK_CANARY_INIT
144 #endif
145 } };
146 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
147
x86_xsave_setup(char * s)148 static int __init x86_xsave_setup(char *s)
149 {
150 if (strlen(s))
151 return 0;
152 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
154 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
155 setup_clear_cpu_cap(X86_FEATURE_AVX);
156 setup_clear_cpu_cap(X86_FEATURE_AVX2);
157 return 1;
158 }
159 __setup("noxsave", x86_xsave_setup);
160
x86_xsaveopt_setup(char * s)161 static int __init x86_xsaveopt_setup(char *s)
162 {
163 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
164 return 1;
165 }
166 __setup("noxsaveopt", x86_xsaveopt_setup);
167
x86_xsaves_setup(char * s)168 static int __init x86_xsaves_setup(char *s)
169 {
170 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
171 return 1;
172 }
173 __setup("noxsaves", x86_xsaves_setup);
174
175 #ifdef CONFIG_X86_32
176 static int cachesize_override = -1;
177 static int disable_x86_serial_nr = 1;
178
cachesize_setup(char * str)179 static int __init cachesize_setup(char *str)
180 {
181 get_option(&str, &cachesize_override);
182 return 1;
183 }
184 __setup("cachesize=", cachesize_setup);
185
x86_fxsr_setup(char * s)186 static int __init x86_fxsr_setup(char *s)
187 {
188 setup_clear_cpu_cap(X86_FEATURE_FXSR);
189 setup_clear_cpu_cap(X86_FEATURE_XMM);
190 return 1;
191 }
192 __setup("nofxsr", x86_fxsr_setup);
193
x86_sep_setup(char * s)194 static int __init x86_sep_setup(char *s)
195 {
196 setup_clear_cpu_cap(X86_FEATURE_SEP);
197 return 1;
198 }
199 __setup("nosep", x86_sep_setup);
200
201 /* Standard macro to see if a specific flag is changeable */
flag_is_changeable_p(u32 flag)202 static inline int flag_is_changeable_p(u32 flag)
203 {
204 u32 f1, f2;
205
206 /*
207 * Cyrix and IDT cpus allow disabling of CPUID
208 * so the code below may return different results
209 * when it is executed before and after enabling
210 * the CPUID. Add "volatile" to not allow gcc to
211 * optimize the subsequent calls to this function.
212 */
213 asm volatile ("pushfl \n\t"
214 "pushfl \n\t"
215 "popl %0 \n\t"
216 "movl %0, %1 \n\t"
217 "xorl %2, %0 \n\t"
218 "pushl %0 \n\t"
219 "popfl \n\t"
220 "pushfl \n\t"
221 "popl %0 \n\t"
222 "popfl \n\t"
223
224 : "=&r" (f1), "=&r" (f2)
225 : "ir" (flag));
226
227 return ((f1^f2) & flag) != 0;
228 }
229
230 /* Probe for the CPUID instruction */
have_cpuid_p(void)231 int have_cpuid_p(void)
232 {
233 return flag_is_changeable_p(X86_EFLAGS_ID);
234 }
235
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)236 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
237 {
238 unsigned long lo, hi;
239
240 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
241 return;
242
243 /* Disable processor serial number: */
244
245 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
246 lo |= 0x200000;
247 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
248
249 printk(KERN_NOTICE "CPU serial number disabled.\n");
250 clear_cpu_cap(c, X86_FEATURE_PN);
251
252 /* Disabling the serial number may affect the cpuid level */
253 c->cpuid_level = cpuid_eax(0);
254 }
255
x86_serial_nr_setup(char * s)256 static int __init x86_serial_nr_setup(char *s)
257 {
258 disable_x86_serial_nr = 0;
259 return 1;
260 }
261 __setup("serialnumber", x86_serial_nr_setup);
262 #else
flag_is_changeable_p(u32 flag)263 static inline int flag_is_changeable_p(u32 flag)
264 {
265 return 1;
266 }
squash_the_stupid_serial_number(struct cpuinfo_x86 * c)267 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
268 {
269 }
270 #endif
271
setup_disable_smep(char * arg)272 static __init int setup_disable_smep(char *arg)
273 {
274 setup_clear_cpu_cap(X86_FEATURE_SMEP);
275 return 1;
276 }
277 __setup("nosmep", setup_disable_smep);
278
setup_smep(struct cpuinfo_x86 * c)279 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
280 {
281 if (cpu_has(c, X86_FEATURE_SMEP))
282 cr4_set_bits(X86_CR4_SMEP);
283 }
284
setup_disable_smap(char * arg)285 static __init int setup_disable_smap(char *arg)
286 {
287 setup_clear_cpu_cap(X86_FEATURE_SMAP);
288 return 1;
289 }
290 __setup("nosmap", setup_disable_smap);
291
setup_smap(struct cpuinfo_x86 * c)292 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
293 {
294 unsigned long eflags = native_save_fl();
295
296 /* This should have been cleared long ago */
297 BUG_ON(eflags & X86_EFLAGS_AC);
298
299 if (cpu_has(c, X86_FEATURE_SMAP)) {
300 #ifdef CONFIG_X86_SMAP
301 cr4_set_bits(X86_CR4_SMAP);
302 #else
303 cr4_clear_bits(X86_CR4_SMAP);
304 #endif
305 }
306 }
307
308 /*
309 * Some CPU features depend on higher CPUID levels, which may not always
310 * be available due to CPUID level capping or broken virtualization
311 * software. Add those features to this table to auto-disable them.
312 */
313 struct cpuid_dependent_feature {
314 u32 feature;
315 u32 level;
316 };
317
318 static const struct cpuid_dependent_feature
319 cpuid_dependent_features[] = {
320 { X86_FEATURE_MWAIT, 0x00000005 },
321 { X86_FEATURE_DCA, 0x00000009 },
322 { X86_FEATURE_XSAVE, 0x0000000d },
323 { 0, 0 }
324 };
325
filter_cpuid_features(struct cpuinfo_x86 * c,bool warn)326 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
327 {
328 const struct cpuid_dependent_feature *df;
329
330 for (df = cpuid_dependent_features; df->feature; df++) {
331
332 if (!cpu_has(c, df->feature))
333 continue;
334 /*
335 * Note: cpuid_level is set to -1 if unavailable, but
336 * extended_extended_level is set to 0 if unavailable
337 * and the legitimate extended levels are all negative
338 * when signed; hence the weird messing around with
339 * signs here...
340 */
341 if (!((s32)df->level < 0 ?
342 (u32)df->level > (u32)c->extended_cpuid_level :
343 (s32)df->level > (s32)c->cpuid_level))
344 continue;
345
346 clear_cpu_cap(c, df->feature);
347 if (!warn)
348 continue;
349
350 printk(KERN_WARNING
351 "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
352 x86_cap_flag(df->feature), df->level);
353 }
354 }
355
356 /*
357 * Naming convention should be: <Name> [(<Codename>)]
358 * This table only is used unless init_<vendor>() below doesn't set it;
359 * in particular, if CPUID levels 0x80000002..4 are supported, this
360 * isn't used
361 */
362
363 /* Look up CPU names by table lookup. */
table_lookup_model(struct cpuinfo_x86 * c)364 static const char *table_lookup_model(struct cpuinfo_x86 *c)
365 {
366 #ifdef CONFIG_X86_32
367 const struct legacy_cpu_model_info *info;
368
369 if (c->x86_model >= 16)
370 return NULL; /* Range check */
371
372 if (!this_cpu)
373 return NULL;
374
375 info = this_cpu->legacy_models;
376
377 while (info->family) {
378 if (info->family == c->x86)
379 return info->model_names[c->x86_model];
380 info++;
381 }
382 #endif
383 return NULL; /* Not found */
384 }
385
386 __u32 cpu_caps_cleared[NCAPINTS];
387 __u32 cpu_caps_set[NCAPINTS];
388
load_percpu_segment(int cpu)389 void load_percpu_segment(int cpu)
390 {
391 #ifdef CONFIG_X86_32
392 loadsegment(fs, __KERNEL_PERCPU);
393 #else
394 loadsegment(gs, 0);
395 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
396 #endif
397 load_stack_canary_segment();
398 }
399
400 /*
401 * Current gdt points %fs at the "master" per-cpu area: after this,
402 * it's on the real one.
403 */
switch_to_new_gdt(int cpu)404 void switch_to_new_gdt(int cpu)
405 {
406 struct desc_ptr gdt_descr;
407
408 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
409 gdt_descr.size = GDT_SIZE - 1;
410 load_gdt(&gdt_descr);
411 /* Reload the per-cpu base */
412
413 load_percpu_segment(cpu);
414 }
415
416 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
417
get_model_name(struct cpuinfo_x86 * c)418 static void get_model_name(struct cpuinfo_x86 *c)
419 {
420 unsigned int *v;
421 char *p, *q;
422
423 if (c->extended_cpuid_level < 0x80000004)
424 return;
425
426 v = (unsigned int *)c->x86_model_id;
427 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
428 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
429 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
430 c->x86_model_id[48] = 0;
431
432 /*
433 * Intel chips right-justify this string for some dumb reason;
434 * undo that brain damage:
435 */
436 p = q = &c->x86_model_id[0];
437 while (*p == ' ')
438 p++;
439 if (p != q) {
440 while (*p)
441 *q++ = *p++;
442 while (q <= &c->x86_model_id[48])
443 *q++ = '\0'; /* Zero-pad the rest */
444 }
445 }
446
cpu_detect_cache_sizes(struct cpuinfo_x86 * c)447 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
448 {
449 unsigned int n, dummy, ebx, ecx, edx, l2size;
450
451 n = c->extended_cpuid_level;
452
453 if (n >= 0x80000005) {
454 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
455 c->x86_cache_size = (ecx>>24) + (edx>>24);
456 #ifdef CONFIG_X86_64
457 /* On K8 L1 TLB is inclusive, so don't count it */
458 c->x86_tlbsize = 0;
459 #endif
460 }
461
462 if (n < 0x80000006) /* Some chips just has a large L1. */
463 return;
464
465 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
466 l2size = ecx >> 16;
467
468 #ifdef CONFIG_X86_64
469 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
470 #else
471 /* do processor-specific cache resizing */
472 if (this_cpu->legacy_cache_size)
473 l2size = this_cpu->legacy_cache_size(c, l2size);
474
475 /* Allow user to override all this if necessary. */
476 if (cachesize_override != -1)
477 l2size = cachesize_override;
478
479 if (l2size == 0)
480 return; /* Again, no L2 cache is possible */
481 #endif
482
483 c->x86_cache_size = l2size;
484 }
485
486 u16 __read_mostly tlb_lli_4k[NR_INFO];
487 u16 __read_mostly tlb_lli_2m[NR_INFO];
488 u16 __read_mostly tlb_lli_4m[NR_INFO];
489 u16 __read_mostly tlb_lld_4k[NR_INFO];
490 u16 __read_mostly tlb_lld_2m[NR_INFO];
491 u16 __read_mostly tlb_lld_4m[NR_INFO];
492 u16 __read_mostly tlb_lld_1g[NR_INFO];
493
cpu_detect_tlb(struct cpuinfo_x86 * c)494 void cpu_detect_tlb(struct cpuinfo_x86 *c)
495 {
496 if (this_cpu->c_detect_tlb)
497 this_cpu->c_detect_tlb(c);
498
499 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
500 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
501 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
502 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
503 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
504 tlb_lld_1g[ENTRIES]);
505 }
506
detect_ht(struct cpuinfo_x86 * c)507 void detect_ht(struct cpuinfo_x86 *c)
508 {
509 #ifdef CONFIG_X86_HT
510 u32 eax, ebx, ecx, edx;
511 int index_msb, core_bits;
512 static bool printed;
513
514 if (!cpu_has(c, X86_FEATURE_HT))
515 return;
516
517 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
518 goto out;
519
520 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
521 return;
522
523 cpuid(1, &eax, &ebx, &ecx, &edx);
524
525 smp_num_siblings = (ebx & 0xff0000) >> 16;
526
527 if (smp_num_siblings == 1) {
528 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
529 goto out;
530 }
531
532 if (smp_num_siblings <= 1)
533 goto out;
534
535 index_msb = get_count_order(smp_num_siblings);
536 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
537
538 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
539
540 index_msb = get_count_order(smp_num_siblings);
541
542 core_bits = get_count_order(c->x86_max_cores);
543
544 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
545 ((1 << core_bits) - 1);
546
547 out:
548 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
549 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
550 c->phys_proc_id);
551 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
552 c->cpu_core_id);
553 printed = 1;
554 }
555 #endif
556 }
557
get_cpu_vendor(struct cpuinfo_x86 * c)558 static void get_cpu_vendor(struct cpuinfo_x86 *c)
559 {
560 char *v = c->x86_vendor_id;
561 int i;
562
563 for (i = 0; i < X86_VENDOR_NUM; i++) {
564 if (!cpu_devs[i])
565 break;
566
567 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
568 (cpu_devs[i]->c_ident[1] &&
569 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
570
571 this_cpu = cpu_devs[i];
572 c->x86_vendor = this_cpu->c_x86_vendor;
573 return;
574 }
575 }
576
577 printk_once(KERN_ERR
578 "CPU: vendor_id '%s' unknown, using generic init.\n" \
579 "CPU: Your system may be unstable.\n", v);
580
581 c->x86_vendor = X86_VENDOR_UNKNOWN;
582 this_cpu = &default_cpu;
583 }
584
cpu_detect(struct cpuinfo_x86 * c)585 void cpu_detect(struct cpuinfo_x86 *c)
586 {
587 /* Get vendor name */
588 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
589 (unsigned int *)&c->x86_vendor_id[0],
590 (unsigned int *)&c->x86_vendor_id[8],
591 (unsigned int *)&c->x86_vendor_id[4]);
592
593 c->x86 = 4;
594 /* Intel-defined flags: level 0x00000001 */
595 if (c->cpuid_level >= 0x00000001) {
596 u32 junk, tfms, cap0, misc;
597
598 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
599 c->x86 = (tfms >> 8) & 0xf;
600 c->x86_model = (tfms >> 4) & 0xf;
601 c->x86_mask = tfms & 0xf;
602
603 if (c->x86 == 0xf)
604 c->x86 += (tfms >> 20) & 0xff;
605 if (c->x86 >= 0x6)
606 c->x86_model += ((tfms >> 16) & 0xf) << 4;
607
608 if (cap0 & (1<<19)) {
609 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
610 c->x86_cache_alignment = c->x86_clflush_size;
611 }
612 }
613 }
614
get_cpu_cap(struct cpuinfo_x86 * c)615 void get_cpu_cap(struct cpuinfo_x86 *c)
616 {
617 u32 tfms, xlvl;
618 u32 ebx;
619
620 /* Intel-defined flags: level 0x00000001 */
621 if (c->cpuid_level >= 0x00000001) {
622 u32 capability, excap;
623
624 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
625 c->x86_capability[0] = capability;
626 c->x86_capability[4] = excap;
627 }
628
629 /* Additional Intel-defined flags: level 0x00000007 */
630 if (c->cpuid_level >= 0x00000007) {
631 u32 eax, ebx, ecx, edx;
632
633 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
634
635 c->x86_capability[9] = ebx;
636 }
637
638 /* Extended state features: level 0x0000000d */
639 if (c->cpuid_level >= 0x0000000d) {
640 u32 eax, ebx, ecx, edx;
641
642 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
643
644 c->x86_capability[10] = eax;
645 }
646
647 /* AMD-defined flags: level 0x80000001 */
648 xlvl = cpuid_eax(0x80000000);
649 c->extended_cpuid_level = xlvl;
650
651 if ((xlvl & 0xffff0000) == 0x80000000) {
652 if (xlvl >= 0x80000001) {
653 c->x86_capability[1] = cpuid_edx(0x80000001);
654 c->x86_capability[6] = cpuid_ecx(0x80000001);
655 }
656 }
657
658 if (c->extended_cpuid_level >= 0x80000008) {
659 u32 eax = cpuid_eax(0x80000008);
660
661 c->x86_virt_bits = (eax >> 8) & 0xff;
662 c->x86_phys_bits = eax & 0xff;
663 }
664 #ifdef CONFIG_X86_32
665 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
666 c->x86_phys_bits = 36;
667 #endif
668
669 if (c->extended_cpuid_level >= 0x80000007)
670 c->x86_power = cpuid_edx(0x80000007);
671
672 init_scattered_cpuid_features(c);
673 }
674
identify_cpu_without_cpuid(struct cpuinfo_x86 * c)675 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
676 {
677 #ifdef CONFIG_X86_32
678 int i;
679
680 /*
681 * First of all, decide if this is a 486 or higher
682 * It's a 486 if we can modify the AC flag
683 */
684 if (flag_is_changeable_p(X86_EFLAGS_AC))
685 c->x86 = 4;
686 else
687 c->x86 = 3;
688
689 for (i = 0; i < X86_VENDOR_NUM; i++)
690 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
691 c->x86_vendor_id[0] = 0;
692 cpu_devs[i]->c_identify(c);
693 if (c->x86_vendor_id[0]) {
694 get_cpu_vendor(c);
695 break;
696 }
697 }
698 #endif
699 }
700
701 /*
702 * Do minimum CPU detection early.
703 * Fields really needed: vendor, cpuid_level, family, model, mask,
704 * cache alignment.
705 * The others are not touched to avoid unwanted side effects.
706 *
707 * WARNING: this function is only called on the BP. Don't add code here
708 * that is supposed to run on all CPUs.
709 */
early_identify_cpu(struct cpuinfo_x86 * c)710 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
711 {
712 #ifdef CONFIG_X86_64
713 c->x86_clflush_size = 64;
714 c->x86_phys_bits = 36;
715 c->x86_virt_bits = 48;
716 #else
717 c->x86_clflush_size = 32;
718 c->x86_phys_bits = 32;
719 c->x86_virt_bits = 32;
720 #endif
721 c->x86_cache_alignment = c->x86_clflush_size;
722
723 memset(&c->x86_capability, 0, sizeof c->x86_capability);
724 c->extended_cpuid_level = 0;
725
726 if (!have_cpuid_p())
727 identify_cpu_without_cpuid(c);
728
729 /* cyrix could have cpuid enabled via c_identify()*/
730 if (!have_cpuid_p())
731 return;
732
733 cpu_detect(c);
734 get_cpu_vendor(c);
735 get_cpu_cap(c);
736 fpu_detect(c);
737
738 if (this_cpu->c_early_init)
739 this_cpu->c_early_init(c);
740
741 c->cpu_index = 0;
742 filter_cpuid_features(c, false);
743
744 if (this_cpu->c_bsp_init)
745 this_cpu->c_bsp_init(c);
746
747 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
748 }
749
early_cpu_init(void)750 void __init early_cpu_init(void)
751 {
752 const struct cpu_dev *const *cdev;
753 int count = 0;
754
755 #ifdef CONFIG_PROCESSOR_SELECT
756 printk(KERN_INFO "KERNEL supported cpus:\n");
757 #endif
758
759 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
760 const struct cpu_dev *cpudev = *cdev;
761
762 if (count >= X86_VENDOR_NUM)
763 break;
764 cpu_devs[count] = cpudev;
765 count++;
766
767 #ifdef CONFIG_PROCESSOR_SELECT
768 {
769 unsigned int j;
770
771 for (j = 0; j < 2; j++) {
772 if (!cpudev->c_ident[j])
773 continue;
774 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
775 cpudev->c_ident[j]);
776 }
777 }
778 #endif
779 }
780 early_identify_cpu(&boot_cpu_data);
781 }
782
783 /*
784 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
785 * unfortunately, that's not true in practice because of early VIA
786 * chips and (more importantly) broken virtualizers that are not easy
787 * to detect. In the latter case it doesn't even *fail* reliably, so
788 * probing for it doesn't even work. Disable it completely on 32-bit
789 * unless we can find a reliable way to detect all the broken cases.
790 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
791 */
detect_nopl(struct cpuinfo_x86 * c)792 static void detect_nopl(struct cpuinfo_x86 *c)
793 {
794 #ifdef CONFIG_X86_32
795 clear_cpu_cap(c, X86_FEATURE_NOPL);
796 #else
797 set_cpu_cap(c, X86_FEATURE_NOPL);
798 #endif
799 }
800
generic_identify(struct cpuinfo_x86 * c)801 static void generic_identify(struct cpuinfo_x86 *c)
802 {
803 c->extended_cpuid_level = 0;
804
805 if (!have_cpuid_p())
806 identify_cpu_without_cpuid(c);
807
808 /* cyrix could have cpuid enabled via c_identify()*/
809 if (!have_cpuid_p())
810 return;
811
812 cpu_detect(c);
813
814 get_cpu_vendor(c);
815
816 get_cpu_cap(c);
817
818 if (c->cpuid_level >= 0x00000001) {
819 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
820 #ifdef CONFIG_X86_32
821 # ifdef CONFIG_X86_HT
822 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
823 # else
824 c->apicid = c->initial_apicid;
825 # endif
826 #endif
827 c->phys_proc_id = c->initial_apicid;
828 }
829
830 get_model_name(c); /* Default name */
831
832 detect_nopl(c);
833 }
834
835 /*
836 * This does the hard work of actually picking apart the CPU stuff...
837 */
identify_cpu(struct cpuinfo_x86 * c)838 static void identify_cpu(struct cpuinfo_x86 *c)
839 {
840 int i;
841
842 c->loops_per_jiffy = loops_per_jiffy;
843 c->x86_cache_size = -1;
844 c->x86_vendor = X86_VENDOR_UNKNOWN;
845 c->x86_model = c->x86_mask = 0; /* So far unknown... */
846 c->x86_vendor_id[0] = '\0'; /* Unset */
847 c->x86_model_id[0] = '\0'; /* Unset */
848 c->x86_max_cores = 1;
849 c->x86_coreid_bits = 0;
850 #ifdef CONFIG_X86_64
851 c->x86_clflush_size = 64;
852 c->x86_phys_bits = 36;
853 c->x86_virt_bits = 48;
854 #else
855 c->cpuid_level = -1; /* CPUID not detected */
856 c->x86_clflush_size = 32;
857 c->x86_phys_bits = 32;
858 c->x86_virt_bits = 32;
859 #endif
860 c->x86_cache_alignment = c->x86_clflush_size;
861 memset(&c->x86_capability, 0, sizeof c->x86_capability);
862
863 generic_identify(c);
864
865 if (this_cpu->c_identify)
866 this_cpu->c_identify(c);
867
868 /* Clear/Set all flags overriden by options, after probe */
869 for (i = 0; i < NCAPINTS; i++) {
870 c->x86_capability[i] &= ~cpu_caps_cleared[i];
871 c->x86_capability[i] |= cpu_caps_set[i];
872 }
873
874 #ifdef CONFIG_X86_64
875 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
876 #endif
877
878 /*
879 * Vendor-specific initialization. In this section we
880 * canonicalize the feature flags, meaning if there are
881 * features a certain CPU supports which CPUID doesn't
882 * tell us, CPUID claiming incorrect flags, or other bugs,
883 * we handle them here.
884 *
885 * At the end of this section, c->x86_capability better
886 * indicate the features this CPU genuinely supports!
887 */
888 if (this_cpu->c_init)
889 this_cpu->c_init(c);
890
891 /* Disable the PN if appropriate */
892 squash_the_stupid_serial_number(c);
893
894 /* Set up SMEP/SMAP */
895 setup_smep(c);
896 setup_smap(c);
897
898 /*
899 * The vendor-specific functions might have changed features.
900 * Now we do "generic changes."
901 */
902
903 /* Filter out anything that depends on CPUID levels we don't have */
904 filter_cpuid_features(c, true);
905
906 /* If the model name is still unset, do table lookup. */
907 if (!c->x86_model_id[0]) {
908 const char *p;
909 p = table_lookup_model(c);
910 if (p)
911 strcpy(c->x86_model_id, p);
912 else
913 /* Last resort... */
914 sprintf(c->x86_model_id, "%02x/%02x",
915 c->x86, c->x86_model);
916 }
917
918 #ifdef CONFIG_X86_64
919 detect_ht(c);
920 #endif
921
922 init_hypervisor(c);
923 x86_init_rdrand(c);
924
925 /*
926 * Clear/Set all flags overriden by options, need do it
927 * before following smp all cpus cap AND.
928 */
929 for (i = 0; i < NCAPINTS; i++) {
930 c->x86_capability[i] &= ~cpu_caps_cleared[i];
931 c->x86_capability[i] |= cpu_caps_set[i];
932 }
933
934 /*
935 * On SMP, boot_cpu_data holds the common feature set between
936 * all CPUs; so make sure that we indicate which features are
937 * common between the CPUs. The first time this routine gets
938 * executed, c == &boot_cpu_data.
939 */
940 if (c != &boot_cpu_data) {
941 /* AND the already accumulated flags with these */
942 for (i = 0; i < NCAPINTS; i++)
943 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
944
945 /* OR, i.e. replicate the bug flags */
946 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
947 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
948 }
949
950 /* Init Machine Check Exception if available. */
951 mcheck_cpu_init(c);
952
953 select_idle_routine(c);
954
955 #ifdef CONFIG_NUMA
956 numa_add_cpu(smp_processor_id());
957 #endif
958 }
959
960 #ifdef CONFIG_X86_64
vgetcpu_set_mode(void)961 static void vgetcpu_set_mode(void)
962 {
963 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
964 vgetcpu_mode = VGETCPU_RDTSCP;
965 else
966 vgetcpu_mode = VGETCPU_LSL;
967 }
968
969 #ifdef CONFIG_IA32_EMULATION
970 /* May not be __init: called during resume */
syscall32_cpu_init(void)971 static void syscall32_cpu_init(void)
972 {
973 /* Load these always in case some future AMD CPU supports
974 SYSENTER from compat mode too. */
975 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
976 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
977 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
978
979 wrmsrl(MSR_CSTAR, ia32_cstar_target);
980 }
981 #endif /* CONFIG_IA32_EMULATION */
982 #endif /* CONFIG_X86_64 */
983
984 #ifdef CONFIG_X86_32
enable_sep_cpu(void)985 void enable_sep_cpu(void)
986 {
987 int cpu = get_cpu();
988 struct tss_struct *tss = &per_cpu(init_tss, cpu);
989
990 if (!boot_cpu_has(X86_FEATURE_SEP)) {
991 put_cpu();
992 return;
993 }
994
995 tss->x86_tss.ss1 = __KERNEL_CS;
996 tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss;
997 wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0);
998 wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0);
999 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0);
1000 put_cpu();
1001 }
1002 #endif
1003
identify_boot_cpu(void)1004 void __init identify_boot_cpu(void)
1005 {
1006 identify_cpu(&boot_cpu_data);
1007 init_amd_e400_c1e_mask();
1008 #ifdef CONFIG_X86_32
1009 sysenter_setup();
1010 enable_sep_cpu();
1011 #else
1012 vgetcpu_set_mode();
1013 #endif
1014 cpu_detect_tlb(&boot_cpu_data);
1015 }
1016
identify_secondary_cpu(struct cpuinfo_x86 * c)1017 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1018 {
1019 BUG_ON(c == &boot_cpu_data);
1020 identify_cpu(c);
1021 #ifdef CONFIG_X86_32
1022 enable_sep_cpu();
1023 #endif
1024 mtrr_ap_init();
1025 }
1026
1027 struct msr_range {
1028 unsigned min;
1029 unsigned max;
1030 };
1031
1032 static const struct msr_range msr_range_array[] = {
1033 { 0x00000000, 0x00000418},
1034 { 0xc0000000, 0xc000040b},
1035 { 0xc0010000, 0xc0010142},
1036 { 0xc0011000, 0xc001103b},
1037 };
1038
__print_cpu_msr(void)1039 static void __print_cpu_msr(void)
1040 {
1041 unsigned index_min, index_max;
1042 unsigned index;
1043 u64 val;
1044 int i;
1045
1046 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1047 index_min = msr_range_array[i].min;
1048 index_max = msr_range_array[i].max;
1049
1050 for (index = index_min; index < index_max; index++) {
1051 if (rdmsrl_safe(index, &val))
1052 continue;
1053 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1054 }
1055 }
1056 }
1057
1058 static int show_msr;
1059
setup_show_msr(char * arg)1060 static __init int setup_show_msr(char *arg)
1061 {
1062 int num;
1063
1064 get_option(&arg, &num);
1065
1066 if (num > 0)
1067 show_msr = num;
1068 return 1;
1069 }
1070 __setup("show_msr=", setup_show_msr);
1071
setup_noclflush(char * arg)1072 static __init int setup_noclflush(char *arg)
1073 {
1074 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1075 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1076 return 1;
1077 }
1078 __setup("noclflush", setup_noclflush);
1079
print_cpu_info(struct cpuinfo_x86 * c)1080 void print_cpu_info(struct cpuinfo_x86 *c)
1081 {
1082 const char *vendor = NULL;
1083
1084 if (c->x86_vendor < X86_VENDOR_NUM) {
1085 vendor = this_cpu->c_vendor;
1086 } else {
1087 if (c->cpuid_level >= 0)
1088 vendor = c->x86_vendor_id;
1089 }
1090
1091 if (vendor && !strstr(c->x86_model_id, vendor))
1092 printk(KERN_CONT "%s ", vendor);
1093
1094 if (c->x86_model_id[0])
1095 printk(KERN_CONT "%s", strim(c->x86_model_id));
1096 else
1097 printk(KERN_CONT "%d86", c->x86);
1098
1099 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1100
1101 if (c->x86_mask || c->cpuid_level >= 0)
1102 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1103 else
1104 printk(KERN_CONT ")\n");
1105
1106 print_cpu_msr(c);
1107 }
1108
print_cpu_msr(struct cpuinfo_x86 * c)1109 void print_cpu_msr(struct cpuinfo_x86 *c)
1110 {
1111 if (c->cpu_index < show_msr)
1112 __print_cpu_msr();
1113 }
1114
setup_disablecpuid(char * arg)1115 static __init int setup_disablecpuid(char *arg)
1116 {
1117 int bit;
1118
1119 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1120 setup_clear_cpu_cap(bit);
1121 else
1122 return 0;
1123
1124 return 1;
1125 }
1126 __setup("clearcpuid=", setup_disablecpuid);
1127
1128 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1129 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1130 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1131
1132 #ifdef CONFIG_X86_64
1133 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1134 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1135 (unsigned long) debug_idt_table };
1136
1137 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1138 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1139
1140 /*
1141 * The following four percpu variables are hot. Align current_task to
1142 * cacheline size such that all four fall in the same cacheline.
1143 */
1144 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1145 &init_task;
1146 EXPORT_PER_CPU_SYMBOL(current_task);
1147
1148 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1149 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1150
1151 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1152
1153 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1154 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1155
1156 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1157
1158 /*
1159 * Special IST stacks which the CPU switches to when it calls
1160 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1161 * limit), all of them are 4K, except the debug stack which
1162 * is 8K.
1163 */
1164 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1165 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1166 [DEBUG_STACK - 1] = DEBUG_STKSZ
1167 };
1168
1169 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1170 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1171
1172 /* May not be marked __init: used by software suspend */
syscall_init(void)1173 void syscall_init(void)
1174 {
1175 /*
1176 * LSTAR and STAR live in a bit strange symbiosis.
1177 * They both write to the same internal register. STAR allows to
1178 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1179 */
1180 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1181 wrmsrl(MSR_LSTAR, system_call);
1182 wrmsrl(MSR_CSTAR, ignore_sysret);
1183
1184 #ifdef CONFIG_IA32_EMULATION
1185 syscall32_cpu_init();
1186 #endif
1187
1188 /* Flags to clear on syscall */
1189 wrmsrl(MSR_SYSCALL_MASK,
1190 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1191 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1192 }
1193
1194 /*
1195 * Copies of the original ist values from the tss are only accessed during
1196 * debugging, no special alignment required.
1197 */
1198 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1199
1200 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1201 DEFINE_PER_CPU(int, debug_stack_usage);
1202
is_debug_stack(unsigned long addr)1203 int is_debug_stack(unsigned long addr)
1204 {
1205 return __this_cpu_read(debug_stack_usage) ||
1206 (addr <= __this_cpu_read(debug_stack_addr) &&
1207 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1208 }
1209 NOKPROBE_SYMBOL(is_debug_stack);
1210
1211 DEFINE_PER_CPU(u32, debug_idt_ctr);
1212
debug_stack_set_zero(void)1213 void debug_stack_set_zero(void)
1214 {
1215 this_cpu_inc(debug_idt_ctr);
1216 load_current_idt();
1217 }
1218 NOKPROBE_SYMBOL(debug_stack_set_zero);
1219
debug_stack_reset(void)1220 void debug_stack_reset(void)
1221 {
1222 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1223 return;
1224 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1225 load_current_idt();
1226 }
1227 NOKPROBE_SYMBOL(debug_stack_reset);
1228
1229 #else /* CONFIG_X86_64 */
1230
1231 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1232 EXPORT_PER_CPU_SYMBOL(current_task);
1233 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1234 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1235 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1236
1237 #ifdef CONFIG_CC_STACKPROTECTOR
1238 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1239 #endif
1240
1241 #endif /* CONFIG_X86_64 */
1242
1243 /*
1244 * Clear all 6 debug registers:
1245 */
clear_all_debug_regs(void)1246 static void clear_all_debug_regs(void)
1247 {
1248 int i;
1249
1250 for (i = 0; i < 8; i++) {
1251 /* Ignore db4, db5 */
1252 if ((i == 4) || (i == 5))
1253 continue;
1254
1255 set_debugreg(0, i);
1256 }
1257 }
1258
1259 #ifdef CONFIG_KGDB
1260 /*
1261 * Restore debug regs if using kgdbwait and you have a kernel debugger
1262 * connection established.
1263 */
dbg_restore_debug_regs(void)1264 static void dbg_restore_debug_regs(void)
1265 {
1266 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1267 arch_kgdb_ops.correct_hw_break();
1268 }
1269 #else /* ! CONFIG_KGDB */
1270 #define dbg_restore_debug_regs()
1271 #endif /* ! CONFIG_KGDB */
1272
wait_for_master_cpu(int cpu)1273 static void wait_for_master_cpu(int cpu)
1274 {
1275 #ifdef CONFIG_SMP
1276 /*
1277 * wait for ACK from master CPU before continuing
1278 * with AP initialization
1279 */
1280 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1281 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1282 cpu_relax();
1283 #endif
1284 }
1285
1286 /*
1287 * cpu_init() initializes state that is per-CPU. Some data is already
1288 * initialized (naturally) in the bootstrap process, such as the GDT
1289 * and IDT. We reload them nevertheless, this function acts as a
1290 * 'CPU state barrier', nothing should get across.
1291 * A lot of state is already set up in PDA init for 64 bit
1292 */
1293 #ifdef CONFIG_X86_64
1294
cpu_init(void)1295 void cpu_init(void)
1296 {
1297 struct orig_ist *oist;
1298 struct task_struct *me;
1299 struct tss_struct *t;
1300 unsigned long v;
1301 int cpu = stack_smp_processor_id();
1302 int i;
1303
1304 wait_for_master_cpu(cpu);
1305
1306 /*
1307 * Initialize the CR4 shadow before doing anything that could
1308 * try to read it.
1309 */
1310 cr4_init_shadow();
1311
1312 /*
1313 * Load microcode on this cpu if a valid microcode is available.
1314 * This is early microcode loading procedure.
1315 */
1316 load_ucode_ap();
1317
1318 t = &per_cpu(init_tss, cpu);
1319 oist = &per_cpu(orig_ist, cpu);
1320
1321 #ifdef CONFIG_NUMA
1322 if (this_cpu_read(numa_node) == 0 &&
1323 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1324 set_numa_node(early_cpu_to_node(cpu));
1325 #endif
1326
1327 me = current;
1328
1329 pr_debug("Initializing CPU#%d\n", cpu);
1330
1331 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1332
1333 /*
1334 * Initialize the per-CPU GDT with the boot GDT,
1335 * and set up the GDT descriptor:
1336 */
1337
1338 switch_to_new_gdt(cpu);
1339 loadsegment(fs, 0);
1340
1341 load_current_idt();
1342
1343 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1344 syscall_init();
1345
1346 wrmsrl(MSR_FS_BASE, 0);
1347 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1348 barrier();
1349
1350 x86_configure_nx();
1351 enable_x2apic();
1352
1353 /*
1354 * set up and load the per-CPU TSS
1355 */
1356 if (!oist->ist[0]) {
1357 char *estacks = per_cpu(exception_stacks, cpu);
1358
1359 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1360 estacks += exception_stack_sizes[v];
1361 oist->ist[v] = t->x86_tss.ist[v] =
1362 (unsigned long)estacks;
1363 if (v == DEBUG_STACK-1)
1364 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1365 }
1366 }
1367
1368 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1369
1370 /*
1371 * <= is required because the CPU will access up to
1372 * 8 bits beyond the end of the IO permission bitmap.
1373 */
1374 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1375 t->io_bitmap[i] = ~0UL;
1376
1377 atomic_inc(&init_mm.mm_count);
1378 me->active_mm = &init_mm;
1379 BUG_ON(me->mm);
1380 enter_lazy_tlb(&init_mm, me);
1381
1382 load_sp0(t, ¤t->thread);
1383 set_tss_desc(cpu, t);
1384 load_TR_desc();
1385 load_mm_ldt(&init_mm);
1386
1387 clear_all_debug_regs();
1388 dbg_restore_debug_regs();
1389
1390 fpu_init();
1391
1392 if (is_uv_system())
1393 uv_cpu_init();
1394 }
1395
1396 #else
1397
cpu_init(void)1398 void cpu_init(void)
1399 {
1400 int cpu = smp_processor_id();
1401 struct task_struct *curr = current;
1402 struct tss_struct *t = &per_cpu(init_tss, cpu);
1403 struct thread_struct *thread = &curr->thread;
1404
1405 wait_for_master_cpu(cpu);
1406
1407 /*
1408 * Initialize the CR4 shadow before doing anything that could
1409 * try to read it.
1410 */
1411 cr4_init_shadow();
1412
1413 show_ucode_info_early();
1414
1415 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1416
1417 if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)
1418 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1419
1420 load_current_idt();
1421 switch_to_new_gdt(cpu);
1422
1423 /*
1424 * Set up and load the per-CPU TSS and LDT
1425 */
1426 atomic_inc(&init_mm.mm_count);
1427 curr->active_mm = &init_mm;
1428 BUG_ON(curr->mm);
1429 enter_lazy_tlb(&init_mm, curr);
1430
1431 load_sp0(t, thread);
1432 set_tss_desc(cpu, t);
1433 load_TR_desc();
1434 load_mm_ldt(&init_mm);
1435
1436 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1437
1438 #ifdef CONFIG_DOUBLEFAULT
1439 /* Set up doublefault TSS pointer in the GDT */
1440 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1441 #endif
1442
1443 clear_all_debug_regs();
1444 dbg_restore_debug_regs();
1445
1446 fpu_init();
1447 }
1448 #endif
1449
1450 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
warn_pre_alternatives(void)1451 void warn_pre_alternatives(void)
1452 {
1453 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1454 }
1455 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1456 #endif
1457
__static_cpu_has_safe(u16 bit)1458 inline bool __static_cpu_has_safe(u16 bit)
1459 {
1460 return boot_cpu_has(bit);
1461 }
1462 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
1463