1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
intel_ring_initialized(struct intel_engine_cs * ring)37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
__intel_ring_space(int head,int tail,int size)53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - (tail + I915_RING_FREE_SPACE);
56 if (space < 0)
57 space += size;
58 return space;
59 }
60
intel_ring_space(struct intel_ringbuffer * ringbuf)61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
62 {
63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
65 }
66
intel_ring_stopped(struct intel_engine_cs * ring)67 bool intel_ring_stopped(struct intel_engine_cs *ring)
68 {
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71 }
72
__intel_ring_advance(struct intel_engine_cs * ring)73 void __intel_ring_advance(struct intel_engine_cs *ring)
74 {
75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
77 if (intel_ring_stopped(ring))
78 return;
79 ring->write_tail(ring, ringbuf->tail);
80 }
81
82 static int
gen2_render_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)83 gen2_render_ring_flush(struct intel_engine_cs *ring,
84 u32 invalidate_domains,
85 u32 flush_domains)
86 {
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106 }
107
108 static int
gen4_render_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)109 gen4_render_ring_flush(struct intel_engine_cs *ring,
110 u32 invalidate_domains,
111 u32 flush_domains)
112 {
113 struct drm_device *dev = ring->dev;
114 u32 cmd;
115 int ret;
116
117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
147 cmd &= ~MI_NO_WRITE_FLUSH;
148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
150
151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
154
155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
158
159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
162
163 return 0;
164 }
165
166 /**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203 static int
intel_emit_post_sync_nonzero_flush(struct intel_engine_cs * ring)204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
205 {
206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236 }
237
238 static int
gen6_render_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)239 gen6_render_ring_flush(struct intel_engine_cs *ring,
240 u32 invalidate_domains, u32 flush_domains)
241 {
242 u32 flags = 0;
243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
244 int ret;
245
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
262 flags |= PIPE_CONTROL_CS_STALL;
263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
275 }
276
277 ret = intel_ring_begin(ring, 4);
278 if (ret)
279 return ret;
280
281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
284 intel_ring_emit(ring, 0);
285 intel_ring_advance(ring);
286
287 return 0;
288 }
289
290 static int
gen7_render_ring_cs_stall_wa(struct intel_engine_cs * ring)291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
292 {
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307 }
308
gen7_ring_fbc_flush(struct intel_engine_cs * ring,u32 value)309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
310 {
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
316 ret = intel_ring_begin(ring, 6);
317 if (ret)
318 return ret;
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330 }
331
332 static int
gen7_render_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)333 gen7_render_ring_flush(struct intel_engine_cs *ring,
334 u32 invalidate_domains, u32 flush_domains)
335 {
336 u32 flags = 0;
337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
338 int ret;
339
340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
366 /*
367 * TLB invalidate requires a post-sync write.
368 */
369 flags |= PIPE_CONTROL_QW_WRITE;
370 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
371
372 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
373
374 /* Workaround: we must issue a pipe_control with CS-stall bit
375 * set before a pipe_control command that has the state cache
376 * invalidate bit set. */
377 gen7_render_ring_cs_stall_wa(ring);
378 }
379
380 ret = intel_ring_begin(ring, 4);
381 if (ret)
382 return ret;
383
384 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
385 intel_ring_emit(ring, flags);
386 intel_ring_emit(ring, scratch_addr);
387 intel_ring_emit(ring, 0);
388 intel_ring_advance(ring);
389
390 if (!invalidate_domains && flush_domains)
391 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
392
393 return 0;
394 }
395
396 static int
gen8_emit_pipe_control(struct intel_engine_cs * ring,u32 flags,u32 scratch_addr)397 gen8_emit_pipe_control(struct intel_engine_cs *ring,
398 u32 flags, u32 scratch_addr)
399 {
400 int ret;
401
402 ret = intel_ring_begin(ring, 6);
403 if (ret)
404 return ret;
405
406 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
407 intel_ring_emit(ring, flags);
408 intel_ring_emit(ring, scratch_addr);
409 intel_ring_emit(ring, 0);
410 intel_ring_emit(ring, 0);
411 intel_ring_emit(ring, 0);
412 intel_ring_advance(ring);
413
414 return 0;
415 }
416
417 static int
gen8_render_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)418 gen8_render_ring_flush(struct intel_engine_cs *ring,
419 u32 invalidate_domains, u32 flush_domains)
420 {
421 u32 flags = 0;
422 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
423 int ret;
424
425 flags |= PIPE_CONTROL_CS_STALL;
426
427 if (flush_domains) {
428 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
429 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
430 }
431 if (invalidate_domains) {
432 flags |= PIPE_CONTROL_TLB_INVALIDATE;
433 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
436 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
437 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
438 flags |= PIPE_CONTROL_QW_WRITE;
439 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
440
441 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
442 ret = gen8_emit_pipe_control(ring,
443 PIPE_CONTROL_CS_STALL |
444 PIPE_CONTROL_STALL_AT_SCOREBOARD,
445 0);
446 if (ret)
447 return ret;
448 }
449
450 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
451 if (ret)
452 return ret;
453
454 if (!invalidate_domains && flush_domains)
455 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
456
457 return 0;
458 }
459
ring_write_tail(struct intel_engine_cs * ring,u32 value)460 static void ring_write_tail(struct intel_engine_cs *ring,
461 u32 value)
462 {
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 I915_WRITE_TAIL(ring, value);
465 }
466
intel_ring_get_active_head(struct intel_engine_cs * ring)467 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
468 {
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u64 acthd;
471
472 if (INTEL_INFO(ring->dev)->gen >= 8)
473 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
474 RING_ACTHD_UDW(ring->mmio_base));
475 else if (INTEL_INFO(ring->dev)->gen >= 4)
476 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
477 else
478 acthd = I915_READ(ACTHD);
479
480 return acthd;
481 }
482
ring_setup_phys_status_page(struct intel_engine_cs * ring)483 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
484 {
485 struct drm_i915_private *dev_priv = ring->dev->dev_private;
486 u32 addr;
487
488 addr = dev_priv->status_page_dmah->busaddr;
489 if (INTEL_INFO(ring->dev)->gen >= 4)
490 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
491 I915_WRITE(HWS_PGA, addr);
492 }
493
stop_ring(struct intel_engine_cs * ring)494 static bool stop_ring(struct intel_engine_cs *ring)
495 {
496 struct drm_i915_private *dev_priv = to_i915(ring->dev);
497
498 if (!IS_GEN2(ring->dev)) {
499 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
500 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
501 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
502 /* Sometimes we observe that the idle flag is not
503 * set even though the ring is empty. So double
504 * check before giving up.
505 */
506 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
507 return false;
508 }
509 }
510
511 I915_WRITE_CTL(ring, 0);
512 I915_WRITE_HEAD(ring, 0);
513 ring->write_tail(ring, 0);
514
515 if (!IS_GEN2(ring->dev)) {
516 (void)I915_READ_CTL(ring);
517 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
518 }
519
520 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
521 }
522
init_ring_common(struct intel_engine_cs * ring)523 static int init_ring_common(struct intel_engine_cs *ring)
524 {
525 struct drm_device *dev = ring->dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 struct intel_ringbuffer *ringbuf = ring->buffer;
528 struct drm_i915_gem_object *obj = ringbuf->obj;
529 int ret = 0;
530
531 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
532
533 if (!stop_ring(ring)) {
534 /* G45 ring initialization often fails to reset head to zero */
535 DRM_DEBUG_KMS("%s head not reset to zero "
536 "ctl %08x head %08x tail %08x start %08x\n",
537 ring->name,
538 I915_READ_CTL(ring),
539 I915_READ_HEAD(ring),
540 I915_READ_TAIL(ring),
541 I915_READ_START(ring));
542
543 if (!stop_ring(ring)) {
544 DRM_ERROR("failed to set %s head to zero "
545 "ctl %08x head %08x tail %08x start %08x\n",
546 ring->name,
547 I915_READ_CTL(ring),
548 I915_READ_HEAD(ring),
549 I915_READ_TAIL(ring),
550 I915_READ_START(ring));
551 ret = -EIO;
552 goto out;
553 }
554 }
555
556 if (I915_NEED_GFX_HWS(dev))
557 intel_ring_setup_status_page(ring);
558 else
559 ring_setup_phys_status_page(ring);
560
561 /* Enforce ordering by reading HEAD register back */
562 I915_READ_HEAD(ring);
563
564 /* Initialize the ring. This must happen _after_ we've cleared the ring
565 * registers with the above sequence (the readback of the HEAD registers
566 * also enforces ordering), otherwise the hw might lose the new ring
567 * register values. */
568 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
569
570 /* WaClearRingBufHeadRegAtInit:ctg,elk */
571 if (I915_READ_HEAD(ring))
572 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
573 ring->name, I915_READ_HEAD(ring));
574 I915_WRITE_HEAD(ring, 0);
575 (void)I915_READ_HEAD(ring);
576
577 I915_WRITE_CTL(ring,
578 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
579 | RING_VALID);
580
581 /* If the head is still not zero, the ring is dead */
582 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
583 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
584 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
585 DRM_ERROR("%s initialization failed "
586 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
587 ring->name,
588 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
589 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
590 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
591 ret = -EIO;
592 goto out;
593 }
594
595 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
596 i915_kernel_lost_context(ring->dev);
597 else {
598 ringbuf->head = I915_READ_HEAD(ring);
599 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
600 ringbuf->space = intel_ring_space(ringbuf);
601 ringbuf->last_retired_head = -1;
602 }
603
604 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
605
606 out:
607 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
608
609 return ret;
610 }
611
612 void
intel_fini_pipe_control(struct intel_engine_cs * ring)613 intel_fini_pipe_control(struct intel_engine_cs *ring)
614 {
615 struct drm_device *dev = ring->dev;
616
617 if (ring->scratch.obj == NULL)
618 return;
619
620 if (INTEL_INFO(dev)->gen >= 5) {
621 kunmap(sg_page(ring->scratch.obj->pages->sgl));
622 i915_gem_object_ggtt_unpin(ring->scratch.obj);
623 }
624
625 drm_gem_object_unreference(&ring->scratch.obj->base);
626 ring->scratch.obj = NULL;
627 }
628
629 int
intel_init_pipe_control(struct intel_engine_cs * ring)630 intel_init_pipe_control(struct intel_engine_cs *ring)
631 {
632 int ret;
633
634 if (ring->scratch.obj)
635 return 0;
636
637 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
638 if (ring->scratch.obj == NULL) {
639 DRM_ERROR("Failed to allocate seqno page\n");
640 ret = -ENOMEM;
641 goto err;
642 }
643
644 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
645 if (ret)
646 goto err_unref;
647
648 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
649 if (ret)
650 goto err_unref;
651
652 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
653 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
654 if (ring->scratch.cpu_page == NULL) {
655 ret = -ENOMEM;
656 goto err_unpin;
657 }
658
659 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
660 ring->name, ring->scratch.gtt_offset);
661 return 0;
662
663 err_unpin:
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 err_unref:
666 drm_gem_object_unreference(&ring->scratch.obj->base);
667 err:
668 return ret;
669 }
670
intel_ring_emit_wa(struct intel_engine_cs * ring,u32 addr,u32 value)671 static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
672 u32 addr, u32 value)
673 {
674 struct drm_device *dev = ring->dev;
675 struct drm_i915_private *dev_priv = dev->dev_private;
676
677 if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
678 return;
679
680 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
681 intel_ring_emit(ring, addr);
682 intel_ring_emit(ring, value);
683
684 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
685 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
686 /* value is updated with the status of remaining bits of this
687 * register when it is read from debugfs file
688 */
689 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
690 dev_priv->num_wa_regs++;
691
692 return;
693 }
694
bdw_init_workarounds(struct intel_engine_cs * ring)695 static int bdw_init_workarounds(struct intel_engine_cs *ring)
696 {
697 int ret;
698 struct drm_device *dev = ring->dev;
699 struct drm_i915_private *dev_priv = dev->dev_private;
700
701 /*
702 * workarounds applied in this fn are part of register state context,
703 * they need to be re-initialized followed by gpu reset, suspend/resume,
704 * module reload.
705 */
706 dev_priv->num_wa_regs = 0;
707 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
708
709 /*
710 * update the number of dwords required based on the
711 * actual number of workarounds applied
712 */
713 ret = intel_ring_begin(ring, 18);
714 if (ret)
715 return ret;
716
717 /* WaDisablePartialInstShootdown:bdw */
718 /* WaDisableThreadStallDopClockGating:bdw */
719 /* FIXME: Unclear whether we really need this on production bdw. */
720 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
721 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
722 | STALL_DOP_GATING_DISABLE));
723
724 /* WaDisableDopClockGating:bdw May not be needed for production */
725 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
726 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
727
728 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
729 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
730
731 /* Use Force Non-Coherent whenever executing a 3D context. This is a
732 * workaround for for a possible hang in the unlikely event a TLB
733 * invalidation occurs during a PSD flush.
734 */
735 intel_ring_emit_wa(ring, HDC_CHICKEN0,
736 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
737
738 /* Wa4x4STCOptimizationDisable:bdw */
739 intel_ring_emit_wa(ring, CACHE_MODE_1,
740 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
741
742 /*
743 * BSpec recommends 8x4 when MSAA is used,
744 * however in practice 16x4 seems fastest.
745 *
746 * Note that PS/WM thread counts depend on the WIZ hashing
747 * disable bit, which we don't touch here, but it's good
748 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
749 */
750 intel_ring_emit_wa(ring, GEN7_GT_MODE,
751 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
752
753 intel_ring_advance(ring);
754
755 DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
756 dev_priv->num_wa_regs);
757
758 return 0;
759 }
760
chv_init_workarounds(struct intel_engine_cs * ring)761 static int chv_init_workarounds(struct intel_engine_cs *ring)
762 {
763 int ret;
764 struct drm_device *dev = ring->dev;
765 struct drm_i915_private *dev_priv = dev->dev_private;
766
767 /*
768 * workarounds applied in this fn are part of register state context,
769 * they need to be re-initialized followed by gpu reset, suspend/resume,
770 * module reload.
771 */
772 dev_priv->num_wa_regs = 0;
773 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
774
775 ret = intel_ring_begin(ring, 12);
776 if (ret)
777 return ret;
778
779 /* WaDisablePartialInstShootdown:chv */
780 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
781 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
782
783 /* WaDisableThreadStallDopClockGating:chv */
784 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
785 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
786
787 /* WaDisableDopClockGating:chv (pre-production hw) */
788 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
789 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
790
791 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
792 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
793 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
794
795 intel_ring_advance(ring);
796
797 return 0;
798 }
799
init_render_ring(struct intel_engine_cs * ring)800 static int init_render_ring(struct intel_engine_cs *ring)
801 {
802 struct drm_device *dev = ring->dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 int ret = init_ring_common(ring);
805 if (ret)
806 return ret;
807
808 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
809 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
810 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
811
812 /* We need to disable the AsyncFlip performance optimisations in order
813 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
814 * programmed to '1' on all products.
815 *
816 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
817 */
818 if (INTEL_INFO(dev)->gen >= 6)
819 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
820
821 /* Required for the hardware to program scanline values for waiting */
822 /* WaEnableFlushTlbInvalidationMode:snb */
823 if (INTEL_INFO(dev)->gen == 6)
824 I915_WRITE(GFX_MODE,
825 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
826
827 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
828 if (IS_GEN7(dev))
829 I915_WRITE(GFX_MODE_GEN7,
830 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
831 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
832
833 if (INTEL_INFO(dev)->gen >= 5) {
834 ret = intel_init_pipe_control(ring);
835 if (ret)
836 return ret;
837 }
838
839 if (IS_GEN6(dev)) {
840 /* From the Sandybridge PRM, volume 1 part 3, page 24:
841 * "If this bit is set, STCunit will have LRA as replacement
842 * policy. [...] This bit must be reset. LRA replacement
843 * policy is not supported."
844 */
845 I915_WRITE(CACHE_MODE_0,
846 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
847 }
848
849 if (INTEL_INFO(dev)->gen >= 6)
850 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
851
852 if (HAS_L3_DPF(dev))
853 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
854
855 return ret;
856 }
857
render_ring_cleanup(struct intel_engine_cs * ring)858 static void render_ring_cleanup(struct intel_engine_cs *ring)
859 {
860 struct drm_device *dev = ring->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862
863 if (dev_priv->semaphore_obj) {
864 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
865 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
866 dev_priv->semaphore_obj = NULL;
867 }
868
869 intel_fini_pipe_control(ring);
870 }
871
gen8_rcs_signal(struct intel_engine_cs * signaller,unsigned int num_dwords)872 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
873 unsigned int num_dwords)
874 {
875 #define MBOX_UPDATE_DWORDS 8
876 struct drm_device *dev = signaller->dev;
877 struct drm_i915_private *dev_priv = dev->dev_private;
878 struct intel_engine_cs *waiter;
879 int i, ret, num_rings;
880
881 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
882 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
883 #undef MBOX_UPDATE_DWORDS
884
885 ret = intel_ring_begin(signaller, num_dwords);
886 if (ret)
887 return ret;
888
889 for_each_ring(waiter, dev_priv, i) {
890 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
891 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
892 continue;
893
894 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
895 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
896 PIPE_CONTROL_QW_WRITE |
897 PIPE_CONTROL_FLUSH_ENABLE);
898 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
899 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
900 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
901 intel_ring_emit(signaller, 0);
902 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
903 MI_SEMAPHORE_TARGET(waiter->id));
904 intel_ring_emit(signaller, 0);
905 }
906
907 return 0;
908 }
909
gen8_xcs_signal(struct intel_engine_cs * signaller,unsigned int num_dwords)910 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
911 unsigned int num_dwords)
912 {
913 #define MBOX_UPDATE_DWORDS 6
914 struct drm_device *dev = signaller->dev;
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 struct intel_engine_cs *waiter;
917 int i, ret, num_rings;
918
919 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
920 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
921 #undef MBOX_UPDATE_DWORDS
922
923 ret = intel_ring_begin(signaller, num_dwords);
924 if (ret)
925 return ret;
926
927 for_each_ring(waiter, dev_priv, i) {
928 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
929 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
930 continue;
931
932 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
933 MI_FLUSH_DW_OP_STOREDW);
934 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
935 MI_FLUSH_DW_USE_GTT);
936 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
937 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
938 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
939 MI_SEMAPHORE_TARGET(waiter->id));
940 intel_ring_emit(signaller, 0);
941 }
942
943 return 0;
944 }
945
gen6_signal(struct intel_engine_cs * signaller,unsigned int num_dwords)946 static int gen6_signal(struct intel_engine_cs *signaller,
947 unsigned int num_dwords)
948 {
949 struct drm_device *dev = signaller->dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951 struct intel_engine_cs *useless;
952 int i, ret, num_rings;
953
954 #define MBOX_UPDATE_DWORDS 3
955 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
956 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
957 #undef MBOX_UPDATE_DWORDS
958
959 ret = intel_ring_begin(signaller, num_dwords);
960 if (ret)
961 return ret;
962
963 for_each_ring(useless, dev_priv, i) {
964 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
965 if (mbox_reg != GEN6_NOSYNC) {
966 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
967 intel_ring_emit(signaller, mbox_reg);
968 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
969 }
970 }
971
972 /* If num_dwords was rounded, make sure the tail pointer is correct */
973 if (num_rings % 2 == 0)
974 intel_ring_emit(signaller, MI_NOOP);
975
976 return 0;
977 }
978
979 /**
980 * gen6_add_request - Update the semaphore mailbox registers
981 *
982 * @ring - ring that is adding a request
983 * @seqno - return seqno stuck into the ring
984 *
985 * Update the mailbox registers in the *other* rings with the current seqno.
986 * This acts like a signal in the canonical semaphore.
987 */
988 static int
gen6_add_request(struct intel_engine_cs * ring)989 gen6_add_request(struct intel_engine_cs *ring)
990 {
991 int ret;
992
993 if (ring->semaphore.signal)
994 ret = ring->semaphore.signal(ring, 4);
995 else
996 ret = intel_ring_begin(ring, 4);
997
998 if (ret)
999 return ret;
1000
1001 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1002 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1003 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1004 intel_ring_emit(ring, MI_USER_INTERRUPT);
1005 __intel_ring_advance(ring);
1006
1007 return 0;
1008 }
1009
i915_gem_has_seqno_wrapped(struct drm_device * dev,u32 seqno)1010 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1011 u32 seqno)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 return dev_priv->last_seqno < seqno;
1015 }
1016
1017 /**
1018 * intel_ring_sync - sync the waiter to the signaller on seqno
1019 *
1020 * @waiter - ring that is waiting
1021 * @signaller - ring which has, or will signal
1022 * @seqno - seqno which the waiter will block on
1023 */
1024
1025 static int
gen8_ring_sync(struct intel_engine_cs * waiter,struct intel_engine_cs * signaller,u32 seqno)1026 gen8_ring_sync(struct intel_engine_cs *waiter,
1027 struct intel_engine_cs *signaller,
1028 u32 seqno)
1029 {
1030 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1031 int ret;
1032
1033 ret = intel_ring_begin(waiter, 4);
1034 if (ret)
1035 return ret;
1036
1037 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1038 MI_SEMAPHORE_GLOBAL_GTT |
1039 MI_SEMAPHORE_POLL |
1040 MI_SEMAPHORE_SAD_GTE_SDD);
1041 intel_ring_emit(waiter, seqno);
1042 intel_ring_emit(waiter,
1043 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1044 intel_ring_emit(waiter,
1045 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1046 intel_ring_advance(waiter);
1047 return 0;
1048 }
1049
1050 static int
gen6_ring_sync(struct intel_engine_cs * waiter,struct intel_engine_cs * signaller,u32 seqno)1051 gen6_ring_sync(struct intel_engine_cs *waiter,
1052 struct intel_engine_cs *signaller,
1053 u32 seqno)
1054 {
1055 u32 dw1 = MI_SEMAPHORE_MBOX |
1056 MI_SEMAPHORE_COMPARE |
1057 MI_SEMAPHORE_REGISTER;
1058 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1059 int ret;
1060
1061 /* Throughout all of the GEM code, seqno passed implies our current
1062 * seqno is >= the last seqno executed. However for hardware the
1063 * comparison is strictly greater than.
1064 */
1065 seqno -= 1;
1066
1067 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1068
1069 ret = intel_ring_begin(waiter, 4);
1070 if (ret)
1071 return ret;
1072
1073 /* If seqno wrap happened, omit the wait with no-ops */
1074 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1075 intel_ring_emit(waiter, dw1 | wait_mbox);
1076 intel_ring_emit(waiter, seqno);
1077 intel_ring_emit(waiter, 0);
1078 intel_ring_emit(waiter, MI_NOOP);
1079 } else {
1080 intel_ring_emit(waiter, MI_NOOP);
1081 intel_ring_emit(waiter, MI_NOOP);
1082 intel_ring_emit(waiter, MI_NOOP);
1083 intel_ring_emit(waiter, MI_NOOP);
1084 }
1085 intel_ring_advance(waiter);
1086
1087 return 0;
1088 }
1089
1090 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1091 do { \
1092 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1093 PIPE_CONTROL_DEPTH_STALL); \
1094 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1095 intel_ring_emit(ring__, 0); \
1096 intel_ring_emit(ring__, 0); \
1097 } while (0)
1098
1099 static int
pc_render_add_request(struct intel_engine_cs * ring)1100 pc_render_add_request(struct intel_engine_cs *ring)
1101 {
1102 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1103 int ret;
1104
1105 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1106 * incoherent with writes to memory, i.e. completely fubar,
1107 * so we need to use PIPE_NOTIFY instead.
1108 *
1109 * However, we also need to workaround the qword write
1110 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1111 * memory before requesting an interrupt.
1112 */
1113 ret = intel_ring_begin(ring, 32);
1114 if (ret)
1115 return ret;
1116
1117 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1118 PIPE_CONTROL_WRITE_FLUSH |
1119 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1120 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1121 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1122 intel_ring_emit(ring, 0);
1123 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1124 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1125 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1126 scratch_addr += 2 * CACHELINE_BYTES;
1127 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1128 scratch_addr += 2 * CACHELINE_BYTES;
1129 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1130 scratch_addr += 2 * CACHELINE_BYTES;
1131 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1132 scratch_addr += 2 * CACHELINE_BYTES;
1133 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1134
1135 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1136 PIPE_CONTROL_WRITE_FLUSH |
1137 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1138 PIPE_CONTROL_NOTIFY);
1139 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1140 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1141 intel_ring_emit(ring, 0);
1142 __intel_ring_advance(ring);
1143
1144 return 0;
1145 }
1146
1147 static u32
gen6_ring_get_seqno(struct intel_engine_cs * ring,bool lazy_coherency)1148 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1149 {
1150 /* Workaround to force correct ordering between irq and seqno writes on
1151 * ivb (and maybe also on snb) by reading from a CS register (like
1152 * ACTHD) before reading the status page. */
1153 if (!lazy_coherency) {
1154 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1155 POSTING_READ(RING_ACTHD(ring->mmio_base));
1156 }
1157
1158 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1159 }
1160
1161 static u32
ring_get_seqno(struct intel_engine_cs * ring,bool lazy_coherency)1162 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1163 {
1164 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1165 }
1166
1167 static void
ring_set_seqno(struct intel_engine_cs * ring,u32 seqno)1168 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1169 {
1170 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1171 }
1172
1173 static u32
pc_render_get_seqno(struct intel_engine_cs * ring,bool lazy_coherency)1174 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1175 {
1176 return ring->scratch.cpu_page[0];
1177 }
1178
1179 static void
pc_render_set_seqno(struct intel_engine_cs * ring,u32 seqno)1180 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1181 {
1182 ring->scratch.cpu_page[0] = seqno;
1183 }
1184
1185 static bool
gen5_ring_get_irq(struct intel_engine_cs * ring)1186 gen5_ring_get_irq(struct intel_engine_cs *ring)
1187 {
1188 struct drm_device *dev = ring->dev;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 unsigned long flags;
1191
1192 if (!dev->irq_enabled)
1193 return false;
1194
1195 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1196 if (ring->irq_refcount++ == 0)
1197 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1198 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1199
1200 return true;
1201 }
1202
1203 static void
gen5_ring_put_irq(struct intel_engine_cs * ring)1204 gen5_ring_put_irq(struct intel_engine_cs *ring)
1205 {
1206 struct drm_device *dev = ring->dev;
1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 unsigned long flags;
1209
1210 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1211 if (--ring->irq_refcount == 0)
1212 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1213 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1214 }
1215
1216 static bool
i9xx_ring_get_irq(struct intel_engine_cs * ring)1217 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1218 {
1219 struct drm_device *dev = ring->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 unsigned long flags;
1222
1223 if (!dev->irq_enabled)
1224 return false;
1225
1226 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1227 if (ring->irq_refcount++ == 0) {
1228 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1229 I915_WRITE(IMR, dev_priv->irq_mask);
1230 POSTING_READ(IMR);
1231 }
1232 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1233
1234 return true;
1235 }
1236
1237 static void
i9xx_ring_put_irq(struct intel_engine_cs * ring)1238 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1239 {
1240 struct drm_device *dev = ring->dev;
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1245 if (--ring->irq_refcount == 0) {
1246 dev_priv->irq_mask |= ring->irq_enable_mask;
1247 I915_WRITE(IMR, dev_priv->irq_mask);
1248 POSTING_READ(IMR);
1249 }
1250 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1251 }
1252
1253 static bool
i8xx_ring_get_irq(struct intel_engine_cs * ring)1254 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1255 {
1256 struct drm_device *dev = ring->dev;
1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 unsigned long flags;
1259
1260 if (!dev->irq_enabled)
1261 return false;
1262
1263 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1264 if (ring->irq_refcount++ == 0) {
1265 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1266 I915_WRITE16(IMR, dev_priv->irq_mask);
1267 POSTING_READ16(IMR);
1268 }
1269 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1270
1271 return true;
1272 }
1273
1274 static void
i8xx_ring_put_irq(struct intel_engine_cs * ring)1275 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1276 {
1277 struct drm_device *dev = ring->dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 unsigned long flags;
1280
1281 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1282 if (--ring->irq_refcount == 0) {
1283 dev_priv->irq_mask |= ring->irq_enable_mask;
1284 I915_WRITE16(IMR, dev_priv->irq_mask);
1285 POSTING_READ16(IMR);
1286 }
1287 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1288 }
1289
intel_ring_setup_status_page(struct intel_engine_cs * ring)1290 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1291 {
1292 struct drm_device *dev = ring->dev;
1293 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1294 u32 mmio = 0;
1295
1296 /* The ring status page addresses are no longer next to the rest of
1297 * the ring registers as of gen7.
1298 */
1299 if (IS_GEN7(dev)) {
1300 switch (ring->id) {
1301 case RCS:
1302 mmio = RENDER_HWS_PGA_GEN7;
1303 break;
1304 case BCS:
1305 mmio = BLT_HWS_PGA_GEN7;
1306 break;
1307 /*
1308 * VCS2 actually doesn't exist on Gen7. Only shut up
1309 * gcc switch check warning
1310 */
1311 case VCS2:
1312 case VCS:
1313 mmio = BSD_HWS_PGA_GEN7;
1314 break;
1315 case VECS:
1316 mmio = VEBOX_HWS_PGA_GEN7;
1317 break;
1318 }
1319 } else if (IS_GEN6(ring->dev)) {
1320 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1321 } else {
1322 /* XXX: gen8 returns to sanity */
1323 mmio = RING_HWS_PGA(ring->mmio_base);
1324 }
1325
1326 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1327 POSTING_READ(mmio);
1328
1329 /*
1330 * Flush the TLB for this page
1331 *
1332 * FIXME: These two bits have disappeared on gen8, so a question
1333 * arises: do we still need this and if so how should we go about
1334 * invalidating the TLB?
1335 */
1336 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1337 u32 reg = RING_INSTPM(ring->mmio_base);
1338
1339 /* ring should be idle before issuing a sync flush*/
1340 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1341
1342 I915_WRITE(reg,
1343 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1344 INSTPM_SYNC_FLUSH));
1345 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1346 1000))
1347 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1348 ring->name);
1349 }
1350 }
1351
1352 static int
bsd_ring_flush(struct intel_engine_cs * ring,u32 invalidate_domains,u32 flush_domains)1353 bsd_ring_flush(struct intel_engine_cs *ring,
1354 u32 invalidate_domains,
1355 u32 flush_domains)
1356 {
1357 int ret;
1358
1359 ret = intel_ring_begin(ring, 2);
1360 if (ret)
1361 return ret;
1362
1363 intel_ring_emit(ring, MI_FLUSH);
1364 intel_ring_emit(ring, MI_NOOP);
1365 intel_ring_advance(ring);
1366 return 0;
1367 }
1368
1369 static int
i9xx_add_request(struct intel_engine_cs * ring)1370 i9xx_add_request(struct intel_engine_cs *ring)
1371 {
1372 int ret;
1373
1374 ret = intel_ring_begin(ring, 4);
1375 if (ret)
1376 return ret;
1377
1378 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1379 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1380 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1381 intel_ring_emit(ring, MI_USER_INTERRUPT);
1382 __intel_ring_advance(ring);
1383
1384 return 0;
1385 }
1386
1387 static bool
gen6_ring_get_irq(struct intel_engine_cs * ring)1388 gen6_ring_get_irq(struct intel_engine_cs *ring)
1389 {
1390 struct drm_device *dev = ring->dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 unsigned long flags;
1393
1394 if (!dev->irq_enabled)
1395 return false;
1396
1397 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1398 if (ring->irq_refcount++ == 0) {
1399 if (HAS_L3_DPF(dev) && ring->id == RCS)
1400 I915_WRITE_IMR(ring,
1401 ~(ring->irq_enable_mask |
1402 GT_PARITY_ERROR(dev)));
1403 else
1404 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1405 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1406 }
1407 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1408
1409 return true;
1410 }
1411
1412 static void
gen6_ring_put_irq(struct intel_engine_cs * ring)1413 gen6_ring_put_irq(struct intel_engine_cs *ring)
1414 {
1415 struct drm_device *dev = ring->dev;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 unsigned long flags;
1418
1419 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1420 if (--ring->irq_refcount == 0) {
1421 if (HAS_L3_DPF(dev) && ring->id == RCS)
1422 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1423 else
1424 I915_WRITE_IMR(ring, ~0);
1425 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1426 }
1427 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1428 }
1429
1430 static bool
hsw_vebox_get_irq(struct intel_engine_cs * ring)1431 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1432 {
1433 struct drm_device *dev = ring->dev;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 unsigned long flags;
1436
1437 if (!dev->irq_enabled)
1438 return false;
1439
1440 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1441 if (ring->irq_refcount++ == 0) {
1442 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1443 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1444 }
1445 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1446
1447 return true;
1448 }
1449
1450 static void
hsw_vebox_put_irq(struct intel_engine_cs * ring)1451 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1452 {
1453 struct drm_device *dev = ring->dev;
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 unsigned long flags;
1456
1457 if (!dev->irq_enabled)
1458 return;
1459
1460 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1461 if (--ring->irq_refcount == 0) {
1462 I915_WRITE_IMR(ring, ~0);
1463 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1464 }
1465 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1466 }
1467
1468 static bool
gen8_ring_get_irq(struct intel_engine_cs * ring)1469 gen8_ring_get_irq(struct intel_engine_cs *ring)
1470 {
1471 struct drm_device *dev = ring->dev;
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 unsigned long flags;
1474
1475 if (!dev->irq_enabled)
1476 return false;
1477
1478 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1479 if (ring->irq_refcount++ == 0) {
1480 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1481 I915_WRITE_IMR(ring,
1482 ~(ring->irq_enable_mask |
1483 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1484 } else {
1485 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1486 }
1487 POSTING_READ(RING_IMR(ring->mmio_base));
1488 }
1489 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1490
1491 return true;
1492 }
1493
1494 static void
gen8_ring_put_irq(struct intel_engine_cs * ring)1495 gen8_ring_put_irq(struct intel_engine_cs *ring)
1496 {
1497 struct drm_device *dev = ring->dev;
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 unsigned long flags;
1500
1501 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1502 if (--ring->irq_refcount == 0) {
1503 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1504 I915_WRITE_IMR(ring,
1505 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1506 } else {
1507 I915_WRITE_IMR(ring, ~0);
1508 }
1509 POSTING_READ(RING_IMR(ring->mmio_base));
1510 }
1511 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1512 }
1513
1514 static int
i965_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 length,unsigned flags)1515 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1516 u64 offset, u32 length,
1517 unsigned flags)
1518 {
1519 int ret;
1520
1521 ret = intel_ring_begin(ring, 2);
1522 if (ret)
1523 return ret;
1524
1525 intel_ring_emit(ring,
1526 MI_BATCH_BUFFER_START |
1527 MI_BATCH_GTT |
1528 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1529 intel_ring_emit(ring, offset);
1530 intel_ring_advance(ring);
1531
1532 return 0;
1533 }
1534
1535 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1536 #define I830_BATCH_LIMIT (256*1024)
1537 #define I830_TLB_ENTRIES (2)
1538 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1539 static int
i830_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 len,unsigned flags)1540 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1541 u64 offset, u32 len,
1542 unsigned flags)
1543 {
1544 u32 cs_offset = ring->scratch.gtt_offset;
1545 int ret;
1546
1547 ret = intel_ring_begin(ring, 6);
1548 if (ret)
1549 return ret;
1550
1551 /* Evict the invalid PTE TLBs */
1552 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1553 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1554 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1555 intel_ring_emit(ring, cs_offset);
1556 intel_ring_emit(ring, 0xdeadbeef);
1557 intel_ring_emit(ring, MI_NOOP);
1558 intel_ring_advance(ring);
1559
1560 if ((flags & I915_DISPATCH_PINNED) == 0) {
1561 if (len > I830_BATCH_LIMIT)
1562 return -ENOSPC;
1563
1564 ret = intel_ring_begin(ring, 6 + 2);
1565 if (ret)
1566 return ret;
1567
1568 /* Blit the batch (which has now all relocs applied) to the
1569 * stable batch scratch bo area (so that the CS never
1570 * stumbles over its tlb invalidation bug) ...
1571 */
1572 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1573 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1574 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1575 intel_ring_emit(ring, cs_offset);
1576 intel_ring_emit(ring, 4096);
1577 intel_ring_emit(ring, offset);
1578
1579 intel_ring_emit(ring, MI_FLUSH);
1580 intel_ring_emit(ring, MI_NOOP);
1581 intel_ring_advance(ring);
1582
1583 /* ... and execute it. */
1584 offset = cs_offset;
1585 }
1586
1587 ret = intel_ring_begin(ring, 4);
1588 if (ret)
1589 return ret;
1590
1591 intel_ring_emit(ring, MI_BATCH_BUFFER);
1592 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1593 intel_ring_emit(ring, offset + len - 8);
1594 intel_ring_emit(ring, MI_NOOP);
1595 intel_ring_advance(ring);
1596
1597 return 0;
1598 }
1599
1600 static int
i915_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 len,unsigned flags)1601 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1602 u64 offset, u32 len,
1603 unsigned flags)
1604 {
1605 int ret;
1606
1607 ret = intel_ring_begin(ring, 2);
1608 if (ret)
1609 return ret;
1610
1611 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1612 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1613 intel_ring_advance(ring);
1614
1615 return 0;
1616 }
1617
cleanup_status_page(struct intel_engine_cs * ring)1618 static void cleanup_status_page(struct intel_engine_cs *ring)
1619 {
1620 struct drm_i915_gem_object *obj;
1621
1622 obj = ring->status_page.obj;
1623 if (obj == NULL)
1624 return;
1625
1626 kunmap(sg_page(obj->pages->sgl));
1627 i915_gem_object_ggtt_unpin(obj);
1628 drm_gem_object_unreference(&obj->base);
1629 ring->status_page.obj = NULL;
1630 }
1631
init_status_page(struct intel_engine_cs * ring)1632 static int init_status_page(struct intel_engine_cs *ring)
1633 {
1634 struct drm_i915_gem_object *obj;
1635
1636 if ((obj = ring->status_page.obj) == NULL) {
1637 unsigned flags;
1638 int ret;
1639
1640 obj = i915_gem_alloc_object(ring->dev, 4096);
1641 if (obj == NULL) {
1642 DRM_ERROR("Failed to allocate status page\n");
1643 return -ENOMEM;
1644 }
1645
1646 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1647 if (ret)
1648 goto err_unref;
1649
1650 flags = 0;
1651 if (!HAS_LLC(ring->dev))
1652 /* On g33, we cannot place HWS above 256MiB, so
1653 * restrict its pinning to the low mappable arena.
1654 * Though this restriction is not documented for
1655 * gen4, gen5, or byt, they also behave similarly
1656 * and hang if the HWS is placed at the top of the
1657 * GTT. To generalise, it appears that all !llc
1658 * platforms have issues with us placing the HWS
1659 * above the mappable region (even though we never
1660 * actualy map it).
1661 */
1662 flags |= PIN_MAPPABLE;
1663 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1664 if (ret) {
1665 err_unref:
1666 drm_gem_object_unreference(&obj->base);
1667 return ret;
1668 }
1669
1670 ring->status_page.obj = obj;
1671 }
1672
1673 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1674 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1675 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1676
1677 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1678 ring->name, ring->status_page.gfx_addr);
1679
1680 return 0;
1681 }
1682
init_phys_status_page(struct intel_engine_cs * ring)1683 static int init_phys_status_page(struct intel_engine_cs *ring)
1684 {
1685 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1686
1687 if (!dev_priv->status_page_dmah) {
1688 dev_priv->status_page_dmah =
1689 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1690 if (!dev_priv->status_page_dmah)
1691 return -ENOMEM;
1692 }
1693
1694 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1695 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1696
1697 return 0;
1698 }
1699
intel_destroy_ringbuffer_obj(struct intel_ringbuffer * ringbuf)1700 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1701 {
1702 if (!ringbuf->obj)
1703 return;
1704
1705 iounmap(ringbuf->virtual_start);
1706 i915_gem_object_ggtt_unpin(ringbuf->obj);
1707 drm_gem_object_unreference(&ringbuf->obj->base);
1708 ringbuf->obj = NULL;
1709 }
1710
intel_alloc_ringbuffer_obj(struct drm_device * dev,struct intel_ringbuffer * ringbuf)1711 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1712 struct intel_ringbuffer *ringbuf)
1713 {
1714 struct drm_i915_private *dev_priv = to_i915(dev);
1715 struct drm_i915_gem_object *obj;
1716 int ret;
1717
1718 if (ringbuf->obj)
1719 return 0;
1720
1721 obj = NULL;
1722 if (!HAS_LLC(dev))
1723 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1724 if (obj == NULL)
1725 obj = i915_gem_alloc_object(dev, ringbuf->size);
1726 if (obj == NULL)
1727 return -ENOMEM;
1728
1729 /* mark ring buffers as read-only from GPU side by default */
1730 obj->gt_ro = 1;
1731
1732 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1733 if (ret)
1734 goto err_unref;
1735
1736 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1737 if (ret)
1738 goto err_unpin;
1739
1740 ringbuf->virtual_start =
1741 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1742 ringbuf->size);
1743 if (ringbuf->virtual_start == NULL) {
1744 ret = -EINVAL;
1745 goto err_unpin;
1746 }
1747
1748 ringbuf->obj = obj;
1749 return 0;
1750
1751 err_unpin:
1752 i915_gem_object_ggtt_unpin(obj);
1753 err_unref:
1754 drm_gem_object_unreference(&obj->base);
1755 return ret;
1756 }
1757
intel_init_ring_buffer(struct drm_device * dev,struct intel_engine_cs * ring)1758 static int intel_init_ring_buffer(struct drm_device *dev,
1759 struct intel_engine_cs *ring)
1760 {
1761 struct intel_ringbuffer *ringbuf = ring->buffer;
1762 int ret;
1763
1764 if (ringbuf == NULL) {
1765 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1766 if (!ringbuf)
1767 return -ENOMEM;
1768 ring->buffer = ringbuf;
1769 }
1770
1771 ring->dev = dev;
1772 INIT_LIST_HEAD(&ring->active_list);
1773 INIT_LIST_HEAD(&ring->request_list);
1774 INIT_LIST_HEAD(&ring->execlist_queue);
1775 ringbuf->size = 32 * PAGE_SIZE;
1776 ringbuf->ring = ring;
1777 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1778
1779 init_waitqueue_head(&ring->irq_queue);
1780
1781 if (I915_NEED_GFX_HWS(dev)) {
1782 ret = init_status_page(ring);
1783 if (ret)
1784 goto error;
1785 } else {
1786 BUG_ON(ring->id != RCS);
1787 ret = init_phys_status_page(ring);
1788 if (ret)
1789 goto error;
1790 }
1791
1792 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1793 if (ret) {
1794 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1795 goto error;
1796 }
1797
1798 /* Workaround an erratum on the i830 which causes a hang if
1799 * the TAIL pointer points to within the last 2 cachelines
1800 * of the buffer.
1801 */
1802 ringbuf->effective_size = ringbuf->size;
1803 if (IS_I830(dev) || IS_845G(dev))
1804 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1805
1806 ret = i915_cmd_parser_init_ring(ring);
1807 if (ret)
1808 goto error;
1809
1810 ret = ring->init(ring);
1811 if (ret)
1812 goto error;
1813
1814 return 0;
1815
1816 error:
1817 kfree(ringbuf);
1818 ring->buffer = NULL;
1819 return ret;
1820 }
1821
intel_cleanup_ring_buffer(struct intel_engine_cs * ring)1822 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1823 {
1824 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1825 struct intel_ringbuffer *ringbuf = ring->buffer;
1826
1827 if (!intel_ring_initialized(ring))
1828 return;
1829
1830 intel_stop_ring_buffer(ring);
1831 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1832
1833 intel_destroy_ringbuffer_obj(ringbuf);
1834 ring->preallocated_lazy_request = NULL;
1835 ring->outstanding_lazy_seqno = 0;
1836
1837 if (ring->cleanup)
1838 ring->cleanup(ring);
1839
1840 cleanup_status_page(ring);
1841
1842 i915_cmd_parser_fini_ring(ring);
1843
1844 kfree(ringbuf);
1845 ring->buffer = NULL;
1846 }
1847
intel_ring_wait_request(struct intel_engine_cs * ring,int n)1848 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1849 {
1850 struct intel_ringbuffer *ringbuf = ring->buffer;
1851 struct drm_i915_gem_request *request;
1852 u32 seqno = 0;
1853 int ret;
1854
1855 if (ringbuf->last_retired_head != -1) {
1856 ringbuf->head = ringbuf->last_retired_head;
1857 ringbuf->last_retired_head = -1;
1858
1859 ringbuf->space = intel_ring_space(ringbuf);
1860 if (ringbuf->space >= n)
1861 return 0;
1862 }
1863
1864 list_for_each_entry(request, &ring->request_list, list) {
1865 if (__intel_ring_space(request->tail, ringbuf->tail,
1866 ringbuf->size) >= n) {
1867 seqno = request->seqno;
1868 break;
1869 }
1870 }
1871
1872 if (seqno == 0)
1873 return -ENOSPC;
1874
1875 ret = i915_wait_seqno(ring, seqno);
1876 if (ret)
1877 return ret;
1878
1879 i915_gem_retire_requests_ring(ring);
1880 ringbuf->head = ringbuf->last_retired_head;
1881 ringbuf->last_retired_head = -1;
1882
1883 ringbuf->space = intel_ring_space(ringbuf);
1884 return 0;
1885 }
1886
ring_wait_for_space(struct intel_engine_cs * ring,int n)1887 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1888 {
1889 struct drm_device *dev = ring->dev;
1890 struct drm_i915_private *dev_priv = dev->dev_private;
1891 struct intel_ringbuffer *ringbuf = ring->buffer;
1892 unsigned long end;
1893 int ret;
1894
1895 ret = intel_ring_wait_request(ring, n);
1896 if (ret != -ENOSPC)
1897 return ret;
1898
1899 /* force the tail write in case we have been skipping them */
1900 __intel_ring_advance(ring);
1901
1902 /* With GEM the hangcheck timer should kick us out of the loop,
1903 * leaving it early runs the risk of corrupting GEM state (due
1904 * to running on almost untested codepaths). But on resume
1905 * timers don't work yet, so prevent a complete hang in that
1906 * case by choosing an insanely large timeout. */
1907 end = jiffies + 60 * HZ;
1908
1909 trace_i915_ring_wait_begin(ring);
1910 do {
1911 ringbuf->head = I915_READ_HEAD(ring);
1912 ringbuf->space = intel_ring_space(ringbuf);
1913 if (ringbuf->space >= n) {
1914 ret = 0;
1915 break;
1916 }
1917
1918 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1919 dev->primary->master) {
1920 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1921 if (master_priv->sarea_priv)
1922 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1923 }
1924
1925 msleep(1);
1926
1927 if (dev_priv->mm.interruptible && signal_pending(current)) {
1928 ret = -ERESTARTSYS;
1929 break;
1930 }
1931
1932 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1933 dev_priv->mm.interruptible);
1934 if (ret)
1935 break;
1936
1937 if (time_after(jiffies, end)) {
1938 ret = -EBUSY;
1939 break;
1940 }
1941 } while (1);
1942 trace_i915_ring_wait_end(ring);
1943 return ret;
1944 }
1945
intel_wrap_ring_buffer(struct intel_engine_cs * ring)1946 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1947 {
1948 uint32_t __iomem *virt;
1949 struct intel_ringbuffer *ringbuf = ring->buffer;
1950 int rem = ringbuf->size - ringbuf->tail;
1951
1952 if (ringbuf->space < rem) {
1953 int ret = ring_wait_for_space(ring, rem);
1954 if (ret)
1955 return ret;
1956 }
1957
1958 virt = ringbuf->virtual_start + ringbuf->tail;
1959 rem /= 4;
1960 while (rem--)
1961 iowrite32(MI_NOOP, virt++);
1962
1963 ringbuf->tail = 0;
1964 ringbuf->space = intel_ring_space(ringbuf);
1965
1966 return 0;
1967 }
1968
intel_ring_idle(struct intel_engine_cs * ring)1969 int intel_ring_idle(struct intel_engine_cs *ring)
1970 {
1971 u32 seqno;
1972 int ret;
1973
1974 /* We need to add any requests required to flush the objects and ring */
1975 if (ring->outstanding_lazy_seqno) {
1976 ret = i915_add_request(ring, NULL);
1977 if (ret)
1978 return ret;
1979 }
1980
1981 /* Wait upon the last request to be completed */
1982 if (list_empty(&ring->request_list))
1983 return 0;
1984
1985 seqno = list_entry(ring->request_list.prev,
1986 struct drm_i915_gem_request,
1987 list)->seqno;
1988
1989 return i915_wait_seqno(ring, seqno);
1990 }
1991
1992 static int
intel_ring_alloc_seqno(struct intel_engine_cs * ring)1993 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
1994 {
1995 if (ring->outstanding_lazy_seqno)
1996 return 0;
1997
1998 if (ring->preallocated_lazy_request == NULL) {
1999 struct drm_i915_gem_request *request;
2000
2001 request = kmalloc(sizeof(*request), GFP_KERNEL);
2002 if (request == NULL)
2003 return -ENOMEM;
2004
2005 ring->preallocated_lazy_request = request;
2006 }
2007
2008 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2009 }
2010
__intel_ring_prepare(struct intel_engine_cs * ring,int bytes)2011 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2012 int bytes)
2013 {
2014 struct intel_ringbuffer *ringbuf = ring->buffer;
2015 int ret;
2016
2017 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2018 ret = intel_wrap_ring_buffer(ring);
2019 if (unlikely(ret))
2020 return ret;
2021 }
2022
2023 if (unlikely(ringbuf->space < bytes)) {
2024 ret = ring_wait_for_space(ring, bytes);
2025 if (unlikely(ret))
2026 return ret;
2027 }
2028
2029 return 0;
2030 }
2031
intel_ring_begin(struct intel_engine_cs * ring,int num_dwords)2032 int intel_ring_begin(struct intel_engine_cs *ring,
2033 int num_dwords)
2034 {
2035 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2036 int ret;
2037
2038 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2039 dev_priv->mm.interruptible);
2040 if (ret)
2041 return ret;
2042
2043 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2044 if (ret)
2045 return ret;
2046
2047 /* Preallocate the olr before touching the ring */
2048 ret = intel_ring_alloc_seqno(ring);
2049 if (ret)
2050 return ret;
2051
2052 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2053 return 0;
2054 }
2055
2056 /* Align the ring tail to a cacheline boundary */
intel_ring_cacheline_align(struct intel_engine_cs * ring)2057 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2058 {
2059 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2060 int ret;
2061
2062 if (num_dwords == 0)
2063 return 0;
2064
2065 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2066 ret = intel_ring_begin(ring, num_dwords);
2067 if (ret)
2068 return ret;
2069
2070 while (num_dwords--)
2071 intel_ring_emit(ring, MI_NOOP);
2072
2073 intel_ring_advance(ring);
2074
2075 return 0;
2076 }
2077
intel_ring_init_seqno(struct intel_engine_cs * ring,u32 seqno)2078 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2079 {
2080 struct drm_device *dev = ring->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082
2083 BUG_ON(ring->outstanding_lazy_seqno);
2084
2085 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2086 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2087 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2088 if (HAS_VEBOX(dev))
2089 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2090 }
2091
2092 ring->set_seqno(ring, seqno);
2093 ring->hangcheck.seqno = seqno;
2094 }
2095
gen6_bsd_ring_write_tail(struct intel_engine_cs * ring,u32 value)2096 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2097 u32 value)
2098 {
2099 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2100
2101 /* Every tail move must follow the sequence below */
2102
2103 /* Disable notification that the ring is IDLE. The GT
2104 * will then assume that it is busy and bring it out of rc6.
2105 */
2106 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2107 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2108
2109 /* Clear the context id. Here be magic! */
2110 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2111
2112 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2113 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2114 GEN6_BSD_SLEEP_INDICATOR) == 0,
2115 50))
2116 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2117
2118 /* Now that the ring is fully powered up, update the tail */
2119 I915_WRITE_TAIL(ring, value);
2120 POSTING_READ(RING_TAIL(ring->mmio_base));
2121
2122 /* Let the ring send IDLE messages to the GT again,
2123 * and so let it sleep to conserve power when idle.
2124 */
2125 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2126 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2127 }
2128
gen6_bsd_ring_flush(struct intel_engine_cs * ring,u32 invalidate,u32 flush)2129 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2130 u32 invalidate, u32 flush)
2131 {
2132 uint32_t cmd;
2133 int ret;
2134
2135 ret = intel_ring_begin(ring, 4);
2136 if (ret)
2137 return ret;
2138
2139 cmd = MI_FLUSH_DW;
2140 if (INTEL_INFO(ring->dev)->gen >= 8)
2141 cmd += 1;
2142
2143 /* We always require a command barrier so that subsequent
2144 * commands, such as breadcrumb interrupts, are strictly ordered
2145 * wrt the contents of the write cache being flushed to memory
2146 * (and thus being coherent from the CPU).
2147 */
2148 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2149
2150 /*
2151 * Bspec vol 1c.5 - video engine command streamer:
2152 * "If ENABLED, all TLBs will be invalidated once the flush
2153 * operation is complete. This bit is only valid when the
2154 * Post-Sync Operation field is a value of 1h or 3h."
2155 */
2156 if (invalidate & I915_GEM_GPU_DOMAINS)
2157 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2158
2159 intel_ring_emit(ring, cmd);
2160 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2161 if (INTEL_INFO(ring->dev)->gen >= 8) {
2162 intel_ring_emit(ring, 0); /* upper addr */
2163 intel_ring_emit(ring, 0); /* value */
2164 } else {
2165 intel_ring_emit(ring, 0);
2166 intel_ring_emit(ring, MI_NOOP);
2167 }
2168 intel_ring_advance(ring);
2169 return 0;
2170 }
2171
2172 static int
gen8_ring_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 len,unsigned flags)2173 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2174 u64 offset, u32 len,
2175 unsigned flags)
2176 {
2177 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2178 int ret;
2179
2180 ret = intel_ring_begin(ring, 4);
2181 if (ret)
2182 return ret;
2183
2184 /* FIXME(BDW): Address space and security selectors. */
2185 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2186 intel_ring_emit(ring, lower_32_bits(offset));
2187 intel_ring_emit(ring, upper_32_bits(offset));
2188 intel_ring_emit(ring, MI_NOOP);
2189 intel_ring_advance(ring);
2190
2191 return 0;
2192 }
2193
2194 static int
hsw_ring_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 len,unsigned flags)2195 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2196 u64 offset, u32 len,
2197 unsigned flags)
2198 {
2199 int ret;
2200
2201 ret = intel_ring_begin(ring, 2);
2202 if (ret)
2203 return ret;
2204
2205 intel_ring_emit(ring,
2206 MI_BATCH_BUFFER_START |
2207 (flags & I915_DISPATCH_SECURE ?
2208 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2209 /* bit0-7 is the length on GEN6+ */
2210 intel_ring_emit(ring, offset);
2211 intel_ring_advance(ring);
2212
2213 return 0;
2214 }
2215
2216 static int
gen6_ring_dispatch_execbuffer(struct intel_engine_cs * ring,u64 offset,u32 len,unsigned flags)2217 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2218 u64 offset, u32 len,
2219 unsigned flags)
2220 {
2221 int ret;
2222
2223 ret = intel_ring_begin(ring, 2);
2224 if (ret)
2225 return ret;
2226
2227 intel_ring_emit(ring,
2228 MI_BATCH_BUFFER_START |
2229 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2230 /* bit0-7 is the length on GEN6+ */
2231 intel_ring_emit(ring, offset);
2232 intel_ring_advance(ring);
2233
2234 return 0;
2235 }
2236
2237 /* Blitter support (SandyBridge+) */
2238
gen6_ring_flush(struct intel_engine_cs * ring,u32 invalidate,u32 flush)2239 static int gen6_ring_flush(struct intel_engine_cs *ring,
2240 u32 invalidate, u32 flush)
2241 {
2242 struct drm_device *dev = ring->dev;
2243 uint32_t cmd;
2244 int ret;
2245
2246 ret = intel_ring_begin(ring, 4);
2247 if (ret)
2248 return ret;
2249
2250 cmd = MI_FLUSH_DW;
2251 if (INTEL_INFO(ring->dev)->gen >= 8)
2252 cmd += 1;
2253
2254 /* We always require a command barrier so that subsequent
2255 * commands, such as breadcrumb interrupts, are strictly ordered
2256 * wrt the contents of the write cache being flushed to memory
2257 * (and thus being coherent from the CPU).
2258 */
2259 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2260
2261 /*
2262 * Bspec vol 1c.3 - blitter engine command streamer:
2263 * "If ENABLED, all TLBs will be invalidated once the flush
2264 * operation is complete. This bit is only valid when the
2265 * Post-Sync Operation field is a value of 1h or 3h."
2266 */
2267 if (invalidate & I915_GEM_DOMAIN_RENDER)
2268 cmd |= MI_INVALIDATE_TLB;
2269 intel_ring_emit(ring, cmd);
2270 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2271 if (INTEL_INFO(ring->dev)->gen >= 8) {
2272 intel_ring_emit(ring, 0); /* upper addr */
2273 intel_ring_emit(ring, 0); /* value */
2274 } else {
2275 intel_ring_emit(ring, 0);
2276 intel_ring_emit(ring, MI_NOOP);
2277 }
2278 intel_ring_advance(ring);
2279
2280 if (IS_GEN7(dev) && !invalidate && flush)
2281 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2282
2283 return 0;
2284 }
2285
intel_init_render_ring_buffer(struct drm_device * dev)2286 int intel_init_render_ring_buffer(struct drm_device *dev)
2287 {
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2290 struct drm_i915_gem_object *obj;
2291 int ret;
2292
2293 ring->name = "render ring";
2294 ring->id = RCS;
2295 ring->mmio_base = RENDER_RING_BASE;
2296
2297 if (INTEL_INFO(dev)->gen >= 8) {
2298 if (i915_semaphore_is_enabled(dev)) {
2299 obj = i915_gem_alloc_object(dev, 4096);
2300 if (obj == NULL) {
2301 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2302 i915.semaphores = 0;
2303 } else {
2304 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2305 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2306 if (ret != 0) {
2307 drm_gem_object_unreference(&obj->base);
2308 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2309 i915.semaphores = 0;
2310 } else
2311 dev_priv->semaphore_obj = obj;
2312 }
2313 }
2314 if (IS_CHERRYVIEW(dev))
2315 ring->init_context = chv_init_workarounds;
2316 else
2317 ring->init_context = bdw_init_workarounds;
2318 ring->add_request = gen6_add_request;
2319 ring->flush = gen8_render_ring_flush;
2320 ring->irq_get = gen8_ring_get_irq;
2321 ring->irq_put = gen8_ring_put_irq;
2322 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2323 ring->get_seqno = gen6_ring_get_seqno;
2324 ring->set_seqno = ring_set_seqno;
2325 if (i915_semaphore_is_enabled(dev)) {
2326 WARN_ON(!dev_priv->semaphore_obj);
2327 ring->semaphore.sync_to = gen8_ring_sync;
2328 ring->semaphore.signal = gen8_rcs_signal;
2329 GEN8_RING_SEMAPHORE_INIT;
2330 }
2331 } else if (INTEL_INFO(dev)->gen >= 6) {
2332 ring->add_request = gen6_add_request;
2333 ring->flush = gen7_render_ring_flush;
2334 if (INTEL_INFO(dev)->gen == 6)
2335 ring->flush = gen6_render_ring_flush;
2336 ring->irq_get = gen6_ring_get_irq;
2337 ring->irq_put = gen6_ring_put_irq;
2338 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2339 ring->get_seqno = gen6_ring_get_seqno;
2340 ring->set_seqno = ring_set_seqno;
2341 if (i915_semaphore_is_enabled(dev)) {
2342 ring->semaphore.sync_to = gen6_ring_sync;
2343 ring->semaphore.signal = gen6_signal;
2344 /*
2345 * The current semaphore is only applied on pre-gen8
2346 * platform. And there is no VCS2 ring on the pre-gen8
2347 * platform. So the semaphore between RCS and VCS2 is
2348 * initialized as INVALID. Gen8 will initialize the
2349 * sema between VCS2 and RCS later.
2350 */
2351 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2352 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2353 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2354 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2355 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2356 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2357 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2358 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2359 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2360 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2361 }
2362 } else if (IS_GEN5(dev)) {
2363 ring->add_request = pc_render_add_request;
2364 ring->flush = gen4_render_ring_flush;
2365 ring->get_seqno = pc_render_get_seqno;
2366 ring->set_seqno = pc_render_set_seqno;
2367 ring->irq_get = gen5_ring_get_irq;
2368 ring->irq_put = gen5_ring_put_irq;
2369 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2370 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2371 } else {
2372 ring->add_request = i9xx_add_request;
2373 if (INTEL_INFO(dev)->gen < 4)
2374 ring->flush = gen2_render_ring_flush;
2375 else
2376 ring->flush = gen4_render_ring_flush;
2377 ring->get_seqno = ring_get_seqno;
2378 ring->set_seqno = ring_set_seqno;
2379 if (IS_GEN2(dev)) {
2380 ring->irq_get = i8xx_ring_get_irq;
2381 ring->irq_put = i8xx_ring_put_irq;
2382 } else {
2383 ring->irq_get = i9xx_ring_get_irq;
2384 ring->irq_put = i9xx_ring_put_irq;
2385 }
2386 ring->irq_enable_mask = I915_USER_INTERRUPT;
2387 }
2388 ring->write_tail = ring_write_tail;
2389
2390 if (IS_HASWELL(dev))
2391 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2392 else if (IS_GEN8(dev))
2393 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2394 else if (INTEL_INFO(dev)->gen >= 6)
2395 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2396 else if (INTEL_INFO(dev)->gen >= 4)
2397 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2398 else if (IS_I830(dev) || IS_845G(dev))
2399 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2400 else
2401 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2402 ring->init = init_render_ring;
2403 ring->cleanup = render_ring_cleanup;
2404
2405 /* Workaround batchbuffer to combat CS tlb bug. */
2406 if (HAS_BROKEN_CS_TLB(dev)) {
2407 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2408 if (obj == NULL) {
2409 DRM_ERROR("Failed to allocate batch bo\n");
2410 return -ENOMEM;
2411 }
2412
2413 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2414 if (ret != 0) {
2415 drm_gem_object_unreference(&obj->base);
2416 DRM_ERROR("Failed to ping batch bo\n");
2417 return ret;
2418 }
2419
2420 ring->scratch.obj = obj;
2421 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2422 }
2423
2424 return intel_init_ring_buffer(dev, ring);
2425 }
2426
intel_render_ring_init_dri(struct drm_device * dev,u64 start,u32 size)2427 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2428 {
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2431 struct intel_ringbuffer *ringbuf = ring->buffer;
2432 int ret;
2433
2434 if (ringbuf == NULL) {
2435 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2436 if (!ringbuf)
2437 return -ENOMEM;
2438 ring->buffer = ringbuf;
2439 }
2440
2441 ring->name = "render ring";
2442 ring->id = RCS;
2443 ring->mmio_base = RENDER_RING_BASE;
2444
2445 if (INTEL_INFO(dev)->gen >= 6) {
2446 /* non-kms not supported on gen6+ */
2447 ret = -ENODEV;
2448 goto err_ringbuf;
2449 }
2450
2451 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2452 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2453 * the special gen5 functions. */
2454 ring->add_request = i9xx_add_request;
2455 if (INTEL_INFO(dev)->gen < 4)
2456 ring->flush = gen2_render_ring_flush;
2457 else
2458 ring->flush = gen4_render_ring_flush;
2459 ring->get_seqno = ring_get_seqno;
2460 ring->set_seqno = ring_set_seqno;
2461 if (IS_GEN2(dev)) {
2462 ring->irq_get = i8xx_ring_get_irq;
2463 ring->irq_put = i8xx_ring_put_irq;
2464 } else {
2465 ring->irq_get = i9xx_ring_get_irq;
2466 ring->irq_put = i9xx_ring_put_irq;
2467 }
2468 ring->irq_enable_mask = I915_USER_INTERRUPT;
2469 ring->write_tail = ring_write_tail;
2470 if (INTEL_INFO(dev)->gen >= 4)
2471 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2472 else if (IS_I830(dev) || IS_845G(dev))
2473 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2474 else
2475 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2476 ring->init = init_render_ring;
2477 ring->cleanup = render_ring_cleanup;
2478
2479 ring->dev = dev;
2480 INIT_LIST_HEAD(&ring->active_list);
2481 INIT_LIST_HEAD(&ring->request_list);
2482
2483 ringbuf->size = size;
2484 ringbuf->effective_size = ringbuf->size;
2485 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2486 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2487
2488 ringbuf->virtual_start = ioremap_wc(start, size);
2489 if (ringbuf->virtual_start == NULL) {
2490 DRM_ERROR("can not ioremap virtual address for"
2491 " ring buffer\n");
2492 ret = -ENOMEM;
2493 goto err_ringbuf;
2494 }
2495
2496 if (!I915_NEED_GFX_HWS(dev)) {
2497 ret = init_phys_status_page(ring);
2498 if (ret)
2499 goto err_vstart;
2500 }
2501
2502 return 0;
2503
2504 err_vstart:
2505 iounmap(ringbuf->virtual_start);
2506 err_ringbuf:
2507 kfree(ringbuf);
2508 ring->buffer = NULL;
2509 return ret;
2510 }
2511
intel_init_bsd_ring_buffer(struct drm_device * dev)2512 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2513 {
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2516
2517 ring->name = "bsd ring";
2518 ring->id = VCS;
2519
2520 ring->write_tail = ring_write_tail;
2521 if (INTEL_INFO(dev)->gen >= 6) {
2522 ring->mmio_base = GEN6_BSD_RING_BASE;
2523 /* gen6 bsd needs a special wa for tail updates */
2524 if (IS_GEN6(dev))
2525 ring->write_tail = gen6_bsd_ring_write_tail;
2526 ring->flush = gen6_bsd_ring_flush;
2527 ring->add_request = gen6_add_request;
2528 ring->get_seqno = gen6_ring_get_seqno;
2529 ring->set_seqno = ring_set_seqno;
2530 if (INTEL_INFO(dev)->gen >= 8) {
2531 ring->irq_enable_mask =
2532 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2533 ring->irq_get = gen8_ring_get_irq;
2534 ring->irq_put = gen8_ring_put_irq;
2535 ring->dispatch_execbuffer =
2536 gen8_ring_dispatch_execbuffer;
2537 if (i915_semaphore_is_enabled(dev)) {
2538 ring->semaphore.sync_to = gen8_ring_sync;
2539 ring->semaphore.signal = gen8_xcs_signal;
2540 GEN8_RING_SEMAPHORE_INIT;
2541 }
2542 } else {
2543 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2544 ring->irq_get = gen6_ring_get_irq;
2545 ring->irq_put = gen6_ring_put_irq;
2546 ring->dispatch_execbuffer =
2547 gen6_ring_dispatch_execbuffer;
2548 if (i915_semaphore_is_enabled(dev)) {
2549 ring->semaphore.sync_to = gen6_ring_sync;
2550 ring->semaphore.signal = gen6_signal;
2551 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2552 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2553 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2554 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2555 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2556 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2557 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2558 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2559 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2560 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2561 }
2562 }
2563 } else {
2564 ring->mmio_base = BSD_RING_BASE;
2565 ring->flush = bsd_ring_flush;
2566 ring->add_request = i9xx_add_request;
2567 ring->get_seqno = ring_get_seqno;
2568 ring->set_seqno = ring_set_seqno;
2569 if (IS_GEN5(dev)) {
2570 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2571 ring->irq_get = gen5_ring_get_irq;
2572 ring->irq_put = gen5_ring_put_irq;
2573 } else {
2574 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2575 ring->irq_get = i9xx_ring_get_irq;
2576 ring->irq_put = i9xx_ring_put_irq;
2577 }
2578 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2579 }
2580 ring->init = init_ring_common;
2581
2582 return intel_init_ring_buffer(dev, ring);
2583 }
2584
2585 /**
2586 * Initialize the second BSD ring for Broadwell GT3.
2587 * It is noted that this only exists on Broadwell GT3.
2588 */
intel_init_bsd2_ring_buffer(struct drm_device * dev)2589 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2590 {
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2593
2594 if ((INTEL_INFO(dev)->gen != 8)) {
2595 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2596 return -EINVAL;
2597 }
2598
2599 ring->name = "bsd2 ring";
2600 ring->id = VCS2;
2601
2602 ring->write_tail = ring_write_tail;
2603 ring->mmio_base = GEN8_BSD2_RING_BASE;
2604 ring->flush = gen6_bsd_ring_flush;
2605 ring->add_request = gen6_add_request;
2606 ring->get_seqno = gen6_ring_get_seqno;
2607 ring->set_seqno = ring_set_seqno;
2608 ring->irq_enable_mask =
2609 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2610 ring->irq_get = gen8_ring_get_irq;
2611 ring->irq_put = gen8_ring_put_irq;
2612 ring->dispatch_execbuffer =
2613 gen8_ring_dispatch_execbuffer;
2614 if (i915_semaphore_is_enabled(dev)) {
2615 ring->semaphore.sync_to = gen8_ring_sync;
2616 ring->semaphore.signal = gen8_xcs_signal;
2617 GEN8_RING_SEMAPHORE_INIT;
2618 }
2619 ring->init = init_ring_common;
2620
2621 return intel_init_ring_buffer(dev, ring);
2622 }
2623
intel_init_blt_ring_buffer(struct drm_device * dev)2624 int intel_init_blt_ring_buffer(struct drm_device *dev)
2625 {
2626 struct drm_i915_private *dev_priv = dev->dev_private;
2627 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2628
2629 ring->name = "blitter ring";
2630 ring->id = BCS;
2631
2632 ring->mmio_base = BLT_RING_BASE;
2633 ring->write_tail = ring_write_tail;
2634 ring->flush = gen6_ring_flush;
2635 ring->add_request = gen6_add_request;
2636 ring->get_seqno = gen6_ring_get_seqno;
2637 ring->set_seqno = ring_set_seqno;
2638 if (INTEL_INFO(dev)->gen >= 8) {
2639 ring->irq_enable_mask =
2640 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2641 ring->irq_get = gen8_ring_get_irq;
2642 ring->irq_put = gen8_ring_put_irq;
2643 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2644 if (i915_semaphore_is_enabled(dev)) {
2645 ring->semaphore.sync_to = gen8_ring_sync;
2646 ring->semaphore.signal = gen8_xcs_signal;
2647 GEN8_RING_SEMAPHORE_INIT;
2648 }
2649 } else {
2650 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2651 ring->irq_get = gen6_ring_get_irq;
2652 ring->irq_put = gen6_ring_put_irq;
2653 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2654 if (i915_semaphore_is_enabled(dev)) {
2655 ring->semaphore.signal = gen6_signal;
2656 ring->semaphore.sync_to = gen6_ring_sync;
2657 /*
2658 * The current semaphore is only applied on pre-gen8
2659 * platform. And there is no VCS2 ring on the pre-gen8
2660 * platform. So the semaphore between BCS and VCS2 is
2661 * initialized as INVALID. Gen8 will initialize the
2662 * sema between BCS and VCS2 later.
2663 */
2664 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2665 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2666 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2667 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2668 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2669 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2670 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2671 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2672 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2673 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2674 }
2675 }
2676 ring->init = init_ring_common;
2677
2678 return intel_init_ring_buffer(dev, ring);
2679 }
2680
intel_init_vebox_ring_buffer(struct drm_device * dev)2681 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2682 {
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2685
2686 ring->name = "video enhancement ring";
2687 ring->id = VECS;
2688
2689 ring->mmio_base = VEBOX_RING_BASE;
2690 ring->write_tail = ring_write_tail;
2691 ring->flush = gen6_ring_flush;
2692 ring->add_request = gen6_add_request;
2693 ring->get_seqno = gen6_ring_get_seqno;
2694 ring->set_seqno = ring_set_seqno;
2695
2696 if (INTEL_INFO(dev)->gen >= 8) {
2697 ring->irq_enable_mask =
2698 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2699 ring->irq_get = gen8_ring_get_irq;
2700 ring->irq_put = gen8_ring_put_irq;
2701 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2702 if (i915_semaphore_is_enabled(dev)) {
2703 ring->semaphore.sync_to = gen8_ring_sync;
2704 ring->semaphore.signal = gen8_xcs_signal;
2705 GEN8_RING_SEMAPHORE_INIT;
2706 }
2707 } else {
2708 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2709 ring->irq_get = hsw_vebox_get_irq;
2710 ring->irq_put = hsw_vebox_put_irq;
2711 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2712 if (i915_semaphore_is_enabled(dev)) {
2713 ring->semaphore.sync_to = gen6_ring_sync;
2714 ring->semaphore.signal = gen6_signal;
2715 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2716 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2717 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2718 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2719 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2720 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2721 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2722 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2723 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2724 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2725 }
2726 }
2727 ring->init = init_ring_common;
2728
2729 return intel_init_ring_buffer(dev, ring);
2730 }
2731
2732 int
intel_ring_flush_all_caches(struct intel_engine_cs * ring)2733 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2734 {
2735 int ret;
2736
2737 if (!ring->gpu_caches_dirty)
2738 return 0;
2739
2740 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2741 if (ret)
2742 return ret;
2743
2744 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2745
2746 ring->gpu_caches_dirty = false;
2747 return 0;
2748 }
2749
2750 int
intel_ring_invalidate_all_caches(struct intel_engine_cs * ring)2751 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2752 {
2753 uint32_t flush_domains;
2754 int ret;
2755
2756 flush_domains = 0;
2757 if (ring->gpu_caches_dirty)
2758 flush_domains = I915_GEM_GPU_DOMAINS;
2759
2760 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2761 if (ret)
2762 return ret;
2763
2764 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2765
2766 ring->gpu_caches_dirty = false;
2767 return 0;
2768 }
2769
2770 void
intel_stop_ring_buffer(struct intel_engine_cs * ring)2771 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2772 {
2773 int ret;
2774
2775 if (!intel_ring_initialized(ring))
2776 return;
2777
2778 ret = intel_ring_idle(ring);
2779 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2780 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2781 ring->name, ret);
2782
2783 stop_ring(ring);
2784 }
2785