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1 /****************************************************************************
2  * Driver for Solarflare network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2005-2013 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10 
11 /* Common definitions for all Efx net driver code */
12 
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
15 
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/vmalloc.h>
29 #include <linux/i2c.h>
30 #include <linux/mtd/mtd.h>
31 #include <net/busy_poll.h>
32 
33 #include "enum.h"
34 #include "bitfield.h"
35 #include "filter.h"
36 
37 /**************************************************************************
38  *
39  * Build definitions
40  *
41  **************************************************************************/
42 
43 #define EFX_DRIVER_VERSION	"4.0"
44 
45 #ifdef DEBUG
46 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
47 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
48 #else
49 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
50 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
51 #endif
52 
53 /**************************************************************************
54  *
55  * Efx data structures
56  *
57  **************************************************************************/
58 
59 #define EFX_MAX_CHANNELS 32U
60 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
61 #define EFX_EXTRA_CHANNEL_IOV	0
62 #define EFX_EXTRA_CHANNEL_PTP	1
63 #define EFX_MAX_EXTRA_CHANNELS	2U
64 
65 /* Checksum generation is a per-queue option in hardware, so each
66  * queue visible to the networking core is backed by two hardware TX
67  * queues. */
68 #define EFX_MAX_TX_TC		2
69 #define EFX_MAX_CORE_TX_QUEUES	(EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
70 #define EFX_TXQ_TYPE_OFFLOAD	1	/* flag */
71 #define EFX_TXQ_TYPE_HIGHPRI	2	/* flag */
72 #define EFX_TXQ_TYPES		4
73 #define EFX_MAX_TX_QUEUES	(EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
74 
75 /* Maximum possible MTU the driver supports */
76 #define EFX_MAX_MTU (9 * 1024)
77 
78 /* Size of an RX scatter buffer.  Small enough to pack 2 into a 4K page,
79  * and should be a multiple of the cache line size.
80  */
81 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
82 
83 /* If possible, we should ensure cache line alignment at start and end
84  * of every buffer.  Otherwise, we just need to ensure 4-byte
85  * alignment of the network header.
86  */
87 #if NET_IP_ALIGN == 0
88 #define EFX_RX_BUF_ALIGNMENT	L1_CACHE_BYTES
89 #else
90 #define EFX_RX_BUF_ALIGNMENT	4
91 #endif
92 
93 /* Forward declare Precision Time Protocol (PTP) support structure. */
94 struct efx_ptp_data;
95 struct hwtstamp_config;
96 
97 struct efx_self_tests;
98 
99 /**
100  * struct efx_buffer - A general-purpose DMA buffer
101  * @addr: host base address of the buffer
102  * @dma_addr: DMA base address of the buffer
103  * @len: Buffer length, in bytes
104  *
105  * The NIC uses these buffers for its interrupt status registers and
106  * MAC stats dumps.
107  */
108 struct efx_buffer {
109 	void *addr;
110 	dma_addr_t dma_addr;
111 	unsigned int len;
112 };
113 
114 /**
115  * struct efx_special_buffer - DMA buffer entered into buffer table
116  * @buf: Standard &struct efx_buffer
117  * @index: Buffer index within controller;s buffer table
118  * @entries: Number of buffer table entries
119  *
120  * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
121  * Event and descriptor rings are addressed via one or more buffer
122  * table entries (and so can be physically non-contiguous, although we
123  * currently do not take advantage of that).  On Falcon and Siena we
124  * have to take care of allocating and initialising the entries
125  * ourselves.  On later hardware this is managed by the firmware and
126  * @index and @entries are left as 0.
127  */
128 struct efx_special_buffer {
129 	struct efx_buffer buf;
130 	unsigned int index;
131 	unsigned int entries;
132 };
133 
134 /**
135  * struct efx_tx_buffer - buffer state for a TX descriptor
136  * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
137  *	freed when descriptor completes
138  * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
139  *	freed when descriptor completes.
140  * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
141  * @dma_addr: DMA address of the fragment.
142  * @flags: Flags for allocation and DMA mapping type
143  * @len: Length of this fragment.
144  *	This field is zero when the queue slot is empty.
145  * @unmap_len: Length of this fragment to unmap
146  * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
147  * Only valid if @unmap_len != 0.
148  */
149 struct efx_tx_buffer {
150 	union {
151 		const struct sk_buff *skb;
152 		void *heap_buf;
153 	};
154 	union {
155 		efx_qword_t option;
156 		dma_addr_t dma_addr;
157 	};
158 	unsigned short flags;
159 	unsigned short len;
160 	unsigned short unmap_len;
161 	unsigned short dma_offset;
162 };
163 #define EFX_TX_BUF_CONT		1	/* not last descriptor of packet */
164 #define EFX_TX_BUF_SKB		2	/* buffer is last part of skb */
165 #define EFX_TX_BUF_HEAP		4	/* buffer was allocated with kmalloc() */
166 #define EFX_TX_BUF_MAP_SINGLE	8	/* buffer was mapped with dma_map_single() */
167 #define EFX_TX_BUF_OPTION	0x10	/* empty buffer for option descriptor */
168 
169 /**
170  * struct efx_tx_queue - An Efx TX queue
171  *
172  * This is a ring buffer of TX fragments.
173  * Since the TX completion path always executes on the same
174  * CPU and the xmit path can operate on different CPUs,
175  * performance is increased by ensuring that the completion
176  * path and the xmit path operate on different cache lines.
177  * This is particularly important if the xmit path is always
178  * executing on one CPU which is different from the completion
179  * path.  There is also a cache line for members which are
180  * read but not written on the fast path.
181  *
182  * @efx: The associated Efx NIC
183  * @queue: DMA queue number
184  * @channel: The associated channel
185  * @core_txq: The networking core TX queue structure
186  * @buffer: The software buffer ring
187  * @tsoh_page: Array of pages of TSO header buffers
188  * @txd: The hardware descriptor ring
189  * @ptr_mask: The size of the ring minus 1.
190  * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191  *	Size of the region is efx_piobuf_size.
192  * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193  * @initialised: Has hardware queue been initialised?
194  * @read_count: Current read pointer.
195  *	This is the number of buffers that have been removed from both rings.
196  * @old_write_count: The value of @write_count when last checked.
197  *	This is here for performance reasons.  The xmit path will
198  *	only get the up-to-date value of @write_count if this
199  *	variable indicates that the queue is empty.  This is to
200  *	avoid cache-line ping-pong between the xmit path and the
201  *	completion path.
202  * @merge_events: Number of TX merged completion events
203  * @insert_count: Current insert pointer
204  *	This is the number of buffers that have been added to the
205  *	software ring.
206  * @write_count: Current write pointer
207  *	This is the number of buffers that have been added to the
208  *	hardware ring.
209  * @old_read_count: The value of read_count when last checked.
210  *	This is here for performance reasons.  The xmit path will
211  *	only get the up-to-date value of read_count if this
212  *	variable indicates that the queue is full.  This is to
213  *	avoid cache-line ping-pong between the xmit path and the
214  *	completion path.
215  * @tso_bursts: Number of times TSO xmit invoked by kernel
216  * @tso_long_headers: Number of packets with headers too long for standard
217  *	blocks
218  * @tso_packets: Number of packets via the TSO xmit path
219  * @pushes: Number of times the TX push feature has been used
220  * @pio_packets: Number of times the TX PIO feature has been used
221  * @xmit_more_available: Are any packets waiting to be pushed to the NIC
222  * @empty_read_count: If the completion path has seen the queue as empty
223  *	and the transmission path has not yet checked this, the value of
224  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
225  */
226 struct efx_tx_queue {
227 	/* Members which don't change on the fast path */
228 	struct efx_nic *efx ____cacheline_aligned_in_smp;
229 	unsigned queue;
230 	struct efx_channel *channel;
231 	struct netdev_queue *core_txq;
232 	struct efx_tx_buffer *buffer;
233 	struct efx_buffer *tsoh_page;
234 	struct efx_special_buffer txd;
235 	unsigned int ptr_mask;
236 	void __iomem *piobuf;
237 	unsigned int piobuf_offset;
238 	bool initialised;
239 
240 	/* Members used mainly on the completion path */
241 	unsigned int read_count ____cacheline_aligned_in_smp;
242 	unsigned int old_write_count;
243 	unsigned int merge_events;
244 
245 	/* Members used only on the xmit path */
246 	unsigned int insert_count ____cacheline_aligned_in_smp;
247 	unsigned int write_count;
248 	unsigned int old_read_count;
249 	unsigned int tso_bursts;
250 	unsigned int tso_long_headers;
251 	unsigned int tso_packets;
252 	unsigned int pushes;
253 	unsigned int pio_packets;
254 	bool xmit_more_available;
255 	/* Statistics to supplement MAC stats */
256 	unsigned long tx_packets;
257 
258 	/* Members shared between paths and sometimes updated */
259 	unsigned int empty_read_count ____cacheline_aligned_in_smp;
260 #define EFX_EMPTY_COUNT_VALID 0x80000000
261 	atomic_t flush_outstanding;
262 };
263 
264 /**
265  * struct efx_rx_buffer - An Efx RX data buffer
266  * @dma_addr: DMA base address of the buffer
267  * @page: The associated page buffer.
268  *	Will be %NULL if the buffer slot is currently free.
269  * @page_offset: If pending: offset in @page of DMA base address.
270  *	If completed: offset in @page of Ethernet header.
271  * @len: If pending: length for DMA descriptor.
272  *	If completed: received length, excluding hash prefix.
273  * @flags: Flags for buffer and packet state.  These are only set on the
274  *	first buffer of a scattered packet.
275  */
276 struct efx_rx_buffer {
277 	dma_addr_t dma_addr;
278 	struct page *page;
279 	u16 page_offset;
280 	u16 len;
281 	u16 flags;
282 };
283 #define EFX_RX_BUF_LAST_IN_PAGE	0x0001
284 #define EFX_RX_PKT_CSUMMED	0x0002
285 #define EFX_RX_PKT_DISCARD	0x0004
286 #define EFX_RX_PKT_TCP		0x0040
287 #define EFX_RX_PKT_PREFIX_LEN	0x0080	/* length is in prefix only */
288 
289 /**
290  * struct efx_rx_page_state - Page-based rx buffer state
291  *
292  * Inserted at the start of every page allocated for receive buffers.
293  * Used to facilitate sharing dma mappings between recycled rx buffers
294  * and those passed up to the kernel.
295  *
296  * @dma_addr: The dma address of this page.
297  */
298 struct efx_rx_page_state {
299 	dma_addr_t dma_addr;
300 
301 	unsigned int __pad[0] ____cacheline_aligned;
302 };
303 
304 /**
305  * struct efx_rx_queue - An Efx RX queue
306  * @efx: The associated Efx NIC
307  * @core_index:  Index of network core RX queue.  Will be >= 0 iff this
308  *	is associated with a real RX queue.
309  * @buffer: The software buffer ring
310  * @rxd: The hardware descriptor ring
311  * @ptr_mask: The size of the ring minus 1.
312  * @refill_enabled: Enable refill whenever fill level is low
313  * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
314  *	@rxq_flush_pending.
315  * @added_count: Number of buffers added to the receive queue.
316  * @notified_count: Number of buffers given to NIC (<= @added_count).
317  * @removed_count: Number of buffers removed from the receive queue.
318  * @scatter_n: Used by NIC specific receive code.
319  * @scatter_len: Used by NIC specific receive code.
320  * @page_ring: The ring to store DMA mapped pages for reuse.
321  * @page_add: Counter to calculate the write pointer for the recycle ring.
322  * @page_remove: Counter to calculate the read pointer for the recycle ring.
323  * @page_recycle_count: The number of pages that have been recycled.
324  * @page_recycle_failed: The number of pages that couldn't be recycled because
325  *      the kernel still held a reference to them.
326  * @page_recycle_full: The number of pages that were released because the
327  *      recycle ring was full.
328  * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
329  * @max_fill: RX descriptor maximum fill level (<= ring size)
330  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
331  *	(<= @max_fill)
332  * @min_fill: RX descriptor minimum non-zero fill level.
333  *	This records the minimum fill level observed when a ring
334  *	refill was triggered.
335  * @recycle_count: RX buffer recycle counter.
336  * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
337  */
338 struct efx_rx_queue {
339 	struct efx_nic *efx;
340 	int core_index;
341 	struct efx_rx_buffer *buffer;
342 	struct efx_special_buffer rxd;
343 	unsigned int ptr_mask;
344 	bool refill_enabled;
345 	bool flush_pending;
346 
347 	unsigned int added_count;
348 	unsigned int notified_count;
349 	unsigned int removed_count;
350 	unsigned int scatter_n;
351 	unsigned int scatter_len;
352 	struct page **page_ring;
353 	unsigned int page_add;
354 	unsigned int page_remove;
355 	unsigned int page_recycle_count;
356 	unsigned int page_recycle_failed;
357 	unsigned int page_recycle_full;
358 	unsigned int page_ptr_mask;
359 	unsigned int max_fill;
360 	unsigned int fast_fill_trigger;
361 	unsigned int min_fill;
362 	unsigned int min_overfill;
363 	unsigned int recycle_count;
364 	struct timer_list slow_fill;
365 	unsigned int slow_fill_count;
366 	/* Statistics to supplement MAC stats */
367 	unsigned long rx_packets;
368 };
369 
370 enum efx_sync_events_state {
371 	SYNC_EVENTS_DISABLED = 0,
372 	SYNC_EVENTS_QUIESCENT,
373 	SYNC_EVENTS_REQUESTED,
374 	SYNC_EVENTS_VALID,
375 };
376 
377 /**
378  * struct efx_channel - An Efx channel
379  *
380  * A channel comprises an event queue, at least one TX queue, at least
381  * one RX queue, and an associated tasklet for processing the event
382  * queue.
383  *
384  * @efx: Associated Efx NIC
385  * @channel: Channel instance number
386  * @type: Channel type definition
387  * @eventq_init: Event queue initialised flag
388  * @enabled: Channel enabled indicator
389  * @irq: IRQ number (MSI and MSI-X only)
390  * @irq_moderation: IRQ moderation value (in hardware ticks)
391  * @napi_dev: Net device used with NAPI
392  * @napi_str: NAPI control structure
393  * @state: state for NAPI vs busy polling
394  * @state_lock: lock protecting @state
395  * @eventq: Event queue buffer
396  * @eventq_mask: Event queue pointer mask
397  * @eventq_read_ptr: Event queue read pointer
398  * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
399  * @irq_count: Number of IRQs since last adaptive moderation decision
400  * @irq_mod_score: IRQ moderation score
401  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
402  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
403  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
404  * @n_rx_mcast_mismatch: Count of unmatched multicast frames
405  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
406  * @n_rx_overlength: Count of RX_OVERLENGTH errors
407  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
408  * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
409  *	lack of descriptors
410  * @n_rx_merge_events: Number of RX merged completion events
411  * @n_rx_merge_packets: Number of RX packets completed by merged events
412  * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
413  *	__efx_rx_packet(), or zero if there is none
414  * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
415  *	by __efx_rx_packet(), if @rx_pkt_n_frags != 0
416  * @rx_queue: RX queue for this channel
417  * @tx_queue: TX queues for this channel
418  * @sync_events_state: Current state of sync events on this channel
419  * @sync_timestamp_major: Major part of the last ptp sync event
420  * @sync_timestamp_minor: Minor part of the last ptp sync event
421  */
422 struct efx_channel {
423 	struct efx_nic *efx;
424 	int channel;
425 	const struct efx_channel_type *type;
426 	bool eventq_init;
427 	bool enabled;
428 	int irq;
429 	unsigned int irq_moderation;
430 	struct net_device *napi_dev;
431 	struct napi_struct napi_str;
432 #ifdef CONFIG_NET_RX_BUSY_POLL
433 	unsigned int state;
434 	spinlock_t state_lock;
435 #define EFX_CHANNEL_STATE_IDLE		0
436 #define EFX_CHANNEL_STATE_NAPI		(1 << 0)  /* NAPI owns this channel */
437 #define EFX_CHANNEL_STATE_POLL		(1 << 1)  /* poll owns this channel */
438 #define EFX_CHANNEL_STATE_DISABLED	(1 << 2)  /* channel is disabled */
439 #define EFX_CHANNEL_STATE_NAPI_YIELD	(1 << 3)  /* NAPI yielded this channel */
440 #define EFX_CHANNEL_STATE_POLL_YIELD	(1 << 4)  /* poll yielded this channel */
441 #define EFX_CHANNEL_OWNED \
442 	(EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL)
443 #define EFX_CHANNEL_LOCKED \
444 	(EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED)
445 #define EFX_CHANNEL_USER_PEND \
446 	(EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD)
447 #endif /* CONFIG_NET_RX_BUSY_POLL */
448 	struct efx_special_buffer eventq;
449 	unsigned int eventq_mask;
450 	unsigned int eventq_read_ptr;
451 	int event_test_cpu;
452 
453 	unsigned int irq_count;
454 	unsigned int irq_mod_score;
455 #ifdef CONFIG_RFS_ACCEL
456 	unsigned int rfs_filters_added;
457 #endif
458 
459 	unsigned n_rx_tobe_disc;
460 	unsigned n_rx_ip_hdr_chksum_err;
461 	unsigned n_rx_tcp_udp_chksum_err;
462 	unsigned n_rx_mcast_mismatch;
463 	unsigned n_rx_frm_trunc;
464 	unsigned n_rx_overlength;
465 	unsigned n_skbuff_leaks;
466 	unsigned int n_rx_nodesc_trunc;
467 	unsigned int n_rx_merge_events;
468 	unsigned int n_rx_merge_packets;
469 
470 	unsigned int rx_pkt_n_frags;
471 	unsigned int rx_pkt_index;
472 
473 	struct efx_rx_queue rx_queue;
474 	struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
475 
476 	enum efx_sync_events_state sync_events_state;
477 	u32 sync_timestamp_major;
478 	u32 sync_timestamp_minor;
479 };
480 
481 #ifdef CONFIG_NET_RX_BUSY_POLL
efx_channel_init_lock(struct efx_channel * channel)482 static inline void efx_channel_init_lock(struct efx_channel *channel)
483 {
484 	spin_lock_init(&channel->state_lock);
485 }
486 
487 /* Called from the device poll routine to get ownership of a channel. */
efx_channel_lock_napi(struct efx_channel * channel)488 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
489 {
490 	bool rc = true;
491 
492 	spin_lock_bh(&channel->state_lock);
493 	if (channel->state & EFX_CHANNEL_LOCKED) {
494 		WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
495 		channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD;
496 		rc = false;
497 	} else {
498 		/* we don't care if someone yielded */
499 		channel->state = EFX_CHANNEL_STATE_NAPI;
500 	}
501 	spin_unlock_bh(&channel->state_lock);
502 	return rc;
503 }
504 
efx_channel_unlock_napi(struct efx_channel * channel)505 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
506 {
507 	spin_lock_bh(&channel->state_lock);
508 	WARN_ON(channel->state &
509 		(EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD));
510 
511 	channel->state &= EFX_CHANNEL_STATE_DISABLED;
512 	spin_unlock_bh(&channel->state_lock);
513 }
514 
515 /* Called from efx_busy_poll(). */
efx_channel_lock_poll(struct efx_channel * channel)516 static inline bool efx_channel_lock_poll(struct efx_channel *channel)
517 {
518 	bool rc = true;
519 
520 	spin_lock_bh(&channel->state_lock);
521 	if ((channel->state & EFX_CHANNEL_LOCKED)) {
522 		channel->state |= EFX_CHANNEL_STATE_POLL_YIELD;
523 		rc = false;
524 	} else {
525 		/* preserve yield marks */
526 		channel->state |= EFX_CHANNEL_STATE_POLL;
527 	}
528 	spin_unlock_bh(&channel->state_lock);
529 	return rc;
530 }
531 
532 /* Returns true if NAPI tried to get the channel while it was locked. */
efx_channel_unlock_poll(struct efx_channel * channel)533 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
534 {
535 	spin_lock_bh(&channel->state_lock);
536 	WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
537 
538 	/* will reset state to idle, unless channel is disabled */
539 	channel->state &= EFX_CHANNEL_STATE_DISABLED;
540 	spin_unlock_bh(&channel->state_lock);
541 }
542 
543 /* True if a socket is polling, even if it did not get the lock. */
efx_channel_busy_polling(struct efx_channel * channel)544 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
545 {
546 	WARN_ON(!(channel->state & EFX_CHANNEL_OWNED));
547 	return channel->state & EFX_CHANNEL_USER_PEND;
548 }
549 
efx_channel_enable(struct efx_channel * channel)550 static inline void efx_channel_enable(struct efx_channel *channel)
551 {
552 	spin_lock_bh(&channel->state_lock);
553 	channel->state = EFX_CHANNEL_STATE_IDLE;
554 	spin_unlock_bh(&channel->state_lock);
555 }
556 
557 /* False if the channel is currently owned. */
efx_channel_disable(struct efx_channel * channel)558 static inline bool efx_channel_disable(struct efx_channel *channel)
559 {
560 	bool rc = true;
561 
562 	spin_lock_bh(&channel->state_lock);
563 	if (channel->state & EFX_CHANNEL_OWNED)
564 		rc = false;
565 	channel->state |= EFX_CHANNEL_STATE_DISABLED;
566 	spin_unlock_bh(&channel->state_lock);
567 
568 	return rc;
569 }
570 
571 #else /* CONFIG_NET_RX_BUSY_POLL */
572 
efx_channel_init_lock(struct efx_channel * channel)573 static inline void efx_channel_init_lock(struct efx_channel *channel)
574 {
575 }
576 
efx_channel_lock_napi(struct efx_channel * channel)577 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
578 {
579 	return true;
580 }
581 
efx_channel_unlock_napi(struct efx_channel * channel)582 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
583 {
584 }
585 
efx_channel_lock_poll(struct efx_channel * channel)586 static inline bool efx_channel_lock_poll(struct efx_channel *channel)
587 {
588 	return false;
589 }
590 
efx_channel_unlock_poll(struct efx_channel * channel)591 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
592 {
593 }
594 
efx_channel_busy_polling(struct efx_channel * channel)595 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
596 {
597 	return false;
598 }
599 
efx_channel_enable(struct efx_channel * channel)600 static inline void efx_channel_enable(struct efx_channel *channel)
601 {
602 }
603 
efx_channel_disable(struct efx_channel * channel)604 static inline bool efx_channel_disable(struct efx_channel *channel)
605 {
606 	return true;
607 }
608 #endif /* CONFIG_NET_RX_BUSY_POLL */
609 
610 /**
611  * struct efx_msi_context - Context for each MSI
612  * @efx: The associated NIC
613  * @index: Index of the channel/IRQ
614  * @name: Name of the channel/IRQ
615  *
616  * Unlike &struct efx_channel, this is never reallocated and is always
617  * safe for the IRQ handler to access.
618  */
619 struct efx_msi_context {
620 	struct efx_nic *efx;
621 	unsigned int index;
622 	char name[IFNAMSIZ + 6];
623 };
624 
625 /**
626  * struct efx_channel_type - distinguishes traffic and extra channels
627  * @handle_no_channel: Handle failure to allocate an extra channel
628  * @pre_probe: Set up extra state prior to initialisation
629  * @post_remove: Tear down extra state after finalisation, if allocated.
630  *	May be called on channels that have not been probed.
631  * @get_name: Generate the channel's name (used for its IRQ handler)
632  * @copy: Copy the channel state prior to reallocation.  May be %NULL if
633  *	reallocation is not supported.
634  * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
635  * @keep_eventq: Flag for whether event queue should be kept initialised
636  *	while the device is stopped
637  */
638 struct efx_channel_type {
639 	void (*handle_no_channel)(struct efx_nic *);
640 	int (*pre_probe)(struct efx_channel *);
641 	void (*post_remove)(struct efx_channel *);
642 	void (*get_name)(struct efx_channel *, char *buf, size_t len);
643 	struct efx_channel *(*copy)(const struct efx_channel *);
644 	bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
645 	bool keep_eventq;
646 };
647 
648 enum efx_led_mode {
649 	EFX_LED_OFF	= 0,
650 	EFX_LED_ON	= 1,
651 	EFX_LED_DEFAULT	= 2
652 };
653 
654 #define STRING_TABLE_LOOKUP(val, member) \
655 	((val) < member ## _max) ? member ## _names[val] : "(invalid)"
656 
657 extern const char *const efx_loopback_mode_names[];
658 extern const unsigned int efx_loopback_mode_max;
659 #define LOOPBACK_MODE(efx) \
660 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
661 
662 extern const char *const efx_reset_type_names[];
663 extern const unsigned int efx_reset_type_max;
664 #define RESET_TYPE(type) \
665 	STRING_TABLE_LOOKUP(type, efx_reset_type)
666 
667 enum efx_int_mode {
668 	/* Be careful if altering to correct macro below */
669 	EFX_INT_MODE_MSIX = 0,
670 	EFX_INT_MODE_MSI = 1,
671 	EFX_INT_MODE_LEGACY = 2,
672 	EFX_INT_MODE_MAX	/* Insert any new items before this */
673 };
674 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
675 
676 enum nic_state {
677 	STATE_UNINIT = 0,	/* device being probed/removed or is frozen */
678 	STATE_READY = 1,	/* hardware ready and netdev registered */
679 	STATE_DISABLED = 2,	/* device disabled due to hardware errors */
680 	STATE_RECOVERY = 3,	/* device recovering from PCI error */
681 };
682 
683 /* Forward declaration */
684 struct efx_nic;
685 
686 /* Pseudo bit-mask flow control field */
687 #define EFX_FC_RX	FLOW_CTRL_RX
688 #define EFX_FC_TX	FLOW_CTRL_TX
689 #define EFX_FC_AUTO	4
690 
691 /**
692  * struct efx_link_state - Current state of the link
693  * @up: Link is up
694  * @fd: Link is full-duplex
695  * @fc: Actual flow control flags
696  * @speed: Link speed (Mbps)
697  */
698 struct efx_link_state {
699 	bool up;
700 	bool fd;
701 	u8 fc;
702 	unsigned int speed;
703 };
704 
efx_link_state_equal(const struct efx_link_state * left,const struct efx_link_state * right)705 static inline bool efx_link_state_equal(const struct efx_link_state *left,
706 					const struct efx_link_state *right)
707 {
708 	return left->up == right->up && left->fd == right->fd &&
709 		left->fc == right->fc && left->speed == right->speed;
710 }
711 
712 /**
713  * struct efx_phy_operations - Efx PHY operations table
714  * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
715  *	efx->loopback_modes.
716  * @init: Initialise PHY
717  * @fini: Shut down PHY
718  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
719  * @poll: Update @link_state and report whether it changed.
720  *	Serialised by the mac_lock.
721  * @get_settings: Get ethtool settings. Serialised by the mac_lock.
722  * @set_settings: Set ethtool settings. Serialised by the mac_lock.
723  * @set_npage_adv: Set abilities advertised in (Extended) Next Page
724  *	(only needed where AN bit is set in mmds)
725  * @test_alive: Test that PHY is 'alive' (online)
726  * @test_name: Get the name of a PHY-specific test/result
727  * @run_tests: Run tests and record results as appropriate (offline).
728  *	Flags are the ethtool tests flags.
729  */
730 struct efx_phy_operations {
731 	int (*probe) (struct efx_nic *efx);
732 	int (*init) (struct efx_nic *efx);
733 	void (*fini) (struct efx_nic *efx);
734 	void (*remove) (struct efx_nic *efx);
735 	int (*reconfigure) (struct efx_nic *efx);
736 	bool (*poll) (struct efx_nic *efx);
737 	void (*get_settings) (struct efx_nic *efx,
738 			      struct ethtool_cmd *ecmd);
739 	int (*set_settings) (struct efx_nic *efx,
740 			     struct ethtool_cmd *ecmd);
741 	void (*set_npage_adv) (struct efx_nic *efx, u32);
742 	int (*test_alive) (struct efx_nic *efx);
743 	const char *(*test_name) (struct efx_nic *efx, unsigned int index);
744 	int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
745 	int (*get_module_eeprom) (struct efx_nic *efx,
746 			       struct ethtool_eeprom *ee,
747 			       u8 *data);
748 	int (*get_module_info) (struct efx_nic *efx,
749 				struct ethtool_modinfo *modinfo);
750 };
751 
752 /**
753  * enum efx_phy_mode - PHY operating mode flags
754  * @PHY_MODE_NORMAL: on and should pass traffic
755  * @PHY_MODE_TX_DISABLED: on with TX disabled
756  * @PHY_MODE_LOW_POWER: set to low power through MDIO
757  * @PHY_MODE_OFF: switched off through external control
758  * @PHY_MODE_SPECIAL: on but will not pass traffic
759  */
760 enum efx_phy_mode {
761 	PHY_MODE_NORMAL		= 0,
762 	PHY_MODE_TX_DISABLED	= 1,
763 	PHY_MODE_LOW_POWER	= 2,
764 	PHY_MODE_OFF		= 4,
765 	PHY_MODE_SPECIAL	= 8,
766 };
767 
efx_phy_mode_disabled(enum efx_phy_mode mode)768 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
769 {
770 	return !!(mode & ~PHY_MODE_TX_DISABLED);
771 }
772 
773 /**
774  * struct efx_hw_stat_desc - Description of a hardware statistic
775  * @name: Name of the statistic as visible through ethtool, or %NULL if
776  *	it should not be exposed
777  * @dma_width: Width in bits (0 for non-DMA statistics)
778  * @offset: Offset within stats (ignored for non-DMA statistics)
779  */
780 struct efx_hw_stat_desc {
781 	const char *name;
782 	u16 dma_width;
783 	u16 offset;
784 };
785 
786 /* Number of bits used in a multicast filter hash address */
787 #define EFX_MCAST_HASH_BITS 8
788 
789 /* Number of (single-bit) entries in a multicast filter hash */
790 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
791 
792 /* An Efx multicast filter hash */
793 union efx_multicast_hash {
794 	u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
795 	efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
796 };
797 
798 struct efx_vf;
799 struct vfdi_status;
800 
801 /**
802  * struct efx_nic - an Efx NIC
803  * @name: Device name (net device name or bus id before net device registered)
804  * @pci_dev: The PCI device
805  * @node: List node for maintaning primary/secondary function lists
806  * @primary: &struct efx_nic instance for the primary function of this
807  *	controller.  May be the same structure, and may be %NULL if no
808  *	primary function is bound.  Serialised by rtnl_lock.
809  * @secondary_list: List of &struct efx_nic instances for the secondary PCI
810  *	functions of the controller, if this is for the primary function.
811  *	Serialised by rtnl_lock.
812  * @type: Controller type attributes
813  * @legacy_irq: IRQ number
814  * @workqueue: Workqueue for port reconfigures and the HW monitor.
815  *	Work items do not hold and must not acquire RTNL.
816  * @workqueue_name: Name of workqueue
817  * @reset_work: Scheduled reset workitem
818  * @membase_phys: Memory BAR value as physical address
819  * @membase: Memory BAR value
820  * @interrupt_mode: Interrupt mode
821  * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
822  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
823  * @irq_rx_moderation: IRQ moderation time for RX event queues
824  * @msg_enable: Log message enable flags
825  * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
826  * @reset_pending: Bitmask for pending resets
827  * @tx_queue: TX DMA queues
828  * @rx_queue: RX DMA queues
829  * @channel: Channels
830  * @msi_context: Context for each MSI
831  * @extra_channel_types: Types of extra (non-traffic) channels that
832  *	should be allocated for this NIC
833  * @rxq_entries: Size of receive queues requested by user.
834  * @txq_entries: Size of transmit queues requested by user.
835  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
836  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
837  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
838  * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
839  * @sram_lim_qw: Qword address limit of SRAM
840  * @next_buffer_table: First available buffer table id
841  * @n_channels: Number of channels in use
842  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
843  * @n_tx_channels: Number of channels used for TX
844  * @rx_ip_align: RX DMA address offset to have IP header aligned in
845  *	in accordance with NET_IP_ALIGN
846  * @rx_dma_len: Current maximum RX DMA length
847  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
848  * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
849  *	for use in sk_buff::truesize
850  * @rx_prefix_size: Size of RX prefix before packet data
851  * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
852  *	(valid only if @rx_prefix_size != 0; always negative)
853  * @rx_packet_len_offset: Offset of RX packet length from start of packet data
854  *	(valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
855  * @rx_packet_ts_offset: Offset of timestamp from start of packet data
856  *	(valid only if channel->sync_timestamps_enabled; always negative)
857  * @rx_hash_key: Toeplitz hash key for RSS
858  * @rx_indir_table: Indirection table for RSS
859  * @rx_scatter: Scatter mode enabled for receives
860  * @int_error_count: Number of internal errors seen recently
861  * @int_error_expire: Time at which error count will be expired
862  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
863  *	acknowledge but do nothing else.
864  * @irq_status: Interrupt status buffer
865  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
866  * @irq_level: IRQ level/index for IRQs not triggered by an event queue
867  * @selftest_work: Work item for asynchronous self-test
868  * @mtd_list: List of MTDs attached to the NIC
869  * @nic_data: Hardware dependent state
870  * @mcdi: Management-Controller-to-Driver Interface state
871  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
872  *	efx_monitor() and efx_reconfigure_port()
873  * @port_enabled: Port enabled indicator.
874  *	Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
875  *	efx_mac_work() with kernel interfaces. Safe to read under any
876  *	one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
877  *	be held to modify it.
878  * @port_initialized: Port initialized?
879  * @net_dev: Operating system network device. Consider holding the rtnl lock
880  * @stats_buffer: DMA buffer for statistics
881  * @phy_type: PHY type
882  * @phy_op: PHY interface
883  * @phy_data: PHY private data (including PHY-specific stats)
884  * @mdio: PHY MDIO interface
885  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
886  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
887  * @link_advertising: Autonegotiation advertising flags
888  * @link_state: Current state of the link
889  * @n_link_state_changes: Number of times the link has changed state
890  * @unicast_filter: Flag for Falcon-arch simple unicast filter.
891  *	Protected by @mac_lock.
892  * @multicast_hash: Multicast hash table for Falcon-arch.
893  *	Protected by @mac_lock.
894  * @wanted_fc: Wanted flow control flags
895  * @fc_disable: When non-zero flow control is disabled. Typically used to
896  *	ensure that network back pressure doesn't delay dma queue flushes.
897  *	Serialised by the rtnl lock.
898  * @mac_work: Work item for changing MAC promiscuity and multicast hash
899  * @loopback_mode: Loopback status
900  * @loopback_modes: Supported loopback mode bitmask
901  * @loopback_selftest: Offline self-test private state
902  * @filter_lock: Filter table lock
903  * @filter_state: Architecture-dependent filter table state
904  * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
905  *	indexed by filter ID
906  * @rps_expire_index: Next index to check for expiry in @rps_flow_id
907  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
908  * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
909  *	Decremented when the efx_flush_rx_queue() is called.
910  * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
911  *	completed (either success or failure). Not used when MCDI is used to
912  *	flush receive queues.
913  * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
914  * @vf: Array of &struct efx_vf objects.
915  * @vf_count: Number of VFs intended to be enabled.
916  * @vf_init_count: Number of VFs that have been fully initialised.
917  * @vi_scale: log2 number of vnics per VF.
918  * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
919  * @vfdi_status: Common VFDI status page to be dmad to VF address space.
920  * @local_addr_list: List of local addresses. Protected by %local_lock.
921  * @local_page_list: List of DMA addressable pages used to broadcast
922  *	%local_addr_list. Protected by %local_lock.
923  * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
924  * @peer_work: Work item to broadcast peer addresses to VMs.
925  * @ptp_data: PTP state data
926  * @vpd_sn: Serial number read from VPD
927  * @monitor_work: Hardware monitor workitem
928  * @biu_lock: BIU (bus interface unit) lock
929  * @last_irq_cpu: Last CPU to handle a possible test interrupt.  This
930  *	field is used by efx_test_interrupts() to verify that an
931  *	interrupt has occurred.
932  * @stats_lock: Statistics update lock. Must be held when calling
933  *	efx_nic_type::{update,start,stop}_stats.
934  * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
935  *
936  * This is stored in the private area of the &struct net_device.
937  */
938 struct efx_nic {
939 	/* The following fields should be written very rarely */
940 
941 	char name[IFNAMSIZ];
942 	struct list_head node;
943 	struct efx_nic *primary;
944 	struct list_head secondary_list;
945 	struct pci_dev *pci_dev;
946 	unsigned int port_num;
947 	const struct efx_nic_type *type;
948 	int legacy_irq;
949 	bool eeh_disabled_legacy_irq;
950 	struct workqueue_struct *workqueue;
951 	char workqueue_name[16];
952 	struct work_struct reset_work;
953 	resource_size_t membase_phys;
954 	void __iomem *membase;
955 
956 	enum efx_int_mode interrupt_mode;
957 	unsigned int timer_quantum_ns;
958 	bool irq_rx_adaptive;
959 	unsigned int irq_rx_moderation;
960 	u32 msg_enable;
961 
962 	enum nic_state state;
963 	unsigned long reset_pending;
964 
965 	struct efx_channel *channel[EFX_MAX_CHANNELS];
966 	struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
967 	const struct efx_channel_type *
968 	extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
969 
970 	unsigned rxq_entries;
971 	unsigned txq_entries;
972 	unsigned int txq_stop_thresh;
973 	unsigned int txq_wake_thresh;
974 
975 	unsigned tx_dc_base;
976 	unsigned rx_dc_base;
977 	unsigned sram_lim_qw;
978 	unsigned next_buffer_table;
979 
980 	unsigned int max_channels;
981 	unsigned n_channels;
982 	unsigned n_rx_channels;
983 	unsigned rss_spread;
984 	unsigned tx_channel_offset;
985 	unsigned n_tx_channels;
986 	unsigned int rx_ip_align;
987 	unsigned int rx_dma_len;
988 	unsigned int rx_buffer_order;
989 	unsigned int rx_buffer_truesize;
990 	unsigned int rx_page_buf_step;
991 	unsigned int rx_bufs_per_page;
992 	unsigned int rx_pages_per_batch;
993 	unsigned int rx_prefix_size;
994 	int rx_packet_hash_offset;
995 	int rx_packet_len_offset;
996 	int rx_packet_ts_offset;
997 	u8 rx_hash_key[40];
998 	u32 rx_indir_table[128];
999 	bool rx_scatter;
1000 
1001 	unsigned int_error_count;
1002 	unsigned long int_error_expire;
1003 
1004 	bool irq_soft_enabled;
1005 	struct efx_buffer irq_status;
1006 	unsigned irq_zero_count;
1007 	unsigned irq_level;
1008 	struct delayed_work selftest_work;
1009 
1010 #ifdef CONFIG_SFC_MTD
1011 	struct list_head mtd_list;
1012 #endif
1013 
1014 	void *nic_data;
1015 	struct efx_mcdi_data *mcdi;
1016 
1017 	struct mutex mac_lock;
1018 	struct work_struct mac_work;
1019 	bool port_enabled;
1020 
1021 	bool mc_bist_for_other_fn;
1022 	bool port_initialized;
1023 	struct net_device *net_dev;
1024 
1025 	struct efx_buffer stats_buffer;
1026 	u64 rx_nodesc_drops_total;
1027 	u64 rx_nodesc_drops_while_down;
1028 	bool rx_nodesc_drops_prev_state;
1029 
1030 	unsigned int phy_type;
1031 	const struct efx_phy_operations *phy_op;
1032 	void *phy_data;
1033 	struct mdio_if_info mdio;
1034 	unsigned int mdio_bus;
1035 	enum efx_phy_mode phy_mode;
1036 
1037 	u32 link_advertising;
1038 	struct efx_link_state link_state;
1039 	unsigned int n_link_state_changes;
1040 
1041 	bool unicast_filter;
1042 	union efx_multicast_hash multicast_hash;
1043 	u8 wanted_fc;
1044 	unsigned fc_disable;
1045 
1046 	atomic_t rx_reset;
1047 	enum efx_loopback_mode loopback_mode;
1048 	u64 loopback_modes;
1049 
1050 	void *loopback_selftest;
1051 
1052 	spinlock_t filter_lock;
1053 	void *filter_state;
1054 #ifdef CONFIG_RFS_ACCEL
1055 	u32 *rps_flow_id;
1056 	unsigned int rps_expire_index;
1057 #endif
1058 
1059 	atomic_t active_queues;
1060 	atomic_t rxq_flush_pending;
1061 	atomic_t rxq_flush_outstanding;
1062 	wait_queue_head_t flush_wq;
1063 
1064 #ifdef CONFIG_SFC_SRIOV
1065 	struct efx_channel *vfdi_channel;
1066 	struct efx_vf *vf;
1067 	unsigned vf_count;
1068 	unsigned vf_init_count;
1069 	unsigned vi_scale;
1070 	unsigned vf_buftbl_base;
1071 	struct efx_buffer vfdi_status;
1072 	struct list_head local_addr_list;
1073 	struct list_head local_page_list;
1074 	struct mutex local_lock;
1075 	struct work_struct peer_work;
1076 #endif
1077 
1078 	struct efx_ptp_data *ptp_data;
1079 
1080 	char *vpd_sn;
1081 
1082 	/* The following fields may be written more often */
1083 
1084 	struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1085 	spinlock_t biu_lock;
1086 	int last_irq_cpu;
1087 	spinlock_t stats_lock;
1088 	atomic_t n_rx_noskb_drops;
1089 };
1090 
efx_dev_registered(struct efx_nic * efx)1091 static inline int efx_dev_registered(struct efx_nic *efx)
1092 {
1093 	return efx->net_dev->reg_state == NETREG_REGISTERED;
1094 }
1095 
efx_port_num(struct efx_nic * efx)1096 static inline unsigned int efx_port_num(struct efx_nic *efx)
1097 {
1098 	return efx->port_num;
1099 }
1100 
1101 struct efx_mtd_partition {
1102 	struct list_head node;
1103 	struct mtd_info mtd;
1104 	const char *dev_type_name;
1105 	const char *type_name;
1106 	char name[IFNAMSIZ + 20];
1107 };
1108 
1109 /**
1110  * struct efx_nic_type - Efx device type definition
1111  * @mem_map_size: Get memory BAR mapped size
1112  * @probe: Probe the controller
1113  * @remove: Free resources allocated by probe()
1114  * @init: Initialise the controller
1115  * @dimension_resources: Dimension controller resources (buffer table,
1116  *	and VIs once the available interrupt resources are clear)
1117  * @fini: Shut down the controller
1118  * @monitor: Periodic function for polling link state and hardware monitor
1119  * @map_reset_reason: Map ethtool reset reason to a reset method
1120  * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1121  * @reset: Reset the controller hardware and possibly the PHY.  This will
1122  *	be called while the controller is uninitialised.
1123  * @probe_port: Probe the MAC and PHY
1124  * @remove_port: Free resources allocated by probe_port()
1125  * @handle_global_event: Handle a "global" event (may be %NULL)
1126  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1127  * @prepare_flush: Prepare the hardware for flushing the DMA queues
1128  *	(for Falcon architecture)
1129  * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1130  *	architecture)
1131  * @prepare_flr: Prepare for an FLR
1132  * @finish_flr: Clean up after an FLR
1133  * @describe_stats: Describe statistics for ethtool
1134  * @update_stats: Update statistics not provided by event handling.
1135  *	Either argument may be %NULL.
1136  * @start_stats: Start the regular fetching of statistics
1137  * @pull_stats: Pull stats from the NIC and wait until they arrive.
1138  * @stop_stats: Stop the regular fetching of statistics
1139  * @set_id_led: Set state of identifying LED or revert to automatic function
1140  * @push_irq_moderation: Apply interrupt moderation value
1141  * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1142  * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1143  * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1144  *	to the hardware.  Serialised by the mac_lock.
1145  * @check_mac_fault: Check MAC fault state. True if fault present.
1146  * @get_wol: Get WoL configuration from driver state
1147  * @set_wol: Push WoL configuration to the NIC
1148  * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1149  * @test_chip: Test registers.  May use efx_farch_test_registers(), and is
1150  *	expected to reset the NIC.
1151  * @test_nvram: Test validity of NVRAM contents
1152  * @mcdi_request: Send an MCDI request with the given header and SDU.
1153  *	The SDU length may be any value from 0 up to the protocol-
1154  *	defined maximum, but its buffer will be padded to a multiple
1155  *	of 4 bytes.
1156  * @mcdi_poll_response: Test whether an MCDI response is available.
1157  * @mcdi_read_response: Read the MCDI response PDU.  The offset will
1158  *	be a multiple of 4.  The length may not be, but the buffer
1159  *	will be padded so it is safe to round up.
1160  * @mcdi_poll_reboot: Test whether the MCDI has rebooted.  If so,
1161  *	return an appropriate error code for aborting any current
1162  *	request; otherwise return 0.
1163  * @irq_enable_master: Enable IRQs on the NIC.  Each event queue must
1164  *	be separately enabled after this.
1165  * @irq_test_generate: Generate a test IRQ
1166  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1167  *	queue must be separately disabled before this.
1168  * @irq_handle_msi: Handle MSI for a channel.  The @dev_id argument is
1169  *	a pointer to the &struct efx_msi_context for the channel.
1170  * @irq_handle_legacy: Handle legacy interrupt.  The @dev_id argument
1171  *	is a pointer to the &struct efx_nic.
1172  * @tx_probe: Allocate resources for TX queue
1173  * @tx_init: Initialise TX queue on the NIC
1174  * @tx_remove: Free resources for TX queue
1175  * @tx_write: Write TX descriptors and doorbell
1176  * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1177  * @rx_probe: Allocate resources for RX queue
1178  * @rx_init: Initialise RX queue on the NIC
1179  * @rx_remove: Free resources for RX queue
1180  * @rx_write: Write RX descriptors and doorbell
1181  * @rx_defer_refill: Generate a refill reminder event
1182  * @ev_probe: Allocate resources for event queue
1183  * @ev_init: Initialise event queue on the NIC
1184  * @ev_fini: Deinitialise event queue on the NIC
1185  * @ev_remove: Free resources for event queue
1186  * @ev_process: Process events for a queue, up to the given NAPI quota
1187  * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1188  * @ev_test_generate: Generate a test event
1189  * @filter_table_probe: Probe filter capabilities and set up filter software state
1190  * @filter_table_restore: Restore filters removed from hardware
1191  * @filter_table_remove: Remove filters from hardware and tear down software state
1192  * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1193  * @filter_insert: add or replace a filter
1194  * @filter_remove_safe: remove a filter by ID, carefully
1195  * @filter_get_safe: retrieve a filter by ID, carefully
1196  * @filter_clear_rx: Remove all RX filters whose priority is less than or
1197  *	equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1198  * @filter_count_rx_used: Get the number of filters in use at a given priority
1199  * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1200  * @filter_get_rx_ids: Get list of RX filters at a given priority
1201  * @filter_rfs_insert: Add or replace a filter for RFS.  This must be
1202  *	atomic.  The hardware change may be asynchronous but should
1203  *	not be delayed for long.  It may fail if this can't be done
1204  *	atomically.
1205  * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1206  *	This must check whether the specified table entry is used by RFS
1207  *	and that rps_may_expire_flow() returns true for it.
1208  * @mtd_probe: Probe and add MTD partitions associated with this net device,
1209  *	 using efx_mtd_add()
1210  * @mtd_rename: Set an MTD partition name using the net device name
1211  * @mtd_read: Read from an MTD partition
1212  * @mtd_erase: Erase part of an MTD partition
1213  * @mtd_write: Write to an MTD partition
1214  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1215  *	also notifies the driver that a writer has finished using this
1216  *	partition.
1217  * @ptp_write_host_time: Send host time to MC as part of sync protocol
1218  * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1219  *	timestamping, possibly only temporarily for the purposes of a reset.
1220  * @ptp_set_ts_config: Set hardware timestamp configuration.  The flags
1221  *	and tx_type will already have been validated but this operation
1222  *	must validate and update rx_filter.
1223  * @revision: Hardware architecture revision
1224  * @txd_ptr_tbl_base: TX descriptor ring base address
1225  * @rxd_ptr_tbl_base: RX descriptor ring base address
1226  * @buf_tbl_base: Buffer table base address
1227  * @evq_ptr_tbl_base: Event queue pointer table base address
1228  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1229  * @max_dma_mask: Maximum possible DMA mask
1230  * @rx_prefix_size: Size of RX prefix before packet data
1231  * @rx_hash_offset: Offset of RX flow hash within prefix
1232  * @rx_ts_offset: Offset of timestamp within prefix
1233  * @rx_buffer_padding: Size of padding at end of RX packet
1234  * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1235  * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1236  * @max_interrupt_mode: Highest capability interrupt mode supported
1237  *	from &enum efx_init_mode.
1238  * @timer_period_max: Maximum period of interrupt timer (in ticks)
1239  * @offload_features: net_device feature flags for protocol offload
1240  *	features implemented in hardware
1241  * @mcdi_max_ver: Maximum MCDI version supported
1242  * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1243  */
1244 struct efx_nic_type {
1245 	unsigned int (*mem_map_size)(struct efx_nic *efx);
1246 	int (*probe)(struct efx_nic *efx);
1247 	void (*remove)(struct efx_nic *efx);
1248 	int (*init)(struct efx_nic *efx);
1249 	int (*dimension_resources)(struct efx_nic *efx);
1250 	void (*fini)(struct efx_nic *efx);
1251 	void (*monitor)(struct efx_nic *efx);
1252 	enum reset_type (*map_reset_reason)(enum reset_type reason);
1253 	int (*map_reset_flags)(u32 *flags);
1254 	int (*reset)(struct efx_nic *efx, enum reset_type method);
1255 	int (*probe_port)(struct efx_nic *efx);
1256 	void (*remove_port)(struct efx_nic *efx);
1257 	bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1258 	int (*fini_dmaq)(struct efx_nic *efx);
1259 	void (*prepare_flush)(struct efx_nic *efx);
1260 	void (*finish_flush)(struct efx_nic *efx);
1261 	void (*prepare_flr)(struct efx_nic *efx);
1262 	void (*finish_flr)(struct efx_nic *efx);
1263 	size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1264 	size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1265 			       struct rtnl_link_stats64 *core_stats);
1266 	void (*start_stats)(struct efx_nic *efx);
1267 	void (*pull_stats)(struct efx_nic *efx);
1268 	void (*stop_stats)(struct efx_nic *efx);
1269 	void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1270 	void (*push_irq_moderation)(struct efx_channel *channel);
1271 	int (*reconfigure_port)(struct efx_nic *efx);
1272 	void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1273 	int (*reconfigure_mac)(struct efx_nic *efx);
1274 	bool (*check_mac_fault)(struct efx_nic *efx);
1275 	void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1276 	int (*set_wol)(struct efx_nic *efx, u32 type);
1277 	void (*resume_wol)(struct efx_nic *efx);
1278 	int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1279 	int (*test_nvram)(struct efx_nic *efx);
1280 	void (*mcdi_request)(struct efx_nic *efx,
1281 			     const efx_dword_t *hdr, size_t hdr_len,
1282 			     const efx_dword_t *sdu, size_t sdu_len);
1283 	bool (*mcdi_poll_response)(struct efx_nic *efx);
1284 	void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1285 				   size_t pdu_offset, size_t pdu_len);
1286 	int (*mcdi_poll_reboot)(struct efx_nic *efx);
1287 	void (*irq_enable_master)(struct efx_nic *efx);
1288 	void (*irq_test_generate)(struct efx_nic *efx);
1289 	void (*irq_disable_non_ev)(struct efx_nic *efx);
1290 	irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1291 	irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1292 	int (*tx_probe)(struct efx_tx_queue *tx_queue);
1293 	void (*tx_init)(struct efx_tx_queue *tx_queue);
1294 	void (*tx_remove)(struct efx_tx_queue *tx_queue);
1295 	void (*tx_write)(struct efx_tx_queue *tx_queue);
1296 	void (*rx_push_rss_config)(struct efx_nic *efx);
1297 	int (*rx_probe)(struct efx_rx_queue *rx_queue);
1298 	void (*rx_init)(struct efx_rx_queue *rx_queue);
1299 	void (*rx_remove)(struct efx_rx_queue *rx_queue);
1300 	void (*rx_write)(struct efx_rx_queue *rx_queue);
1301 	void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1302 	int (*ev_probe)(struct efx_channel *channel);
1303 	int (*ev_init)(struct efx_channel *channel);
1304 	void (*ev_fini)(struct efx_channel *channel);
1305 	void (*ev_remove)(struct efx_channel *channel);
1306 	int (*ev_process)(struct efx_channel *channel, int quota);
1307 	void (*ev_read_ack)(struct efx_channel *channel);
1308 	void (*ev_test_generate)(struct efx_channel *channel);
1309 	int (*filter_table_probe)(struct efx_nic *efx);
1310 	void (*filter_table_restore)(struct efx_nic *efx);
1311 	void (*filter_table_remove)(struct efx_nic *efx);
1312 	void (*filter_update_rx_scatter)(struct efx_nic *efx);
1313 	s32 (*filter_insert)(struct efx_nic *efx,
1314 			     struct efx_filter_spec *spec, bool replace);
1315 	int (*filter_remove_safe)(struct efx_nic *efx,
1316 				  enum efx_filter_priority priority,
1317 				  u32 filter_id);
1318 	int (*filter_get_safe)(struct efx_nic *efx,
1319 			       enum efx_filter_priority priority,
1320 			       u32 filter_id, struct efx_filter_spec *);
1321 	int (*filter_clear_rx)(struct efx_nic *efx,
1322 			       enum efx_filter_priority priority);
1323 	u32 (*filter_count_rx_used)(struct efx_nic *efx,
1324 				    enum efx_filter_priority priority);
1325 	u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1326 	s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1327 				 enum efx_filter_priority priority,
1328 				 u32 *buf, u32 size);
1329 #ifdef CONFIG_RFS_ACCEL
1330 	s32 (*filter_rfs_insert)(struct efx_nic *efx,
1331 				 struct efx_filter_spec *spec);
1332 	bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1333 				      unsigned int index);
1334 #endif
1335 #ifdef CONFIG_SFC_MTD
1336 	int (*mtd_probe)(struct efx_nic *efx);
1337 	void (*mtd_rename)(struct efx_mtd_partition *part);
1338 	int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1339 			size_t *retlen, u8 *buffer);
1340 	int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1341 	int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1342 			 size_t *retlen, const u8 *buffer);
1343 	int (*mtd_sync)(struct mtd_info *mtd);
1344 #endif
1345 	void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1346 	int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1347 	int (*ptp_set_ts_config)(struct efx_nic *efx,
1348 				 struct hwtstamp_config *init);
1349 
1350 	int revision;
1351 	unsigned int txd_ptr_tbl_base;
1352 	unsigned int rxd_ptr_tbl_base;
1353 	unsigned int buf_tbl_base;
1354 	unsigned int evq_ptr_tbl_base;
1355 	unsigned int evq_rptr_tbl_base;
1356 	u64 max_dma_mask;
1357 	unsigned int rx_prefix_size;
1358 	unsigned int rx_hash_offset;
1359 	unsigned int rx_ts_offset;
1360 	unsigned int rx_buffer_padding;
1361 	bool can_rx_scatter;
1362 	bool always_rx_scatter;
1363 	unsigned int max_interrupt_mode;
1364 	unsigned int timer_period_max;
1365 	netdev_features_t offload_features;
1366 	int mcdi_max_ver;
1367 	unsigned int max_rx_ip_filters;
1368 	u32 hwtstamp_filters;
1369 };
1370 
1371 /**************************************************************************
1372  *
1373  * Prototypes and inline functions
1374  *
1375  *************************************************************************/
1376 
1377 static inline struct efx_channel *
efx_get_channel(struct efx_nic * efx,unsigned index)1378 efx_get_channel(struct efx_nic *efx, unsigned index)
1379 {
1380 	EFX_BUG_ON_PARANOID(index >= efx->n_channels);
1381 	return efx->channel[index];
1382 }
1383 
1384 /* Iterate over all used channels */
1385 #define efx_for_each_channel(_channel, _efx)				\
1386 	for (_channel = (_efx)->channel[0];				\
1387 	     _channel;							\
1388 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1389 		     (_efx)->channel[_channel->channel + 1] : NULL)
1390 
1391 /* Iterate over all used channels in reverse */
1392 #define efx_for_each_channel_rev(_channel, _efx)			\
1393 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1394 	     _channel;							\
1395 	     _channel = _channel->channel ?				\
1396 		     (_efx)->channel[_channel->channel - 1] : NULL)
1397 
1398 static inline struct efx_tx_queue *
efx_get_tx_queue(struct efx_nic * efx,unsigned index,unsigned type)1399 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1400 {
1401 	EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
1402 			    type >= EFX_TXQ_TYPES);
1403 	return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1404 }
1405 
efx_channel_has_tx_queues(struct efx_channel * channel)1406 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1407 {
1408 	return channel->channel - channel->efx->tx_channel_offset <
1409 		channel->efx->n_tx_channels;
1410 }
1411 
1412 static inline struct efx_tx_queue *
efx_channel_get_tx_queue(struct efx_channel * channel,unsigned type)1413 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1414 {
1415 	EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
1416 			    type >= EFX_TXQ_TYPES);
1417 	return &channel->tx_queue[type];
1418 }
1419 
efx_tx_queue_used(struct efx_tx_queue * tx_queue)1420 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1421 {
1422 	return !(tx_queue->efx->net_dev->num_tc < 2 &&
1423 		 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1424 }
1425 
1426 /* Iterate over all TX queues belonging to a channel */
1427 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)		\
1428 	if (!efx_channel_has_tx_queues(_channel))			\
1429 		;							\
1430 	else								\
1431 		for (_tx_queue = (_channel)->tx_queue;			\
1432 		     _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1433 			     efx_tx_queue_used(_tx_queue);		\
1434 		     _tx_queue++)
1435 
1436 /* Iterate over all possible TX queues belonging to a channel */
1437 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel)	\
1438 	if (!efx_channel_has_tx_queues(_channel))			\
1439 		;							\
1440 	else								\
1441 		for (_tx_queue = (_channel)->tx_queue;			\
1442 		     _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES;	\
1443 		     _tx_queue++)
1444 
efx_channel_has_rx_queue(struct efx_channel * channel)1445 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1446 {
1447 	return channel->rx_queue.core_index >= 0;
1448 }
1449 
1450 static inline struct efx_rx_queue *
efx_channel_get_rx_queue(struct efx_channel * channel)1451 efx_channel_get_rx_queue(struct efx_channel *channel)
1452 {
1453 	EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
1454 	return &channel->rx_queue;
1455 }
1456 
1457 /* Iterate over all RX queues belonging to a channel */
1458 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)		\
1459 	if (!efx_channel_has_rx_queue(_channel))			\
1460 		;							\
1461 	else								\
1462 		for (_rx_queue = &(_channel)->rx_queue;			\
1463 		     _rx_queue;						\
1464 		     _rx_queue = NULL)
1465 
1466 static inline struct efx_channel *
efx_rx_queue_channel(struct efx_rx_queue * rx_queue)1467 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1468 {
1469 	return container_of(rx_queue, struct efx_channel, rx_queue);
1470 }
1471 
efx_rx_queue_index(struct efx_rx_queue * rx_queue)1472 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1473 {
1474 	return efx_rx_queue_channel(rx_queue)->channel;
1475 }
1476 
1477 /* Returns a pointer to the specified receive buffer in the RX
1478  * descriptor queue.
1479  */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)1480 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1481 						  unsigned int index)
1482 {
1483 	return &rx_queue->buffer[index];
1484 }
1485 
1486 /**
1487  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1488  *
1489  * This calculates the maximum frame length that will be used for a
1490  * given MTU.  The frame length will be equal to the MTU plus a
1491  * constant amount of header space and padding.  This is the quantity
1492  * that the net driver will program into the MAC as the maximum frame
1493  * length.
1494  *
1495  * The 10G MAC requires 8-byte alignment on the frame
1496  * length, so we round up to the nearest 8.
1497  *
1498  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1499  * XGMII cycle).  If the frame length reaches the maximum value in the
1500  * same cycle, the XMAC can miss the IPG altogether.  We work around
1501  * this by adding a further 16 bytes.
1502  */
1503 #define EFX_MAX_FRAME_LEN(mtu) \
1504 	((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1505 
efx_xmit_with_hwtstamp(struct sk_buff * skb)1506 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1507 {
1508 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1509 }
efx_xmit_hwtstamp_pending(struct sk_buff * skb)1510 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1511 {
1512 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1513 }
1514 
1515 #endif /* EFX_NET_DRIVER_H */
1516