1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
5 *
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 *
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
33
34 #include "iwl-debug.h"
35 #include "iwl-csr.h"
36 #include "iwl-prph.h"
37 #include "iwl-io.h"
38 #include "iwl-scd.h"
39 #include "iwl-op-mode.h"
40 #include "internal.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
43
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
46
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
48 * DMA services
49 *
50 * Theory of operation
51 *
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
57 * queue states.
58 *
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
61 *
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
65 * Tx queue resumed.
66 *
67 ***************************************************/
iwl_queue_space(const struct iwl_queue * q)68 static int iwl_queue_space(const struct iwl_queue *q)
69 {
70 unsigned int max;
71 unsigned int used;
72
73 /*
74 * To avoid ambiguity between empty and completely full queues, there
75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
78 */
79 if (q->n_window < TFD_QUEUE_SIZE_MAX)
80 max = q->n_window;
81 else
82 max = TFD_QUEUE_SIZE_MAX - 1;
83
84 /*
85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
87 */
88 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
89
90 if (WARN_ON(used > max))
91 return 0;
92
93 return max - used;
94 }
95
96 /*
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
98 */
iwl_queue_init(struct iwl_queue * q,int slots_num,u32 id)99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
100 {
101 q->n_window = slots_num;
102 q->id = id;
103
104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num)))
107 return -EINVAL;
108
109 q->low_mark = q->n_window / 4;
110 if (q->low_mark < 4)
111 q->low_mark = 4;
112
113 q->high_mark = q->n_window / 8;
114 if (q->high_mark < 2)
115 q->high_mark = 2;
116
117 q->write_ptr = 0;
118 q->read_ptr = 0;
119
120 return 0;
121 }
122
iwl_pcie_alloc_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr,size_t size)123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
124 struct iwl_dma_ptr *ptr, size_t size)
125 {
126 if (WARN_ON(ptr->addr))
127 return -EINVAL;
128
129 ptr->addr = dma_alloc_coherent(trans->dev, size,
130 &ptr->dma, GFP_KERNEL);
131 if (!ptr->addr)
132 return -ENOMEM;
133 ptr->size = size;
134 return 0;
135 }
136
iwl_pcie_free_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr)137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
138 struct iwl_dma_ptr *ptr)
139 {
140 if (unlikely(!ptr->addr))
141 return;
142
143 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
144 memset(ptr, 0, sizeof(*ptr));
145 }
146
iwl_pcie_txq_stuck_timer(unsigned long data)147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
148 {
149 struct iwl_txq *txq = (void *)data;
150 struct iwl_queue *q = &txq->q;
151 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
152 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
153 u32 scd_sram_addr = trans_pcie->scd_base_addr +
154 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
155 u8 buf[16];
156 int i;
157
158 spin_lock(&txq->lock);
159 /* check if triggered erroneously */
160 if (txq->q.read_ptr == txq->q.write_ptr) {
161 spin_unlock(&txq->lock);
162 return;
163 }
164 spin_unlock(&txq->lock);
165
166 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
167 jiffies_to_msecs(trans_pcie->wd_timeout));
168 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
169 txq->q.read_ptr, txq->q.write_ptr);
170
171 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
172
173 iwl_print_hex_error(trans, buf, sizeof(buf));
174
175 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
176 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
177 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
178
179 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
180 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
181 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
182 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
183 u32 tbl_dw =
184 iwl_trans_read_mem32(trans,
185 trans_pcie->scd_base_addr +
186 SCD_TRANS_TBL_OFFSET_QUEUE(i));
187
188 if (i & 0x1)
189 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
190 else
191 tbl_dw = tbl_dw & 0x0000FFFF;
192
193 IWL_ERR(trans,
194 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
195 i, active ? "" : "in", fifo, tbl_dw,
196 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
197 (TFD_QUEUE_SIZE_MAX - 1),
198 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
199 }
200
201 for (i = q->read_ptr; i != q->write_ptr;
202 i = iwl_queue_inc_wrap(i))
203 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
204 le32_to_cpu(txq->scratchbufs[i].scratch));
205
206 iwl_force_nmi(trans);
207 }
208
209 /*
210 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
211 */
iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_txq * txq,u16 byte_cnt)212 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
213 struct iwl_txq *txq, u16 byte_cnt)
214 {
215 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
217 int write_ptr = txq->q.write_ptr;
218 int txq_id = txq->q.id;
219 u8 sec_ctl = 0;
220 u8 sta_id = 0;
221 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
222 __le16 bc_ent;
223 struct iwl_tx_cmd *tx_cmd =
224 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
225
226 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
227
228 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
229
230 sta_id = tx_cmd->sta_id;
231 sec_ctl = tx_cmd->sec_ctl;
232
233 switch (sec_ctl & TX_CMD_SEC_MSK) {
234 case TX_CMD_SEC_CCM:
235 len += IEEE80211_CCMP_MIC_LEN;
236 break;
237 case TX_CMD_SEC_TKIP:
238 len += IEEE80211_TKIP_ICV_LEN;
239 break;
240 case TX_CMD_SEC_WEP:
241 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
242 break;
243 }
244
245 if (trans_pcie->bc_table_dword)
246 len = DIV_ROUND_UP(len, 4);
247
248 bc_ent = cpu_to_le16(len | (sta_id << 12));
249
250 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
251
252 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
253 scd_bc_tbl[txq_id].
254 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
255 }
256
iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_txq * txq)257 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
258 struct iwl_txq *txq)
259 {
260 struct iwl_trans_pcie *trans_pcie =
261 IWL_TRANS_GET_PCIE_TRANS(trans);
262 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
263 int txq_id = txq->q.id;
264 int read_ptr = txq->q.read_ptr;
265 u8 sta_id = 0;
266 __le16 bc_ent;
267 struct iwl_tx_cmd *tx_cmd =
268 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
269
270 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
271
272 if (txq_id != trans_pcie->cmd_queue)
273 sta_id = tx_cmd->sta_id;
274
275 bc_ent = cpu_to_le16(1 | (sta_id << 12));
276 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
277
278 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
279 scd_bc_tbl[txq_id].
280 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
281 }
282
283 /*
284 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
285 */
iwl_pcie_txq_inc_wr_ptr(struct iwl_trans * trans,struct iwl_txq * txq)286 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
287 struct iwl_txq *txq)
288 {
289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
290 u32 reg = 0;
291 int txq_id = txq->q.id;
292
293 lockdep_assert_held(&txq->lock);
294
295 /*
296 * explicitly wake up the NIC if:
297 * 1. shadow registers aren't enabled
298 * 2. NIC is woken up for CMD regardless of shadow outside this function
299 * 3. there is a chance that the NIC is asleep
300 */
301 if (!trans->cfg->base_params->shadow_reg_enable &&
302 txq_id != trans_pcie->cmd_queue &&
303 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
304 /*
305 * wake up nic if it's powered down ...
306 * uCode will wake up, and interrupt us again, so next
307 * time we'll skip this part.
308 */
309 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
310
311 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
312 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
313 txq_id, reg);
314 iwl_set_bit(trans, CSR_GP_CNTRL,
315 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
316 txq->need_update = true;
317 return;
318 }
319 }
320
321 /*
322 * if not in power-save mode, uCode will never sleep when we're
323 * trying to tx (during RFKILL, we're not trying to tx).
324 */
325 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
326 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
327 }
328
iwl_pcie_txq_check_wrptrs(struct iwl_trans * trans)329 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
330 {
331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
332 int i;
333
334 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
335 struct iwl_txq *txq = &trans_pcie->txq[i];
336
337 spin_lock_bh(&txq->lock);
338 if (trans_pcie->txq[i].need_update) {
339 iwl_pcie_txq_inc_wr_ptr(trans, txq);
340 trans_pcie->txq[i].need_update = false;
341 }
342 spin_unlock_bh(&txq->lock);
343 }
344 }
345
iwl_pcie_tfd_tb_get_addr(struct iwl_tfd * tfd,u8 idx)346 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
347 {
348 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
349
350 dma_addr_t addr = get_unaligned_le32(&tb->lo);
351 if (sizeof(dma_addr_t) > sizeof(u32))
352 addr |=
353 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
354
355 return addr;
356 }
357
iwl_pcie_tfd_set_tb(struct iwl_tfd * tfd,u8 idx,dma_addr_t addr,u16 len)358 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
359 dma_addr_t addr, u16 len)
360 {
361 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
362 u16 hi_n_len = len << 4;
363
364 put_unaligned_le32(addr, &tb->lo);
365 if (sizeof(dma_addr_t) > sizeof(u32))
366 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
367
368 tb->hi_n_len = cpu_to_le16(hi_n_len);
369
370 tfd->num_tbs = idx + 1;
371 }
372
iwl_pcie_tfd_get_num_tbs(struct iwl_tfd * tfd)373 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
374 {
375 return tfd->num_tbs & 0x1f;
376 }
377
iwl_pcie_tfd_unmap(struct iwl_trans * trans,struct iwl_cmd_meta * meta,struct iwl_tfd * tfd)378 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
379 struct iwl_cmd_meta *meta,
380 struct iwl_tfd *tfd)
381 {
382 int i;
383 int num_tbs;
384
385 /* Sanity check on number of chunks */
386 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
387
388 if (num_tbs >= IWL_NUM_OF_TBS) {
389 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
390 /* @todo issue fatal error, it is quite serious situation */
391 return;
392 }
393
394 /* first TB is never freed - it's the scratchbuf data */
395
396 for (i = 1; i < num_tbs; i++)
397 dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i),
398 iwl_pcie_tfd_tb_get_len(tfd, i),
399 DMA_TO_DEVICE);
400
401 tfd->num_tbs = 0;
402 }
403
404 /*
405 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
406 * @trans - transport private data
407 * @txq - tx queue
408 * @dma_dir - the direction of the DMA mapping
409 *
410 * Does NOT advance any TFD circular buffer read/write indexes
411 * Does NOT free the TFD itself (which is within circular buffer)
412 */
iwl_pcie_txq_free_tfd(struct iwl_trans * trans,struct iwl_txq * txq)413 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
414 {
415 struct iwl_tfd *tfd_tmp = txq->tfds;
416
417 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
418 * idx is bounded by n_window
419 */
420 int rd_ptr = txq->q.read_ptr;
421 int idx = get_cmd_index(&txq->q, rd_ptr);
422
423 lockdep_assert_held(&txq->lock);
424
425 /* We have only q->n_window txq->entries, but we use
426 * TFD_QUEUE_SIZE_MAX tfds
427 */
428 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
429
430 /* free SKB */
431 if (txq->entries) {
432 struct sk_buff *skb;
433
434 skb = txq->entries[idx].skb;
435
436 /* Can be called from irqs-disabled context
437 * If skb is not NULL, it means that the whole queue is being
438 * freed and that the queue is not empty - free the skb
439 */
440 if (skb) {
441 iwl_op_mode_free_skb(trans->op_mode, skb);
442 txq->entries[idx].skb = NULL;
443 }
444 }
445 }
446
iwl_pcie_txq_build_tfd(struct iwl_trans * trans,struct iwl_txq * txq,dma_addr_t addr,u16 len,bool reset)447 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
448 dma_addr_t addr, u16 len, bool reset)
449 {
450 struct iwl_queue *q;
451 struct iwl_tfd *tfd, *tfd_tmp;
452 u32 num_tbs;
453
454 q = &txq->q;
455 tfd_tmp = txq->tfds;
456 tfd = &tfd_tmp[q->write_ptr];
457
458 if (reset)
459 memset(tfd, 0, sizeof(*tfd));
460
461 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
462
463 /* Each TFD can point to a maximum 20 Tx buffers */
464 if (num_tbs >= IWL_NUM_OF_TBS) {
465 IWL_ERR(trans, "Error can not send more than %d chunks\n",
466 IWL_NUM_OF_TBS);
467 return -EINVAL;
468 }
469
470 if (WARN(addr & ~IWL_TX_DMA_MASK,
471 "Unaligned address = %llx\n", (unsigned long long)addr))
472 return -EINVAL;
473
474 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
475
476 return 0;
477 }
478
iwl_pcie_txq_alloc(struct iwl_trans * trans,struct iwl_txq * txq,int slots_num,u32 txq_id)479 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
480 struct iwl_txq *txq, int slots_num,
481 u32 txq_id)
482 {
483 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
484 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
485 size_t scratchbuf_sz;
486 int i;
487
488 if (WARN_ON(txq->entries || txq->tfds))
489 return -EINVAL;
490
491 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
492 (unsigned long)txq);
493 txq->trans_pcie = trans_pcie;
494
495 txq->q.n_window = slots_num;
496
497 txq->entries = kcalloc(slots_num,
498 sizeof(struct iwl_pcie_txq_entry),
499 GFP_KERNEL);
500
501 if (!txq->entries)
502 goto error;
503
504 if (txq_id == trans_pcie->cmd_queue)
505 for (i = 0; i < slots_num; i++) {
506 txq->entries[i].cmd =
507 kmalloc(sizeof(struct iwl_device_cmd),
508 GFP_KERNEL);
509 if (!txq->entries[i].cmd)
510 goto error;
511 }
512
513 /* Circular buffer of transmit frame descriptors (TFDs),
514 * shared with device */
515 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
516 &txq->q.dma_addr, GFP_KERNEL);
517 if (!txq->tfds)
518 goto error;
519
520 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
521 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
522 sizeof(struct iwl_cmd_header) +
523 offsetof(struct iwl_tx_cmd, scratch));
524
525 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
526
527 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
528 &txq->scratchbufs_dma,
529 GFP_KERNEL);
530 if (!txq->scratchbufs)
531 goto err_free_tfds;
532
533 txq->q.id = txq_id;
534
535 return 0;
536 err_free_tfds:
537 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
538 error:
539 if (txq->entries && txq_id == trans_pcie->cmd_queue)
540 for (i = 0; i < slots_num; i++)
541 kfree(txq->entries[i].cmd);
542 kfree(txq->entries);
543 txq->entries = NULL;
544
545 return -ENOMEM;
546
547 }
548
iwl_pcie_txq_init(struct iwl_trans * trans,struct iwl_txq * txq,int slots_num,u32 txq_id)549 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
550 int slots_num, u32 txq_id)
551 {
552 int ret;
553
554 txq->need_update = false;
555
556 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
557 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
558 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
559
560 /* Initialize queue's high/low-water marks, and head/tail indexes */
561 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
562 if (ret)
563 return ret;
564
565 spin_lock_init(&txq->lock);
566
567 /*
568 * Tell nic where to find circular buffer of Tx Frame Descriptors for
569 * given Tx queue, and enable the DMA channel used for that queue.
570 * Circular buffer (TFD queue in DRAM) physical base address */
571 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
572 txq->q.dma_addr >> 8);
573
574 return 0;
575 }
576
577 /*
578 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
579 */
iwl_pcie_txq_unmap(struct iwl_trans * trans,int txq_id)580 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
581 {
582 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
583 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
584 struct iwl_queue *q = &txq->q;
585
586 spin_lock_bh(&txq->lock);
587 while (q->write_ptr != q->read_ptr) {
588 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
589 txq_id, q->read_ptr);
590 iwl_pcie_txq_free_tfd(trans, txq);
591 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
592 }
593 txq->active = false;
594 spin_unlock_bh(&txq->lock);
595
596 /* just in case - this queue may have been stopped */
597 iwl_wake_queue(trans, txq);
598 }
599
600 /*
601 * iwl_pcie_txq_free - Deallocate DMA queue.
602 * @txq: Transmit queue to deallocate.
603 *
604 * Empty queue by removing and destroying all BD's.
605 * Free all buffers.
606 * 0-fill, but do not free "txq" descriptor structure.
607 */
iwl_pcie_txq_free(struct iwl_trans * trans,int txq_id)608 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
609 {
610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
611 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
612 struct device *dev = trans->dev;
613 int i;
614
615 if (WARN_ON(!txq))
616 return;
617
618 iwl_pcie_txq_unmap(trans, txq_id);
619
620 /* De-alloc array of command/tx buffers */
621 if (txq_id == trans_pcie->cmd_queue)
622 for (i = 0; i < txq->q.n_window; i++) {
623 kzfree(txq->entries[i].cmd);
624 kzfree(txq->entries[i].free_buf);
625 }
626
627 /* De-alloc circular buffer of TFDs */
628 if (txq->tfds) {
629 dma_free_coherent(dev,
630 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
631 txq->tfds, txq->q.dma_addr);
632 txq->q.dma_addr = 0;
633 txq->tfds = NULL;
634
635 dma_free_coherent(dev,
636 sizeof(*txq->scratchbufs) * txq->q.n_window,
637 txq->scratchbufs, txq->scratchbufs_dma);
638 }
639
640 kfree(txq->entries);
641 txq->entries = NULL;
642
643 del_timer_sync(&txq->stuck_timer);
644
645 /* 0-fill queue descriptor structure */
646 memset(txq, 0, sizeof(*txq));
647 }
648
iwl_pcie_tx_start(struct iwl_trans * trans,u32 scd_base_addr)649 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
650 {
651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
652 int nq = trans->cfg->base_params->num_of_queues;
653 int chan;
654 u32 reg_val;
655 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
656 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
657
658 /* make sure all queue are not stopped/used */
659 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
660 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
661
662 trans_pcie->scd_base_addr =
663 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
664
665 WARN_ON(scd_base_addr != 0 &&
666 scd_base_addr != trans_pcie->scd_base_addr);
667
668 /* reset context data, TX status and translation data */
669 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
670 SCD_CONTEXT_MEM_LOWER_BOUND,
671 NULL, clear_dwords);
672
673 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
674 trans_pcie->scd_bc_tbls.dma >> 10);
675
676 /* The chain extension of the SCD doesn't work well. This feature is
677 * enabled by default by the HW, so we need to disable it manually.
678 */
679 if (trans->cfg->base_params->scd_chain_ext_wa)
680 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
681
682 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
683 trans_pcie->cmd_fifo);
684
685 /* Activate all Tx DMA/FIFO channels */
686 iwl_scd_activate_fifos(trans);
687
688 /* Enable DMA channel */
689 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
690 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
692 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
693
694 /* Update FH chicken bits */
695 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
696 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
697 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
698
699 /* Enable L1-Active */
700 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
701 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
702 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
703 }
704
iwl_trans_pcie_tx_reset(struct iwl_trans * trans)705 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
706 {
707 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
708 int txq_id;
709
710 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
711 txq_id++) {
712 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
713
714 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
715 txq->q.dma_addr >> 8);
716 iwl_pcie_txq_unmap(trans, txq_id);
717 txq->q.read_ptr = 0;
718 txq->q.write_ptr = 0;
719 }
720
721 /* Tell NIC where to find the "keep warm" buffer */
722 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
723 trans_pcie->kw.dma >> 4);
724
725 /*
726 * Send 0 as the scd_base_addr since the device may have be reset
727 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
728 * contain garbage.
729 */
730 iwl_pcie_tx_start(trans, 0);
731 }
732
733 /*
734 * iwl_pcie_tx_stop - Stop all Tx DMA channels
735 */
iwl_pcie_tx_stop(struct iwl_trans * trans)736 int iwl_pcie_tx_stop(struct iwl_trans *trans)
737 {
738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
739 int ch, txq_id, ret;
740
741 /* Turn off all Tx DMA fifos */
742 spin_lock(&trans_pcie->irq_lock);
743
744 iwl_scd_deactivate_fifos(trans);
745
746 /* Stop each Tx DMA channel, and wait for it to be idle */
747 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
748 iwl_write_direct32(trans,
749 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
750 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
751 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
752 if (ret < 0)
753 IWL_ERR(trans,
754 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
755 ch,
756 iwl_read_direct32(trans,
757 FH_TSSR_TX_STATUS_REG));
758 }
759 spin_unlock(&trans_pcie->irq_lock);
760
761 /*
762 * This function can be called before the op_mode disabled the
763 * queues. This happens when we have an rfkill interrupt.
764 * Since we stop Tx altogether - mark the queues as stopped.
765 */
766 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
767 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
768
769 /* This can happen: start_hw, stop_device */
770 if (!trans_pcie->txq)
771 return 0;
772
773 /* Unmap DMA from host system and free skb's */
774 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
775 txq_id++)
776 iwl_pcie_txq_unmap(trans, txq_id);
777
778 return 0;
779 }
780
781 /*
782 * iwl_trans_tx_free - Free TXQ Context
783 *
784 * Destroy all TX DMA queues and structures
785 */
iwl_pcie_tx_free(struct iwl_trans * trans)786 void iwl_pcie_tx_free(struct iwl_trans *trans)
787 {
788 int txq_id;
789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
790
791 /* Tx queues */
792 if (trans_pcie->txq) {
793 for (txq_id = 0;
794 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
795 iwl_pcie_txq_free(trans, txq_id);
796 }
797
798 kfree(trans_pcie->txq);
799 trans_pcie->txq = NULL;
800
801 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
802
803 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
804 }
805
806 /*
807 * iwl_pcie_tx_alloc - allocate TX context
808 * Allocate all Tx DMA structures and initialize them
809 */
iwl_pcie_tx_alloc(struct iwl_trans * trans)810 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
811 {
812 int ret;
813 int txq_id, slots_num;
814 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
815
816 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
817 sizeof(struct iwlagn_scd_bc_tbl);
818
819 /*It is not allowed to alloc twice, so warn when this happens.
820 * We cannot rely on the previous allocation, so free and fail */
821 if (WARN_ON(trans_pcie->txq)) {
822 ret = -EINVAL;
823 goto error;
824 }
825
826 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
827 scd_bc_tbls_size);
828 if (ret) {
829 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
830 goto error;
831 }
832
833 /* Alloc keep-warm buffer */
834 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
835 if (ret) {
836 IWL_ERR(trans, "Keep Warm allocation failed\n");
837 goto error;
838 }
839
840 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
841 sizeof(struct iwl_txq), GFP_KERNEL);
842 if (!trans_pcie->txq) {
843 IWL_ERR(trans, "Not enough memory for txq\n");
844 ret = -ENOMEM;
845 goto error;
846 }
847
848 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
849 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
850 txq_id++) {
851 slots_num = (txq_id == trans_pcie->cmd_queue) ?
852 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
853 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
854 slots_num, txq_id);
855 if (ret) {
856 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
857 goto error;
858 }
859 }
860
861 return 0;
862
863 error:
864 iwl_pcie_tx_free(trans);
865
866 return ret;
867 }
iwl_pcie_tx_init(struct iwl_trans * trans)868 int iwl_pcie_tx_init(struct iwl_trans *trans)
869 {
870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
871 int ret;
872 int txq_id, slots_num;
873 bool alloc = false;
874
875 if (!trans_pcie->txq) {
876 ret = iwl_pcie_tx_alloc(trans);
877 if (ret)
878 goto error;
879 alloc = true;
880 }
881
882 spin_lock(&trans_pcie->irq_lock);
883
884 /* Turn off all Tx DMA fifos */
885 iwl_scd_deactivate_fifos(trans);
886
887 /* Tell NIC where to find the "keep warm" buffer */
888 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
889 trans_pcie->kw.dma >> 4);
890
891 spin_unlock(&trans_pcie->irq_lock);
892
893 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
894 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
895 txq_id++) {
896 slots_num = (txq_id == trans_pcie->cmd_queue) ?
897 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
898 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
899 slots_num, txq_id);
900 if (ret) {
901 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
902 goto error;
903 }
904 }
905
906 return 0;
907 error:
908 /*Upon error, free only if we allocated something */
909 if (alloc)
910 iwl_pcie_tx_free(trans);
911 return ret;
912 }
913
iwl_pcie_txq_progress(struct iwl_trans_pcie * trans_pcie,struct iwl_txq * txq)914 static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie,
915 struct iwl_txq *txq)
916 {
917 if (!trans_pcie->wd_timeout)
918 return;
919
920 /*
921 * if empty delete timer, otherwise move timer forward
922 * since we're making progress on this queue
923 */
924 if (txq->q.read_ptr == txq->q.write_ptr)
925 del_timer(&txq->stuck_timer);
926 else
927 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
928 }
929
930 /* Frees buffers until index _not_ inclusive */
iwl_trans_pcie_reclaim(struct iwl_trans * trans,int txq_id,int ssn,struct sk_buff_head * skbs)931 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
932 struct sk_buff_head *skbs)
933 {
934 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
935 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
936 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
937 struct iwl_queue *q = &txq->q;
938 int last_to_free;
939
940 /* This function is not meant to release cmd queue*/
941 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
942 return;
943
944 spin_lock_bh(&txq->lock);
945
946 if (!txq->active) {
947 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
948 txq_id, ssn);
949 goto out;
950 }
951
952 if (txq->q.read_ptr == tfd_num)
953 goto out;
954
955 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
956 txq_id, txq->q.read_ptr, tfd_num, ssn);
957
958 /*Since we free until index _not_ inclusive, the one before index is
959 * the last we will free. This one must be used */
960 last_to_free = iwl_queue_dec_wrap(tfd_num);
961
962 if (!iwl_queue_used(q, last_to_free)) {
963 IWL_ERR(trans,
964 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
965 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
966 q->write_ptr, q->read_ptr);
967 goto out;
968 }
969
970 if (WARN_ON(!skb_queue_empty(skbs)))
971 goto out;
972
973 for (;
974 q->read_ptr != tfd_num;
975 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
976
977 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
978 continue;
979
980 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
981
982 txq->entries[txq->q.read_ptr].skb = NULL;
983
984 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
985
986 iwl_pcie_txq_free_tfd(trans, txq);
987 }
988
989 iwl_pcie_txq_progress(trans_pcie, txq);
990
991 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
992 iwl_wake_queue(trans, txq);
993 out:
994 spin_unlock_bh(&txq->lock);
995 }
996
997 /*
998 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
999 *
1000 * When FW advances 'R' index, all entries between old and new 'R' index
1001 * need to be reclaimed. As result, some free space forms. If there is
1002 * enough free space (> low mark), wake the stack that feeds us.
1003 */
iwl_pcie_cmdq_reclaim(struct iwl_trans * trans,int txq_id,int idx)1004 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1005 {
1006 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1007 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1008 struct iwl_queue *q = &txq->q;
1009 unsigned long flags;
1010 int nfreed = 0;
1011
1012 lockdep_assert_held(&txq->lock);
1013
1014 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1015 IWL_ERR(trans,
1016 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1017 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1018 q->write_ptr, q->read_ptr);
1019 return;
1020 }
1021
1022 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1023 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1024
1025 if (nfreed++ > 0) {
1026 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1027 idx, q->write_ptr, q->read_ptr);
1028 iwl_force_nmi(trans);
1029 }
1030 }
1031
1032 if (trans->cfg->base_params->apmg_wake_up_wa &&
1033 q->read_ptr == q->write_ptr) {
1034 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1035 WARN_ON(!trans_pcie->cmd_in_flight);
1036 trans_pcie->cmd_in_flight = false;
1037 __iwl_trans_pcie_clear_bit(trans,
1038 CSR_GP_CNTRL,
1039 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1040 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1041 }
1042
1043 iwl_pcie_txq_progress(trans_pcie, txq);
1044 }
1045
iwl_pcie_txq_set_ratid_map(struct iwl_trans * trans,u16 ra_tid,u16 txq_id)1046 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1047 u16 txq_id)
1048 {
1049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1050 u32 tbl_dw_addr;
1051 u32 tbl_dw;
1052 u16 scd_q2ratid;
1053
1054 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1055
1056 tbl_dw_addr = trans_pcie->scd_base_addr +
1057 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1058
1059 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1060
1061 if (txq_id & 0x1)
1062 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1063 else
1064 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1065
1066 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1067
1068 return 0;
1069 }
1070
1071 /* Receiver address (actually, Rx station's index into station table),
1072 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1073 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1074
iwl_trans_pcie_txq_enable(struct iwl_trans * trans,int txq_id,u16 ssn,const struct iwl_trans_txq_scd_cfg * cfg)1075 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1076 const struct iwl_trans_txq_scd_cfg *cfg)
1077 {
1078 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1079 int fifo = -1;
1080
1081 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1082 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1083
1084 if (cfg) {
1085 fifo = cfg->fifo;
1086
1087 /* Disable the scheduler prior configuring the cmd queue */
1088 if (txq_id == trans_pcie->cmd_queue &&
1089 trans_pcie->scd_set_active)
1090 iwl_scd_enable_set_active(trans, 0);
1091
1092 /* Stop this Tx queue before configuring it */
1093 iwl_scd_txq_set_inactive(trans, txq_id);
1094
1095 /* Set this queue as a chain-building queue unless it is CMD */
1096 if (txq_id != trans_pcie->cmd_queue)
1097 iwl_scd_txq_set_chain(trans, txq_id);
1098
1099 if (cfg->aggregate) {
1100 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1101
1102 /* Map receiver-address / traffic-ID to this queue */
1103 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1104
1105 /* enable aggregations for the queue */
1106 iwl_scd_txq_enable_agg(trans, txq_id);
1107 trans_pcie->txq[txq_id].ampdu = true;
1108 } else {
1109 /*
1110 * disable aggregations for the queue, this will also
1111 * make the ra_tid mapping configuration irrelevant
1112 * since it is now a non-AGG queue.
1113 */
1114 iwl_scd_txq_disable_agg(trans, txq_id);
1115
1116 ssn = trans_pcie->txq[txq_id].q.read_ptr;
1117 }
1118 }
1119
1120 /* Place first TFD at index corresponding to start sequence number.
1121 * Assumes that ssn_idx is valid (!= 0xFFF) */
1122 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
1123 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
1124
1125 if (cfg) {
1126 u8 frame_limit = cfg->frame_limit;
1127
1128 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1129 (ssn & 0xff) | (txq_id << 8));
1130 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1131
1132 /* Set up Tx window size and frame limit for this queue */
1133 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1134 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1135 iwl_trans_write_mem32(trans,
1136 trans_pcie->scd_base_addr +
1137 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1138 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1139 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1140 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1141 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1142
1143 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1144 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1145 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1146 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1147 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1148 SCD_QUEUE_STTS_REG_MSK);
1149
1150 /* enable the scheduler for this queue (only) */
1151 if (txq_id == trans_pcie->cmd_queue &&
1152 trans_pcie->scd_set_active)
1153 iwl_scd_enable_set_active(trans, BIT(txq_id));
1154 }
1155
1156 trans_pcie->txq[txq_id].active = true;
1157 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n",
1158 txq_id, fifo, ssn & 0xff);
1159 }
1160
iwl_trans_pcie_txq_disable(struct iwl_trans * trans,int txq_id,bool configure_scd)1161 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1162 bool configure_scd)
1163 {
1164 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1165 u32 stts_addr = trans_pcie->scd_base_addr +
1166 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1167 static const u32 zero_val[4] = {};
1168
1169 /*
1170 * Upon HW Rfkill - we stop the device, and then stop the queues
1171 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1172 * allow the op_mode to call txq_disable after it already called
1173 * stop_device.
1174 */
1175 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1176 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1177 "queue %d not used", txq_id);
1178 return;
1179 }
1180
1181 if (configure_scd) {
1182 iwl_scd_txq_set_inactive(trans, txq_id);
1183
1184 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1185 ARRAY_SIZE(zero_val));
1186 }
1187
1188 iwl_pcie_txq_unmap(trans, txq_id);
1189 trans_pcie->txq[txq_id].ampdu = false;
1190
1191 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1192 }
1193
1194 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1195
1196 /*
1197 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1198 * @priv: device private data point
1199 * @cmd: a pointer to the ucode command structure
1200 *
1201 * The function returns < 0 values to indicate the operation
1202 * failed. On success, it returns the index (>= 0) of command in the
1203 * command queue.
1204 */
iwl_pcie_enqueue_hcmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1205 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1206 struct iwl_host_cmd *cmd)
1207 {
1208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1209 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1210 struct iwl_queue *q = &txq->q;
1211 struct iwl_device_cmd *out_cmd;
1212 struct iwl_cmd_meta *out_meta;
1213 unsigned long flags;
1214 void *dup_buf = NULL;
1215 dma_addr_t phys_addr;
1216 int idx;
1217 u16 copy_size, cmd_size, scratch_size;
1218 bool had_nocopy = false;
1219 int i, ret;
1220 u32 cmd_pos;
1221 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1222 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1223
1224 copy_size = sizeof(out_cmd->hdr);
1225 cmd_size = sizeof(out_cmd->hdr);
1226
1227 /* need one for the header if the first is NOCOPY */
1228 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1229
1230 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1231 cmddata[i] = cmd->data[i];
1232 cmdlen[i] = cmd->len[i];
1233
1234 if (!cmd->len[i])
1235 continue;
1236
1237 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1238 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1239 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1240
1241 if (copy > cmdlen[i])
1242 copy = cmdlen[i];
1243 cmdlen[i] -= copy;
1244 cmddata[i] += copy;
1245 copy_size += copy;
1246 }
1247
1248 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1249 had_nocopy = true;
1250 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1251 idx = -EINVAL;
1252 goto free_dup_buf;
1253 }
1254 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1255 /*
1256 * This is also a chunk that isn't copied
1257 * to the static buffer so set had_nocopy.
1258 */
1259 had_nocopy = true;
1260
1261 /* only allowed once */
1262 if (WARN_ON(dup_buf)) {
1263 idx = -EINVAL;
1264 goto free_dup_buf;
1265 }
1266
1267 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1268 GFP_ATOMIC);
1269 if (!dup_buf)
1270 return -ENOMEM;
1271 } else {
1272 /* NOCOPY must not be followed by normal! */
1273 if (WARN_ON(had_nocopy)) {
1274 idx = -EINVAL;
1275 goto free_dup_buf;
1276 }
1277 copy_size += cmdlen[i];
1278 }
1279 cmd_size += cmd->len[i];
1280 }
1281
1282 /*
1283 * If any of the command structures end up being larger than
1284 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1285 * allocated into separate TFDs, then we will need to
1286 * increase the size of the buffers.
1287 */
1288 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1289 "Command %s (%#x) is too large (%d bytes)\n",
1290 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1291 idx = -EINVAL;
1292 goto free_dup_buf;
1293 }
1294
1295 spin_lock_bh(&txq->lock);
1296
1297 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1298 spin_unlock_bh(&txq->lock);
1299
1300 IWL_ERR(trans, "No space in command queue\n");
1301 iwl_op_mode_cmd_queue_full(trans->op_mode);
1302 idx = -ENOSPC;
1303 goto free_dup_buf;
1304 }
1305
1306 idx = get_cmd_index(q, q->write_ptr);
1307 out_cmd = txq->entries[idx].cmd;
1308 out_meta = &txq->entries[idx].meta;
1309
1310 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1311 if (cmd->flags & CMD_WANT_SKB)
1312 out_meta->source = cmd;
1313
1314 /* set up the header */
1315
1316 out_cmd->hdr.cmd = cmd->id;
1317 out_cmd->hdr.flags = 0;
1318 out_cmd->hdr.sequence =
1319 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1320 INDEX_TO_SEQ(q->write_ptr));
1321
1322 /* and copy the data that needs to be copied */
1323 cmd_pos = offsetof(struct iwl_device_cmd, payload);
1324 copy_size = sizeof(out_cmd->hdr);
1325 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1326 int copy;
1327
1328 if (!cmd->len[i])
1329 continue;
1330
1331 /* copy everything if not nocopy/dup */
1332 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1333 IWL_HCMD_DFL_DUP))) {
1334 copy = cmd->len[i];
1335
1336 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1337 cmd_pos += copy;
1338 copy_size += copy;
1339 continue;
1340 }
1341
1342 /*
1343 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1344 * in total (for the scratchbuf handling), but copy up to what
1345 * we can fit into the payload for debug dump purposes.
1346 */
1347 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1348
1349 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1350 cmd_pos += copy;
1351
1352 /* However, treat copy_size the proper way, we need it below */
1353 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1354 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1355
1356 if (copy > cmd->len[i])
1357 copy = cmd->len[i];
1358 copy_size += copy;
1359 }
1360 }
1361
1362 IWL_DEBUG_HC(trans,
1363 "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1364 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1365 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
1366 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1367
1368 /* start the TFD with the scratchbuf */
1369 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1370 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1371 iwl_pcie_txq_build_tfd(trans, txq,
1372 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1373 scratch_size, true);
1374
1375 /* map first command fragment, if any remains */
1376 if (copy_size > scratch_size) {
1377 phys_addr = dma_map_single(trans->dev,
1378 ((u8 *)&out_cmd->hdr) + scratch_size,
1379 copy_size - scratch_size,
1380 DMA_TO_DEVICE);
1381 if (dma_mapping_error(trans->dev, phys_addr)) {
1382 iwl_pcie_tfd_unmap(trans, out_meta,
1383 &txq->tfds[q->write_ptr]);
1384 idx = -ENOMEM;
1385 goto out;
1386 }
1387
1388 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1389 copy_size - scratch_size, false);
1390 }
1391
1392 /* map the remaining (adjusted) nocopy/dup fragments */
1393 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1394 const void *data = cmddata[i];
1395
1396 if (!cmdlen[i])
1397 continue;
1398 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1399 IWL_HCMD_DFL_DUP)))
1400 continue;
1401 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1402 data = dup_buf;
1403 phys_addr = dma_map_single(trans->dev, (void *)data,
1404 cmdlen[i], DMA_TO_DEVICE);
1405 if (dma_mapping_error(trans->dev, phys_addr)) {
1406 iwl_pcie_tfd_unmap(trans, out_meta,
1407 &txq->tfds[q->write_ptr]);
1408 idx = -ENOMEM;
1409 goto out;
1410 }
1411
1412 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1413 }
1414
1415 out_meta->flags = cmd->flags;
1416 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1417 kzfree(txq->entries[idx].free_buf);
1418 txq->entries[idx].free_buf = dup_buf;
1419
1420 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
1421
1422 /* start timer if queue currently empty */
1423 if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout)
1424 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1425
1426 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1427
1428 /*
1429 * wake up the NIC to make sure that the firmware will see the host
1430 * command - we will let the NIC sleep once all the host commands
1431 * returned. This needs to be done only on NICs that have
1432 * apmg_wake_up_wa set.
1433 */
1434 if (trans->cfg->base_params->apmg_wake_up_wa &&
1435 !trans_pcie->cmd_in_flight) {
1436 trans_pcie->cmd_in_flight = true;
1437 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1438 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1439 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1440 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1441 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1442 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1443 15000);
1444 if (ret < 0) {
1445 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1446 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1447 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1448 trans_pcie->cmd_in_flight = false;
1449 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1450 idx = -EIO;
1451 goto out;
1452 }
1453 }
1454
1455 /* Increment and update queue's write index */
1456 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1457 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1458
1459 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1460
1461 out:
1462 spin_unlock_bh(&txq->lock);
1463 free_dup_buf:
1464 if (idx < 0)
1465 kfree(dup_buf);
1466 return idx;
1467 }
1468
1469 /*
1470 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1471 * @rxb: Rx buffer to reclaim
1472 * @handler_status: return value of the handler of the command
1473 * (put in setup_rx_handlers)
1474 *
1475 * If an Rx buffer has an async callback associated with it the callback
1476 * will be executed. The attached skb (if present) will only be freed
1477 * if the callback returns 1
1478 */
iwl_pcie_hcmd_complete(struct iwl_trans * trans,struct iwl_rx_cmd_buffer * rxb,int handler_status)1479 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1480 struct iwl_rx_cmd_buffer *rxb, int handler_status)
1481 {
1482 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1483 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1484 int txq_id = SEQ_TO_QUEUE(sequence);
1485 int index = SEQ_TO_INDEX(sequence);
1486 int cmd_index;
1487 struct iwl_device_cmd *cmd;
1488 struct iwl_cmd_meta *meta;
1489 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1490 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1491
1492 /* If a Tx command is being handled and it isn't in the actual
1493 * command queue then there a command routing bug has been introduced
1494 * in the queue management code. */
1495 if (WARN(txq_id != trans_pcie->cmd_queue,
1496 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1497 txq_id, trans_pcie->cmd_queue, sequence,
1498 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1499 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1500 iwl_print_hex_error(trans, pkt, 32);
1501 return;
1502 }
1503
1504 spin_lock_bh(&txq->lock);
1505
1506 cmd_index = get_cmd_index(&txq->q, index);
1507 cmd = txq->entries[cmd_index].cmd;
1508 meta = &txq->entries[cmd_index].meta;
1509
1510 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1511
1512 /* Input error checking is done when commands are added to queue. */
1513 if (meta->flags & CMD_WANT_SKB) {
1514 struct page *p = rxb_steal_page(rxb);
1515
1516 meta->source->resp_pkt = pkt;
1517 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1518 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1519 meta->source->handler_status = handler_status;
1520 }
1521
1522 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1523
1524 if (!(meta->flags & CMD_ASYNC)) {
1525 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1526 IWL_WARN(trans,
1527 "HCMD_ACTIVE already clear for command %s\n",
1528 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1529 }
1530 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1531 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1532 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1533 wake_up(&trans_pcie->wait_command_queue);
1534 }
1535
1536 meta->flags = 0;
1537
1538 spin_unlock_bh(&txq->lock);
1539 }
1540
1541 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1542
iwl_pcie_send_hcmd_async(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1543 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1544 struct iwl_host_cmd *cmd)
1545 {
1546 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1547 int ret;
1548
1549 /* An asynchronous command can not expect an SKB to be set. */
1550 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1551 return -EINVAL;
1552
1553 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1554 if (ret < 0) {
1555 IWL_ERR(trans,
1556 "Error sending %s: enqueue_hcmd failed: %d\n",
1557 get_cmd_string(trans_pcie, cmd->id), ret);
1558 return ret;
1559 }
1560 return 0;
1561 }
1562
iwl_pcie_send_hcmd_sync(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1563 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1564 struct iwl_host_cmd *cmd)
1565 {
1566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1567 int cmd_idx;
1568 int ret;
1569
1570 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1571 get_cmd_string(trans_pcie, cmd->id));
1572
1573 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1574 &trans->status),
1575 "Command %s: a command is already active!\n",
1576 get_cmd_string(trans_pcie, cmd->id)))
1577 return -EIO;
1578
1579 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1580 get_cmd_string(trans_pcie, cmd->id));
1581
1582 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1583 if (cmd_idx < 0) {
1584 ret = cmd_idx;
1585 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1586 IWL_ERR(trans,
1587 "Error sending %s: enqueue_hcmd failed: %d\n",
1588 get_cmd_string(trans_pcie, cmd->id), ret);
1589 return ret;
1590 }
1591
1592 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1593 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1594 &trans->status),
1595 HOST_COMPLETE_TIMEOUT);
1596 if (!ret) {
1597 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1598 struct iwl_queue *q = &txq->q;
1599
1600 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1601 get_cmd_string(trans_pcie, cmd->id),
1602 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1603
1604 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1605 q->read_ptr, q->write_ptr);
1606
1607 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1608 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1609 get_cmd_string(trans_pcie, cmd->id));
1610 ret = -ETIMEDOUT;
1611
1612 iwl_force_nmi(trans);
1613 iwl_trans_fw_error(trans);
1614
1615 goto cancel;
1616 }
1617
1618 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1619 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1620 get_cmd_string(trans_pcie, cmd->id));
1621 dump_stack();
1622 ret = -EIO;
1623 goto cancel;
1624 }
1625
1626 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1627 test_bit(STATUS_RFKILL, &trans->status)) {
1628 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1629 ret = -ERFKILL;
1630 goto cancel;
1631 }
1632
1633 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1634 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1635 get_cmd_string(trans_pcie, cmd->id));
1636 ret = -EIO;
1637 goto cancel;
1638 }
1639
1640 return 0;
1641
1642 cancel:
1643 if (cmd->flags & CMD_WANT_SKB) {
1644 /*
1645 * Cancel the CMD_WANT_SKB flag for the cmd in the
1646 * TX cmd queue. Otherwise in case the cmd comes
1647 * in later, it will possibly set an invalid
1648 * address (cmd->meta.source).
1649 */
1650 trans_pcie->txq[trans_pcie->cmd_queue].
1651 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1652 }
1653
1654 if (cmd->resp_pkt) {
1655 iwl_free_resp(cmd);
1656 cmd->resp_pkt = NULL;
1657 }
1658
1659 return ret;
1660 }
1661
iwl_trans_pcie_send_hcmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1662 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1663 {
1664 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1665 test_bit(STATUS_RFKILL, &trans->status)) {
1666 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1667 cmd->id);
1668 return -ERFKILL;
1669 }
1670
1671 if (cmd->flags & CMD_ASYNC)
1672 return iwl_pcie_send_hcmd_async(trans, cmd);
1673
1674 /* We still can fail on RFKILL that can be asserted while we wait */
1675 return iwl_pcie_send_hcmd_sync(trans, cmd);
1676 }
1677
iwl_trans_pcie_tx(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_device_cmd * dev_cmd,int txq_id)1678 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1679 struct iwl_device_cmd *dev_cmd, int txq_id)
1680 {
1681 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1682 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1683 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1684 struct iwl_cmd_meta *out_meta;
1685 struct iwl_txq *txq;
1686 struct iwl_queue *q;
1687 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1688 void *tb1_addr;
1689 u16 len, tb1_len, tb2_len;
1690 bool wait_write_ptr;
1691 __le16 fc = hdr->frame_control;
1692 u8 hdr_len = ieee80211_hdrlen(fc);
1693 u16 wifi_seq;
1694
1695 txq = &trans_pcie->txq[txq_id];
1696 q = &txq->q;
1697
1698 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1699 "TX on unused queue %d\n", txq_id))
1700 return -EINVAL;
1701
1702 spin_lock(&txq->lock);
1703
1704 /* In AGG mode, the index in the ring must correspond to the WiFi
1705 * sequence number. This is a HW requirements to help the SCD to parse
1706 * the BA.
1707 * Check here that the packets are in the right place on the ring.
1708 */
1709 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1710 WARN_ONCE(txq->ampdu &&
1711 (wifi_seq & 0xff) != q->write_ptr,
1712 "Q: %d WiFi Seq %d tfdNum %d",
1713 txq_id, wifi_seq, q->write_ptr);
1714
1715 /* Set up driver data for this TFD */
1716 txq->entries[q->write_ptr].skb = skb;
1717 txq->entries[q->write_ptr].cmd = dev_cmd;
1718
1719 dev_cmd->hdr.sequence =
1720 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1721 INDEX_TO_SEQ(q->write_ptr)));
1722
1723 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1724 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1725 offsetof(struct iwl_tx_cmd, scratch);
1726
1727 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1728 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1729
1730 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1731 out_meta = &txq->entries[q->write_ptr].meta;
1732
1733 /*
1734 * The second TB (tb1) points to the remainder of the TX command
1735 * and the 802.11 header - dword aligned size
1736 * (This calculation modifies the TX command, so do it before the
1737 * setup of the first TB)
1738 */
1739 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1740 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1741 tb1_len = ALIGN(len, 4);
1742
1743 /* Tell NIC about any 2-byte padding after MAC header */
1744 if (tb1_len != len)
1745 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1746
1747 /* The first TB points to the scratchbuf data - min_copy bytes */
1748 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1749 IWL_HCMD_SCRATCHBUF_SIZE);
1750 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1751 IWL_HCMD_SCRATCHBUF_SIZE, true);
1752
1753 /* there must be data left over for TB1 or this code must be changed */
1754 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1755
1756 /* map the data for TB1 */
1757 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1758 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1759 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1760 goto out_err;
1761 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1762
1763 /*
1764 * Set up TFD's third entry to point directly to remainder
1765 * of skb, if any (802.11 null frames have no payload).
1766 */
1767 tb2_len = skb->len - hdr_len;
1768 if (tb2_len > 0) {
1769 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1770 skb->data + hdr_len,
1771 tb2_len, DMA_TO_DEVICE);
1772 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1773 iwl_pcie_tfd_unmap(trans, out_meta,
1774 &txq->tfds[q->write_ptr]);
1775 goto out_err;
1776 }
1777 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1778 }
1779
1780 /* Set up entry for this TFD in Tx byte-count array */
1781 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1782
1783 trace_iwlwifi_dev_tx(trans->dev, skb,
1784 &txq->tfds[txq->q.write_ptr],
1785 sizeof(struct iwl_tfd),
1786 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1787 skb->data + hdr_len, tb2_len);
1788 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1789 skb->data + hdr_len, tb2_len);
1790
1791 wait_write_ptr = ieee80211_has_morefrags(fc);
1792
1793 /* start timer if queue currently empty */
1794 if (txq->need_update && q->read_ptr == q->write_ptr &&
1795 trans_pcie->wd_timeout)
1796 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1797
1798 /* Tell device the write index *just past* this latest filled TFD */
1799 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1800 if (!wait_write_ptr)
1801 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1802
1803 /*
1804 * At this point the frame is "transmitted" successfully
1805 * and we will get a TX status notification eventually.
1806 */
1807 if (iwl_queue_space(q) < q->high_mark) {
1808 if (wait_write_ptr)
1809 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1810 else
1811 iwl_stop_queue(trans, txq);
1812 }
1813 spin_unlock(&txq->lock);
1814 return 0;
1815 out_err:
1816 spin_unlock(&txq->lock);
1817 return -1;
1818 }
1819