1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
microMIPS32_to_MIPS32(union mips_instruction * insn_ptr)95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
isBranchInstr(struct pt_regs * regs,struct mm_decoded_insn dec_insn,unsigned long * contpc)437 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443 unsigned int bit0;
444 union fpureg *fpr;
445
446 switch (insn.i_format.opcode) {
447 case spec_op:
448 switch (insn.r_format.func) {
449 case jalr_op:
450 if (insn.r_format.rd != 0) {
451 regs->regs[insn.r_format.rd] =
452 regs->cp0_epc + dec_insn.pc_inc +
453 dec_insn.next_pc_inc;
454 }
455 /* Fall through */
456 case jr_op:
457 /* For R6, JR already emulated in jalr_op */
458 if (NO_R6EMU && insn.r_format.func == jr_op)
459 break;
460 *contpc = regs->regs[insn.r_format.rs];
461 return 1;
462 }
463 break;
464 case bcond_op:
465 switch (insn.i_format.rt) {
466 case bltzal_op:
467 case bltzall_op:
468 if (NO_R6EMU && (insn.i_format.rs ||
469 insn.i_format.rt == bltzall_op))
470 break;
471
472 regs->regs[31] = regs->cp0_epc +
473 dec_insn.pc_inc +
474 dec_insn.next_pc_inc;
475 /* Fall through */
476 case bltzl_op:
477 if (NO_R6EMU)
478 break;
479 case bltz_op:
480 if ((long)regs->regs[insn.i_format.rs] < 0)
481 *contpc = regs->cp0_epc +
482 dec_insn.pc_inc +
483 (insn.i_format.simmediate << 2);
484 else
485 *contpc = regs->cp0_epc +
486 dec_insn.pc_inc +
487 dec_insn.next_pc_inc;
488 return 1;
489 case bgezal_op:
490 case bgezall_op:
491 if (NO_R6EMU && (insn.i_format.rs ||
492 insn.i_format.rt == bgezall_op))
493 break;
494
495 regs->regs[31] = regs->cp0_epc +
496 dec_insn.pc_inc +
497 dec_insn.next_pc_inc;
498 /* Fall through */
499 case bgezl_op:
500 if (NO_R6EMU)
501 break;
502 case bgez_op:
503 if ((long)regs->regs[insn.i_format.rs] >= 0)
504 *contpc = regs->cp0_epc +
505 dec_insn.pc_inc +
506 (insn.i_format.simmediate << 2);
507 else
508 *contpc = regs->cp0_epc +
509 dec_insn.pc_inc +
510 dec_insn.next_pc_inc;
511 return 1;
512 }
513 break;
514 case jalx_op:
515 set_isa16_mode(bit);
516 case jal_op:
517 regs->regs[31] = regs->cp0_epc +
518 dec_insn.pc_inc +
519 dec_insn.next_pc_inc;
520 /* Fall through */
521 case j_op:
522 *contpc = regs->cp0_epc + dec_insn.pc_inc;
523 *contpc >>= 28;
524 *contpc <<= 28;
525 *contpc |= (insn.j_format.target << 2);
526 /* Set microMIPS mode bit: XOR for jalx. */
527 *contpc ^= bit;
528 return 1;
529 case beql_op:
530 if (NO_R6EMU)
531 break;
532 case beq_op:
533 if (regs->regs[insn.i_format.rs] ==
534 regs->regs[insn.i_format.rt])
535 *contpc = regs->cp0_epc +
536 dec_insn.pc_inc +
537 (insn.i_format.simmediate << 2);
538 else
539 *contpc = regs->cp0_epc +
540 dec_insn.pc_inc +
541 dec_insn.next_pc_inc;
542 return 1;
543 case bnel_op:
544 if (NO_R6EMU)
545 break;
546 case bne_op:
547 if (regs->regs[insn.i_format.rs] !=
548 regs->regs[insn.i_format.rt])
549 *contpc = regs->cp0_epc +
550 dec_insn.pc_inc +
551 (insn.i_format.simmediate << 2);
552 else
553 *contpc = regs->cp0_epc +
554 dec_insn.pc_inc +
555 dec_insn.next_pc_inc;
556 return 1;
557 case blezl_op:
558 if (!insn.i_format.rt && NO_R6EMU)
559 break;
560 case blez_op:
561
562 /*
563 * Compact branches for R6 for the
564 * blez and blezl opcodes.
565 * BLEZ | rs = 0 | rt != 0 == BLEZALC
566 * BLEZ | rs = rt != 0 == BGEZALC
567 * BLEZ | rs != 0 | rt != 0 == BGEUC
568 * BLEZL | rs = 0 | rt != 0 == BLEZC
569 * BLEZL | rs = rt != 0 == BGEZC
570 * BLEZL | rs != 0 | rt != 0 == BGEC
571 *
572 * For real BLEZ{,L}, rt is always 0.
573 */
574 if (cpu_has_mips_r6 && insn.i_format.rt) {
575 if ((insn.i_format.opcode == blez_op) &&
576 ((!insn.i_format.rs && insn.i_format.rt) ||
577 (insn.i_format.rs == insn.i_format.rt)))
578 regs->regs[31] = regs->cp0_epc +
579 dec_insn.pc_inc;
580 *contpc = regs->cp0_epc + dec_insn.pc_inc +
581 dec_insn.next_pc_inc;
582
583 return 1;
584 }
585 if ((long)regs->regs[insn.i_format.rs] <= 0)
586 *contpc = regs->cp0_epc +
587 dec_insn.pc_inc +
588 (insn.i_format.simmediate << 2);
589 else
590 *contpc = regs->cp0_epc +
591 dec_insn.pc_inc +
592 dec_insn.next_pc_inc;
593 return 1;
594 case bgtzl_op:
595 if (!insn.i_format.rt && NO_R6EMU)
596 break;
597 case bgtz_op:
598 /*
599 * Compact branches for R6 for the
600 * bgtz and bgtzl opcodes.
601 * BGTZ | rs = 0 | rt != 0 == BGTZALC
602 * BGTZ | rs = rt != 0 == BLTZALC
603 * BGTZ | rs != 0 | rt != 0 == BLTUC
604 * BGTZL | rs = 0 | rt != 0 == BGTZC
605 * BGTZL | rs = rt != 0 == BLTZC
606 * BGTZL | rs != 0 | rt != 0 == BLTC
607 *
608 * *ZALC varint for BGTZ &&& rt != 0
609 * For real GTZ{,L}, rt is always 0.
610 */
611 if (cpu_has_mips_r6 && insn.i_format.rt) {
612 if ((insn.i_format.opcode == blez_op) &&
613 ((!insn.i_format.rs && insn.i_format.rt) ||
614 (insn.i_format.rs == insn.i_format.rt)))
615 regs->regs[31] = regs->cp0_epc +
616 dec_insn.pc_inc;
617 *contpc = regs->cp0_epc + dec_insn.pc_inc +
618 dec_insn.next_pc_inc;
619
620 return 1;
621 }
622
623 if ((long)regs->regs[insn.i_format.rs] > 0)
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 (insn.i_format.simmediate << 2);
627 else
628 *contpc = regs->cp0_epc +
629 dec_insn.pc_inc +
630 dec_insn.next_pc_inc;
631 return 1;
632 case pop10_op:
633 case pop30_op:
634 if (!cpu_has_mips_r6)
635 break;
636 if (insn.i_format.rt && !insn.i_format.rs)
637 regs->regs[31] = regs->cp0_epc + 4;
638 *contpc = regs->cp0_epc + dec_insn.pc_inc +
639 dec_insn.next_pc_inc;
640
641 return 1;
642 #ifdef CONFIG_CPU_CAVIUM_OCTEON
643 case lwc2_op: /* This is bbit0 on Octeon */
644 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
645 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
646 else
647 *contpc = regs->cp0_epc + 8;
648 return 1;
649 case ldc2_op: /* This is bbit032 on Octeon */
650 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
651 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
652 else
653 *contpc = regs->cp0_epc + 8;
654 return 1;
655 case swc2_op: /* This is bbit1 on Octeon */
656 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
657 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
658 else
659 *contpc = regs->cp0_epc + 8;
660 return 1;
661 case sdc2_op: /* This is bbit132 on Octeon */
662 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
663 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
664 else
665 *contpc = regs->cp0_epc + 8;
666 return 1;
667 #else
668 case bc6_op:
669 /*
670 * Only valid for MIPS R6 but we can still end up
671 * here from a broken userland so just tell emulator
672 * this is not a branch and let it break later on.
673 */
674 if (!cpu_has_mips_r6)
675 break;
676 *contpc = regs->cp0_epc + dec_insn.pc_inc +
677 dec_insn.next_pc_inc;
678
679 return 1;
680 case balc6_op:
681 if (!cpu_has_mips_r6)
682 break;
683 regs->regs[31] = regs->cp0_epc + 4;
684 *contpc = regs->cp0_epc + dec_insn.pc_inc +
685 dec_insn.next_pc_inc;
686
687 return 1;
688 case pop66_op:
689 if (!cpu_has_mips_r6)
690 break;
691 *contpc = regs->cp0_epc + dec_insn.pc_inc +
692 dec_insn.next_pc_inc;
693
694 return 1;
695 case pop76_op:
696 if (!cpu_has_mips_r6)
697 break;
698 if (!insn.i_format.rs)
699 regs->regs[31] = regs->cp0_epc + 4;
700 *contpc = regs->cp0_epc + dec_insn.pc_inc +
701 dec_insn.next_pc_inc;
702
703 return 1;
704 #endif
705 case cop0_op:
706 case cop1_op:
707 /* Need to check for R6 bc1nez and bc1eqz branches */
708 if (cpu_has_mips_r6 &&
709 ((insn.i_format.rs == bc1eqz_op) ||
710 (insn.i_format.rs == bc1nez_op))) {
711 bit = 0;
712 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
713 bit0 = get_fpr32(fpr, 0) & 0x1;
714 switch (insn.i_format.rs) {
715 case bc1eqz_op:
716 bit = bit0 == 0;
717 break;
718 case bc1nez_op:
719 bit = bit0 != 0;
720 break;
721 }
722 if (bit)
723 *contpc = regs->cp0_epc +
724 dec_insn.pc_inc +
725 (insn.i_format.simmediate << 2);
726 else
727 *contpc = regs->cp0_epc +
728 dec_insn.pc_inc +
729 dec_insn.next_pc_inc;
730
731 return 1;
732 }
733 /* R2/R6 compatible cop1 instruction. Fall through */
734 case cop2_op:
735 case cop1x_op:
736 if (insn.i_format.rs == bc_op) {
737 preempt_disable();
738 if (is_fpu_owner())
739 fcr31 = read_32bit_cp1_register(CP1_STATUS);
740 else
741 fcr31 = current->thread.fpu.fcr31;
742 preempt_enable();
743
744 bit = (insn.i_format.rt >> 2);
745 bit += (bit != 0);
746 bit += 23;
747 switch (insn.i_format.rt & 3) {
748 case 0: /* bc1f */
749 case 2: /* bc1fl */
750 if (~fcr31 & (1 << bit))
751 *contpc = regs->cp0_epc +
752 dec_insn.pc_inc +
753 (insn.i_format.simmediate << 2);
754 else
755 *contpc = regs->cp0_epc +
756 dec_insn.pc_inc +
757 dec_insn.next_pc_inc;
758 return 1;
759 case 1: /* bc1t */
760 case 3: /* bc1tl */
761 if (fcr31 & (1 << bit))
762 *contpc = regs->cp0_epc +
763 dec_insn.pc_inc +
764 (insn.i_format.simmediate << 2);
765 else
766 *contpc = regs->cp0_epc +
767 dec_insn.pc_inc +
768 dec_insn.next_pc_inc;
769 return 1;
770 }
771 }
772 break;
773 }
774 return 0;
775 }
776
777 /*
778 * In the Linux kernel, we support selection of FPR format on the
779 * basis of the Status.FR bit. If an FPU is not present, the FR bit
780 * is hardwired to zero, which would imply a 32-bit FPU even for
781 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
782 * FPU emu is slow and bulky and optimizing this function offers fairly
783 * sizeable benefits so we try to be clever and make this function return
784 * a constant whenever possible, that is on 64-bit kernels without O32
785 * compatibility enabled and on 32-bit without 64-bit FPU support.
786 */
cop1_64bit(struct pt_regs * xcp)787 static inline int cop1_64bit(struct pt_regs *xcp)
788 {
789 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
790 return 1;
791 else if (config_enabled(CONFIG_32BIT) &&
792 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
793 return 0;
794
795 return !test_thread_flag(TIF_32BIT_FPREGS);
796 }
797
hybrid_fprs(void)798 static inline bool hybrid_fprs(void)
799 {
800 return test_thread_flag(TIF_HYBRID_FPREGS);
801 }
802
803 #define SIFROMREG(si, x) \
804 do { \
805 if (cop1_64bit(xcp) && !hybrid_fprs()) \
806 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
807 else \
808 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
809 } while (0)
810
811 #define SITOREG(si, x) \
812 do { \
813 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
814 unsigned i; \
815 set_fpr32(&ctx->fpr[x], 0, si); \
816 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
817 set_fpr32(&ctx->fpr[x], i, 0); \
818 } else { \
819 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
820 } \
821 } while (0)
822
823 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
824
825 #define SITOHREG(si, x) \
826 do { \
827 unsigned i; \
828 set_fpr32(&ctx->fpr[x], 1, si); \
829 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
830 set_fpr32(&ctx->fpr[x], i, 0); \
831 } while (0)
832
833 #define DIFROMREG(di, x) \
834 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
835
836 #define DITOREG(di, x) \
837 do { \
838 unsigned fpr, i; \
839 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
840 set_fpr64(&ctx->fpr[fpr], 0, di); \
841 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
842 set_fpr64(&ctx->fpr[fpr], i, 0); \
843 } while (0)
844
845 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
846 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
847 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
848 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
849
850 /*
851 * Emulate a CFC1 instruction.
852 */
cop1_cfc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)853 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
854 mips_instruction ir)
855 {
856 u32 fcr31 = ctx->fcr31;
857 u32 value = 0;
858
859 switch (MIPSInst_RD(ir)) {
860 case FPCREG_CSR:
861 value = fcr31;
862 pr_debug("%p gpr[%d]<-csr=%08x\n",
863 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
864 break;
865
866 case FPCREG_FENR:
867 if (!cpu_has_mips_r)
868 break;
869 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
870 MIPS_FENR_FS;
871 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
872 pr_debug("%p gpr[%d]<-enr=%08x\n",
873 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
874 break;
875
876 case FPCREG_FEXR:
877 if (!cpu_has_mips_r)
878 break;
879 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
880 pr_debug("%p gpr[%d]<-exr=%08x\n",
881 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
882 break;
883
884 case FPCREG_FCCR:
885 if (!cpu_has_mips_r)
886 break;
887 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
888 MIPS_FCCR_COND0;
889 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
890 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
891 pr_debug("%p gpr[%d]<-ccr=%08x\n",
892 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
893 break;
894
895 case FPCREG_RID:
896 value = boot_cpu_data.fpu_id;
897 break;
898
899 default:
900 break;
901 }
902
903 if (MIPSInst_RT(ir))
904 xcp->regs[MIPSInst_RT(ir)] = value;
905 }
906
907 /*
908 * Emulate a CTC1 instruction.
909 */
cop1_ctc(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)910 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
911 mips_instruction ir)
912 {
913 u32 fcr31 = ctx->fcr31;
914 u32 value;
915 u32 mask;
916
917 if (MIPSInst_RT(ir) == 0)
918 value = 0;
919 else
920 value = xcp->regs[MIPSInst_RT(ir)];
921
922 switch (MIPSInst_RD(ir)) {
923 case FPCREG_CSR:
924 pr_debug("%p gpr[%d]->csr=%08x\n",
925 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
926
927 /* Preserve read-only bits. */
928 mask = boot_cpu_data.fpu_msk31;
929 fcr31 = (value & ~mask) | (fcr31 & mask);
930 break;
931
932 case FPCREG_FENR:
933 if (!cpu_has_mips_r)
934 break;
935 pr_debug("%p gpr[%d]->enr=%08x\n",
936 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
937 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
938 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
939 FPU_CSR_FS;
940 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
941 break;
942
943 case FPCREG_FEXR:
944 if (!cpu_has_mips_r)
945 break;
946 pr_debug("%p gpr[%d]->exr=%08x\n",
947 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
948 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
949 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
950 break;
951
952 case FPCREG_FCCR:
953 if (!cpu_has_mips_r)
954 break;
955 pr_debug("%p gpr[%d]->ccr=%08x\n",
956 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
957 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
958 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
959 FPU_CSR_COND;
960 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
961 FPU_CSR_CONDX;
962 break;
963
964 default:
965 break;
966 }
967
968 ctx->fcr31 = fcr31;
969 }
970
971 /*
972 * Emulate the single floating point instruction pointed at by EPC.
973 * Two instructions if the instruction is in a branch delay slot.
974 */
975
cop1Emulate(struct pt_regs * xcp,struct mips_fpu_struct * ctx,struct mm_decoded_insn dec_insn,void * __user * fault_addr)976 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
977 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
978 {
979 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
980 unsigned int cond, cbit, bit0;
981 mips_instruction ir;
982 int likely, pc_inc;
983 union fpureg *fpr;
984 u32 __user *wva;
985 u64 __user *dva;
986 u32 wval;
987 u64 dval;
988 int sig;
989
990 /*
991 * These are giving gcc a gentle hint about what to expect in
992 * dec_inst in order to do better optimization.
993 */
994 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
995 unreachable();
996
997 /* XXX NEC Vr54xx bug workaround */
998 if (delay_slot(xcp)) {
999 if (dec_insn.micro_mips_mode) {
1000 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1001 clear_delay_slot(xcp);
1002 } else {
1003 if (!isBranchInstr(xcp, dec_insn, &contpc))
1004 clear_delay_slot(xcp);
1005 }
1006 }
1007
1008 if (delay_slot(xcp)) {
1009 /*
1010 * The instruction to be emulated is in a branch delay slot
1011 * which means that we have to emulate the branch instruction
1012 * BEFORE we do the cop1 instruction.
1013 *
1014 * This branch could be a COP1 branch, but in that case we
1015 * would have had a trap for that instruction, and would not
1016 * come through this route.
1017 *
1018 * Linux MIPS branch emulator operates on context, updating the
1019 * cp0_epc.
1020 */
1021 ir = dec_insn.next_insn; /* process delay slot instr */
1022 pc_inc = dec_insn.next_pc_inc;
1023 } else {
1024 ir = dec_insn.insn; /* process current instr */
1025 pc_inc = dec_insn.pc_inc;
1026 }
1027
1028 /*
1029 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1030 * instructions, we want to convert microMIPS FPU instructions
1031 * into MIPS32 instructions so that we could reuse all of the
1032 * FPU emulation code.
1033 *
1034 * NOTE: We cannot do this for branch instructions since they
1035 * are not a subset. Example: Cannot emulate a 16-bit
1036 * aligned target address with a MIPS32 instruction.
1037 */
1038 if (dec_insn.micro_mips_mode) {
1039 /*
1040 * If next instruction is a 16-bit instruction, then it
1041 * it cannot be a FPU instruction. This could happen
1042 * since we can be called for non-FPU instructions.
1043 */
1044 if ((pc_inc == 2) ||
1045 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1046 == SIGILL))
1047 return SIGILL;
1048 }
1049
1050 emul:
1051 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1052 MIPS_FPU_EMU_INC_STATS(emulated);
1053 switch (MIPSInst_OPCODE(ir)) {
1054 case ldc1_op:
1055 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1056 MIPSInst_SIMM(ir));
1057 MIPS_FPU_EMU_INC_STATS(loads);
1058
1059 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1060 MIPS_FPU_EMU_INC_STATS(errors);
1061 *fault_addr = dva;
1062 return SIGBUS;
1063 }
1064 if (__get_user(dval, dva)) {
1065 MIPS_FPU_EMU_INC_STATS(errors);
1066 *fault_addr = dva;
1067 return SIGSEGV;
1068 }
1069 DITOREG(dval, MIPSInst_RT(ir));
1070 break;
1071
1072 case sdc1_op:
1073 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1074 MIPSInst_SIMM(ir));
1075 MIPS_FPU_EMU_INC_STATS(stores);
1076 DIFROMREG(dval, MIPSInst_RT(ir));
1077 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1078 MIPS_FPU_EMU_INC_STATS(errors);
1079 *fault_addr = dva;
1080 return SIGBUS;
1081 }
1082 if (__put_user(dval, dva)) {
1083 MIPS_FPU_EMU_INC_STATS(errors);
1084 *fault_addr = dva;
1085 return SIGSEGV;
1086 }
1087 break;
1088
1089 case lwc1_op:
1090 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1091 MIPSInst_SIMM(ir));
1092 MIPS_FPU_EMU_INC_STATS(loads);
1093 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1094 MIPS_FPU_EMU_INC_STATS(errors);
1095 *fault_addr = wva;
1096 return SIGBUS;
1097 }
1098 if (__get_user(wval, wva)) {
1099 MIPS_FPU_EMU_INC_STATS(errors);
1100 *fault_addr = wva;
1101 return SIGSEGV;
1102 }
1103 SITOREG(wval, MIPSInst_RT(ir));
1104 break;
1105
1106 case swc1_op:
1107 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1108 MIPSInst_SIMM(ir));
1109 MIPS_FPU_EMU_INC_STATS(stores);
1110 SIFROMREG(wval, MIPSInst_RT(ir));
1111 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1112 MIPS_FPU_EMU_INC_STATS(errors);
1113 *fault_addr = wva;
1114 return SIGBUS;
1115 }
1116 if (__put_user(wval, wva)) {
1117 MIPS_FPU_EMU_INC_STATS(errors);
1118 *fault_addr = wva;
1119 return SIGSEGV;
1120 }
1121 break;
1122
1123 case cop1_op:
1124 switch (MIPSInst_RS(ir)) {
1125 case dmfc_op:
1126 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1127 return SIGILL;
1128
1129 /* copregister fs -> gpr[rt] */
1130 if (MIPSInst_RT(ir) != 0) {
1131 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1132 MIPSInst_RD(ir));
1133 }
1134 break;
1135
1136 case dmtc_op:
1137 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1138 return SIGILL;
1139
1140 /* copregister fs <- rt */
1141 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1142 break;
1143
1144 case mfhc_op:
1145 if (!cpu_has_mips_r2_r6)
1146 goto sigill;
1147
1148 /* copregister rd -> gpr[rt] */
1149 if (MIPSInst_RT(ir) != 0) {
1150 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1151 MIPSInst_RD(ir));
1152 }
1153 break;
1154
1155 case mthc_op:
1156 if (!cpu_has_mips_r2_r6)
1157 goto sigill;
1158
1159 /* copregister rd <- gpr[rt] */
1160 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1161 break;
1162
1163 case mfc_op:
1164 /* copregister rd -> gpr[rt] */
1165 if (MIPSInst_RT(ir) != 0) {
1166 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1167 MIPSInst_RD(ir));
1168 }
1169 break;
1170
1171 case mtc_op:
1172 /* copregister rd <- rt */
1173 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1174 break;
1175
1176 case cfc_op:
1177 /* cop control register rd -> gpr[rt] */
1178 cop1_cfc(xcp, ctx, ir);
1179 break;
1180
1181 case ctc_op:
1182 /* copregister rd <- rt */
1183 cop1_ctc(xcp, ctx, ir);
1184 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1185 return SIGFPE;
1186 }
1187 break;
1188
1189 case bc1eqz_op:
1190 case bc1nez_op:
1191 if (!cpu_has_mips_r6 || delay_slot(xcp))
1192 return SIGILL;
1193
1194 cond = likely = 0;
1195 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1196 bit0 = get_fpr32(fpr, 0) & 0x1;
1197 switch (MIPSInst_RS(ir)) {
1198 case bc1eqz_op:
1199 cond = bit0 == 0;
1200 break;
1201 case bc1nez_op:
1202 cond = bit0 != 0;
1203 break;
1204 }
1205 goto branch_common;
1206
1207 case bc_op:
1208 if (delay_slot(xcp))
1209 return SIGILL;
1210
1211 if (cpu_has_mips_4_5_r)
1212 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1213 else
1214 cbit = FPU_CSR_COND;
1215 cond = ctx->fcr31 & cbit;
1216
1217 likely = 0;
1218 switch (MIPSInst_RT(ir) & 3) {
1219 case bcfl_op:
1220 if (cpu_has_mips_2_3_4_5_r)
1221 likely = 1;
1222 /* Fall through */
1223 case bcf_op:
1224 cond = !cond;
1225 break;
1226 case bctl_op:
1227 if (cpu_has_mips_2_3_4_5_r)
1228 likely = 1;
1229 /* Fall through */
1230 case bct_op:
1231 break;
1232 }
1233 branch_common:
1234 set_delay_slot(xcp);
1235 if (cond) {
1236 /*
1237 * Branch taken: emulate dslot instruction
1238 */
1239 unsigned long bcpc;
1240
1241 /*
1242 * Remember EPC at the branch to point back
1243 * at so that any delay-slot instruction
1244 * signal is not silently ignored.
1245 */
1246 bcpc = xcp->cp0_epc;
1247 xcp->cp0_epc += dec_insn.pc_inc;
1248
1249 contpc = MIPSInst_SIMM(ir);
1250 ir = dec_insn.next_insn;
1251 if (dec_insn.micro_mips_mode) {
1252 contpc = (xcp->cp0_epc + (contpc << 1));
1253
1254 /* If 16-bit instruction, not FPU. */
1255 if ((dec_insn.next_pc_inc == 2) ||
1256 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1257
1258 /*
1259 * Since this instruction will
1260 * be put on the stack with
1261 * 32-bit words, get around
1262 * this problem by putting a
1263 * NOP16 as the second one.
1264 */
1265 if (dec_insn.next_pc_inc == 2)
1266 ir = (ir & (~0xffff)) | MM_NOP16;
1267
1268 /*
1269 * Single step the non-CP1
1270 * instruction in the dslot.
1271 */
1272 sig = mips_dsemul(xcp, ir,
1273 bcpc, contpc);
1274 if (sig < 0)
1275 break;
1276 if (sig)
1277 xcp->cp0_epc = bcpc;
1278 /*
1279 * SIGILL forces out of
1280 * the emulation loop.
1281 */
1282 return sig ? sig : SIGILL;
1283 }
1284 } else
1285 contpc = (xcp->cp0_epc + (contpc << 2));
1286
1287 switch (MIPSInst_OPCODE(ir)) {
1288 case lwc1_op:
1289 case swc1_op:
1290 goto emul;
1291
1292 case ldc1_op:
1293 case sdc1_op:
1294 if (cpu_has_mips_2_3_4_5_r)
1295 goto emul;
1296
1297 goto bc_sigill;
1298
1299 case cop1_op:
1300 goto emul;
1301
1302 case cop1x_op:
1303 if (cpu_has_mips_4_5_64_r2_r6)
1304 /* its one of ours */
1305 goto emul;
1306
1307 goto bc_sigill;
1308
1309 case spec_op:
1310 switch (MIPSInst_FUNC(ir)) {
1311 case movc_op:
1312 if (cpu_has_mips_4_5_r)
1313 goto emul;
1314
1315 goto bc_sigill;
1316 }
1317 break;
1318
1319 bc_sigill:
1320 xcp->cp0_epc = bcpc;
1321 return SIGILL;
1322 }
1323
1324 /*
1325 * Single step the non-cp1
1326 * instruction in the dslot
1327 */
1328 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1329 if (sig < 0)
1330 break;
1331 if (sig)
1332 xcp->cp0_epc = bcpc;
1333 /* SIGILL forces out of the emulation loop. */
1334 return sig ? sig : SIGILL;
1335 } else if (likely) { /* branch not taken */
1336 /*
1337 * branch likely nullifies
1338 * dslot if not taken
1339 */
1340 xcp->cp0_epc += dec_insn.pc_inc;
1341 contpc += dec_insn.pc_inc;
1342 /*
1343 * else continue & execute
1344 * dslot as normal insn
1345 */
1346 }
1347 break;
1348
1349 default:
1350 if (!(MIPSInst_RS(ir) & 0x10))
1351 return SIGILL;
1352
1353 /* a real fpu computation instruction */
1354 if ((sig = fpu_emu(xcp, ctx, ir)))
1355 return sig;
1356 }
1357 break;
1358
1359 case cop1x_op:
1360 if (!cpu_has_mips_4_5_64_r2_r6)
1361 return SIGILL;
1362
1363 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1364 if (sig)
1365 return sig;
1366 break;
1367
1368 case spec_op:
1369 if (!cpu_has_mips_4_5_r)
1370 return SIGILL;
1371
1372 if (MIPSInst_FUNC(ir) != movc_op)
1373 return SIGILL;
1374 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1375 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1376 xcp->regs[MIPSInst_RD(ir)] =
1377 xcp->regs[MIPSInst_RS(ir)];
1378 break;
1379 default:
1380 sigill:
1381 return SIGILL;
1382 }
1383
1384 /* we did it !! */
1385 xcp->cp0_epc = contpc;
1386 clear_delay_slot(xcp);
1387
1388 return 0;
1389 }
1390
1391 /*
1392 * Conversion table from MIPS compare ops 48-63
1393 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1394 */
1395 static const unsigned char cmptab[8] = {
1396 0, /* cmp_0 (sig) cmp_sf */
1397 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1398 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1399 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1400 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1401 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1402 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1403 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1404 };
1405
1406 static const unsigned char negative_cmptab[8] = {
1407 0, /* Reserved */
1408 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1409 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1410 IEEE754_CLT | IEEE754_CGT,
1411 /* Reserved */
1412 };
1413
1414
1415 /*
1416 * Additional MIPS4 instructions
1417 */
1418
1419 #define DEF3OP(name, p, f1, f2, f3) \
1420 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1421 union ieee754##p s, union ieee754##p t) \
1422 { \
1423 struct _ieee754_csr ieee754_csr_save; \
1424 s = f1(s, t); \
1425 ieee754_csr_save = ieee754_csr; \
1426 s = f2(s, r); \
1427 ieee754_csr_save.cx |= ieee754_csr.cx; \
1428 ieee754_csr_save.sx |= ieee754_csr.sx; \
1429 s = f3(s); \
1430 ieee754_csr.cx |= ieee754_csr_save.cx; \
1431 ieee754_csr.sx |= ieee754_csr_save.sx; \
1432 return s; \
1433 }
1434
fpemu_dp_recip(union ieee754dp d)1435 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1436 {
1437 return ieee754dp_div(ieee754dp_one(0), d);
1438 }
1439
fpemu_dp_rsqrt(union ieee754dp d)1440 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1441 {
1442 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1443 }
1444
fpemu_sp_recip(union ieee754sp s)1445 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1446 {
1447 return ieee754sp_div(ieee754sp_one(0), s);
1448 }
1449
fpemu_sp_rsqrt(union ieee754sp s)1450 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1451 {
1452 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1453 }
1454
1455 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1456 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1457 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1458 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1459 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1460 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1461 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1462 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1463
fpux_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir,void * __user * fault_addr)1464 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1465 mips_instruction ir, void *__user *fault_addr)
1466 {
1467 unsigned rcsr = 0; /* resulting csr */
1468
1469 MIPS_FPU_EMU_INC_STATS(cp1xops);
1470
1471 switch (MIPSInst_FMA_FFMT(ir)) {
1472 case s_fmt:{ /* 0 */
1473
1474 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1475 union ieee754sp fd, fr, fs, ft;
1476 u32 __user *va;
1477 u32 val;
1478
1479 switch (MIPSInst_FUNC(ir)) {
1480 case lwxc1_op:
1481 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1482 xcp->regs[MIPSInst_FT(ir)]);
1483
1484 MIPS_FPU_EMU_INC_STATS(loads);
1485 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1486 MIPS_FPU_EMU_INC_STATS(errors);
1487 *fault_addr = va;
1488 return SIGBUS;
1489 }
1490 if (__get_user(val, va)) {
1491 MIPS_FPU_EMU_INC_STATS(errors);
1492 *fault_addr = va;
1493 return SIGSEGV;
1494 }
1495 SITOREG(val, MIPSInst_FD(ir));
1496 break;
1497
1498 case swxc1_op:
1499 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1500 xcp->regs[MIPSInst_FT(ir)]);
1501
1502 MIPS_FPU_EMU_INC_STATS(stores);
1503
1504 SIFROMREG(val, MIPSInst_FS(ir));
1505 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1506 MIPS_FPU_EMU_INC_STATS(errors);
1507 *fault_addr = va;
1508 return SIGBUS;
1509 }
1510 if (put_user(val, va)) {
1511 MIPS_FPU_EMU_INC_STATS(errors);
1512 *fault_addr = va;
1513 return SIGSEGV;
1514 }
1515 break;
1516
1517 case madd_s_op:
1518 handler = fpemu_sp_madd;
1519 goto scoptop;
1520 case msub_s_op:
1521 handler = fpemu_sp_msub;
1522 goto scoptop;
1523 case nmadd_s_op:
1524 handler = fpemu_sp_nmadd;
1525 goto scoptop;
1526 case nmsub_s_op:
1527 handler = fpemu_sp_nmsub;
1528 goto scoptop;
1529
1530 scoptop:
1531 SPFROMREG(fr, MIPSInst_FR(ir));
1532 SPFROMREG(fs, MIPSInst_FS(ir));
1533 SPFROMREG(ft, MIPSInst_FT(ir));
1534 fd = (*handler) (fr, fs, ft);
1535 SPTOREG(fd, MIPSInst_FD(ir));
1536
1537 copcsr:
1538 if (ieee754_cxtest(IEEE754_INEXACT)) {
1539 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1540 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1541 }
1542 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1543 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1544 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1545 }
1546 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1547 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1548 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1549 }
1550 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1551 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1552 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1553 }
1554
1555 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1556 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1557 /*printk ("SIGFPE: FPU csr = %08x\n",
1558 ctx->fcr31); */
1559 return SIGFPE;
1560 }
1561
1562 break;
1563
1564 default:
1565 return SIGILL;
1566 }
1567 break;
1568 }
1569
1570 case d_fmt:{ /* 1 */
1571 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1572 union ieee754dp fd, fr, fs, ft;
1573 u64 __user *va;
1574 u64 val;
1575
1576 switch (MIPSInst_FUNC(ir)) {
1577 case ldxc1_op:
1578 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1579 xcp->regs[MIPSInst_FT(ir)]);
1580
1581 MIPS_FPU_EMU_INC_STATS(loads);
1582 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1583 MIPS_FPU_EMU_INC_STATS(errors);
1584 *fault_addr = va;
1585 return SIGBUS;
1586 }
1587 if (__get_user(val, va)) {
1588 MIPS_FPU_EMU_INC_STATS(errors);
1589 *fault_addr = va;
1590 return SIGSEGV;
1591 }
1592 DITOREG(val, MIPSInst_FD(ir));
1593 break;
1594
1595 case sdxc1_op:
1596 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1597 xcp->regs[MIPSInst_FT(ir)]);
1598
1599 MIPS_FPU_EMU_INC_STATS(stores);
1600 DIFROMREG(val, MIPSInst_FS(ir));
1601 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1602 MIPS_FPU_EMU_INC_STATS(errors);
1603 *fault_addr = va;
1604 return SIGBUS;
1605 }
1606 if (__put_user(val, va)) {
1607 MIPS_FPU_EMU_INC_STATS(errors);
1608 *fault_addr = va;
1609 return SIGSEGV;
1610 }
1611 break;
1612
1613 case madd_d_op:
1614 handler = fpemu_dp_madd;
1615 goto dcoptop;
1616 case msub_d_op:
1617 handler = fpemu_dp_msub;
1618 goto dcoptop;
1619 case nmadd_d_op:
1620 handler = fpemu_dp_nmadd;
1621 goto dcoptop;
1622 case nmsub_d_op:
1623 handler = fpemu_dp_nmsub;
1624 goto dcoptop;
1625
1626 dcoptop:
1627 DPFROMREG(fr, MIPSInst_FR(ir));
1628 DPFROMREG(fs, MIPSInst_FS(ir));
1629 DPFROMREG(ft, MIPSInst_FT(ir));
1630 fd = (*handler) (fr, fs, ft);
1631 DPTOREG(fd, MIPSInst_FD(ir));
1632 goto copcsr;
1633
1634 default:
1635 return SIGILL;
1636 }
1637 break;
1638 }
1639
1640 case 0x3:
1641 if (MIPSInst_FUNC(ir) != pfetch_op)
1642 return SIGILL;
1643
1644 /* ignore prefx operation */
1645 break;
1646
1647 default:
1648 return SIGILL;
1649 }
1650
1651 return 0;
1652 }
1653
1654
1655
1656 /*
1657 * Emulate a single COP1 arithmetic instruction.
1658 */
fpu_emu(struct pt_regs * xcp,struct mips_fpu_struct * ctx,mips_instruction ir)1659 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1660 mips_instruction ir)
1661 {
1662 int rfmt; /* resulting format */
1663 unsigned rcsr = 0; /* resulting csr */
1664 unsigned int oldrm;
1665 unsigned int cbit;
1666 unsigned cond;
1667 union {
1668 union ieee754dp d;
1669 union ieee754sp s;
1670 int w;
1671 s64 l;
1672 } rv; /* resulting value */
1673 u64 bits;
1674
1675 MIPS_FPU_EMU_INC_STATS(cp1ops);
1676 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1677 case s_fmt: { /* 0 */
1678 union {
1679 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1680 union ieee754sp(*u) (union ieee754sp);
1681 } handler;
1682 union ieee754sp fd, fs, ft;
1683
1684 switch (MIPSInst_FUNC(ir)) {
1685 /* binary ops */
1686 case fadd_op:
1687 handler.b = ieee754sp_add;
1688 goto scopbop;
1689 case fsub_op:
1690 handler.b = ieee754sp_sub;
1691 goto scopbop;
1692 case fmul_op:
1693 handler.b = ieee754sp_mul;
1694 goto scopbop;
1695 case fdiv_op:
1696 handler.b = ieee754sp_div;
1697 goto scopbop;
1698
1699 /* unary ops */
1700 case fsqrt_op:
1701 if (!cpu_has_mips_2_3_4_5_r)
1702 return SIGILL;
1703
1704 handler.u = ieee754sp_sqrt;
1705 goto scopuop;
1706
1707 /*
1708 * Note that on some MIPS IV implementations such as the
1709 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1710 * achieve full IEEE-754 accuracy - however this emulator does.
1711 */
1712 case frsqrt_op:
1713 if (!cpu_has_mips_4_5_64_r2_r6)
1714 return SIGILL;
1715
1716 handler.u = fpemu_sp_rsqrt;
1717 goto scopuop;
1718
1719 case frecip_op:
1720 if (!cpu_has_mips_4_5_64_r2_r6)
1721 return SIGILL;
1722
1723 handler.u = fpemu_sp_recip;
1724 goto scopuop;
1725
1726 case fmovc_op:
1727 if (!cpu_has_mips_4_5_r)
1728 return SIGILL;
1729
1730 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1731 if (((ctx->fcr31 & cond) != 0) !=
1732 ((MIPSInst_FT(ir) & 1) != 0))
1733 return 0;
1734 SPFROMREG(rv.s, MIPSInst_FS(ir));
1735 break;
1736
1737 case fmovz_op:
1738 if (!cpu_has_mips_4_5_r)
1739 return SIGILL;
1740
1741 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1742 return 0;
1743 SPFROMREG(rv.s, MIPSInst_FS(ir));
1744 break;
1745
1746 case fmovn_op:
1747 if (!cpu_has_mips_4_5_r)
1748 return SIGILL;
1749
1750 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1751 return 0;
1752 SPFROMREG(rv.s, MIPSInst_FS(ir));
1753 break;
1754
1755 case fseleqz_op:
1756 if (!cpu_has_mips_r6)
1757 return SIGILL;
1758
1759 SPFROMREG(rv.s, MIPSInst_FT(ir));
1760 if (rv.w & 0x1)
1761 rv.w = 0;
1762 else
1763 SPFROMREG(rv.s, MIPSInst_FS(ir));
1764 break;
1765
1766 case fselnez_op:
1767 if (!cpu_has_mips_r6)
1768 return SIGILL;
1769
1770 SPFROMREG(rv.s, MIPSInst_FT(ir));
1771 if (rv.w & 0x1)
1772 SPFROMREG(rv.s, MIPSInst_FS(ir));
1773 else
1774 rv.w = 0;
1775 break;
1776
1777 case fmaddf_op: {
1778 union ieee754sp ft, fs, fd;
1779
1780 if (!cpu_has_mips_r6)
1781 return SIGILL;
1782
1783 SPFROMREG(ft, MIPSInst_FT(ir));
1784 SPFROMREG(fs, MIPSInst_FS(ir));
1785 SPFROMREG(fd, MIPSInst_FD(ir));
1786 rv.s = ieee754sp_maddf(fd, fs, ft);
1787 break;
1788 }
1789
1790 case fmsubf_op: {
1791 union ieee754sp ft, fs, fd;
1792
1793 if (!cpu_has_mips_r6)
1794 return SIGILL;
1795
1796 SPFROMREG(ft, MIPSInst_FT(ir));
1797 SPFROMREG(fs, MIPSInst_FS(ir));
1798 SPFROMREG(fd, MIPSInst_FD(ir));
1799 rv.s = ieee754sp_msubf(fd, fs, ft);
1800 break;
1801 }
1802
1803 case frint_op: {
1804 union ieee754sp fs;
1805
1806 if (!cpu_has_mips_r6)
1807 return SIGILL;
1808
1809 SPFROMREG(fs, MIPSInst_FS(ir));
1810 rv.l = ieee754sp_tlong(fs);
1811 rv.s = ieee754sp_flong(rv.l);
1812 goto copcsr;
1813 }
1814
1815 case fclass_op: {
1816 union ieee754sp fs;
1817
1818 if (!cpu_has_mips_r6)
1819 return SIGILL;
1820
1821 SPFROMREG(fs, MIPSInst_FS(ir));
1822 rv.w = ieee754sp_2008class(fs);
1823 rfmt = w_fmt;
1824 break;
1825 }
1826
1827 case fmin_op: {
1828 union ieee754sp fs, ft;
1829
1830 if (!cpu_has_mips_r6)
1831 return SIGILL;
1832
1833 SPFROMREG(ft, MIPSInst_FT(ir));
1834 SPFROMREG(fs, MIPSInst_FS(ir));
1835 rv.s = ieee754sp_fmin(fs, ft);
1836 break;
1837 }
1838
1839 case fmina_op: {
1840 union ieee754sp fs, ft;
1841
1842 if (!cpu_has_mips_r6)
1843 return SIGILL;
1844
1845 SPFROMREG(ft, MIPSInst_FT(ir));
1846 SPFROMREG(fs, MIPSInst_FS(ir));
1847 rv.s = ieee754sp_fmina(fs, ft);
1848 break;
1849 }
1850
1851 case fmax_op: {
1852 union ieee754sp fs, ft;
1853
1854 if (!cpu_has_mips_r6)
1855 return SIGILL;
1856
1857 SPFROMREG(ft, MIPSInst_FT(ir));
1858 SPFROMREG(fs, MIPSInst_FS(ir));
1859 rv.s = ieee754sp_fmax(fs, ft);
1860 break;
1861 }
1862
1863 case fmaxa_op: {
1864 union ieee754sp fs, ft;
1865
1866 if (!cpu_has_mips_r6)
1867 return SIGILL;
1868
1869 SPFROMREG(ft, MIPSInst_FT(ir));
1870 SPFROMREG(fs, MIPSInst_FS(ir));
1871 rv.s = ieee754sp_fmaxa(fs, ft);
1872 break;
1873 }
1874
1875 case fabs_op:
1876 handler.u = ieee754sp_abs;
1877 goto scopuop;
1878
1879 case fneg_op:
1880 handler.u = ieee754sp_neg;
1881 goto scopuop;
1882
1883 case fmov_op:
1884 /* an easy one */
1885 SPFROMREG(rv.s, MIPSInst_FS(ir));
1886 goto copcsr;
1887
1888 /* binary op on handler */
1889 scopbop:
1890 SPFROMREG(fs, MIPSInst_FS(ir));
1891 SPFROMREG(ft, MIPSInst_FT(ir));
1892
1893 rv.s = (*handler.b) (fs, ft);
1894 goto copcsr;
1895 scopuop:
1896 SPFROMREG(fs, MIPSInst_FS(ir));
1897 rv.s = (*handler.u) (fs);
1898 goto copcsr;
1899 copcsr:
1900 if (ieee754_cxtest(IEEE754_INEXACT)) {
1901 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1902 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1903 }
1904 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1905 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1906 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1907 }
1908 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1909 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1910 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1911 }
1912 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1913 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1914 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1915 }
1916 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1917 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1918 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1919 }
1920 break;
1921
1922 /* unary conv ops */
1923 case fcvts_op:
1924 return SIGILL; /* not defined */
1925
1926 case fcvtd_op:
1927 SPFROMREG(fs, MIPSInst_FS(ir));
1928 rv.d = ieee754dp_fsp(fs);
1929 rfmt = d_fmt;
1930 goto copcsr;
1931
1932 case fcvtw_op:
1933 SPFROMREG(fs, MIPSInst_FS(ir));
1934 rv.w = ieee754sp_tint(fs);
1935 rfmt = w_fmt;
1936 goto copcsr;
1937
1938 case fround_op:
1939 case ftrunc_op:
1940 case fceil_op:
1941 case ffloor_op:
1942 if (!cpu_has_mips_2_3_4_5_r)
1943 return SIGILL;
1944
1945 oldrm = ieee754_csr.rm;
1946 SPFROMREG(fs, MIPSInst_FS(ir));
1947 ieee754_csr.rm = MIPSInst_FUNC(ir);
1948 rv.w = ieee754sp_tint(fs);
1949 ieee754_csr.rm = oldrm;
1950 rfmt = w_fmt;
1951 goto copcsr;
1952
1953 case fsel_op:
1954 if (!cpu_has_mips_r6)
1955 return SIGILL;
1956
1957 SPFROMREG(fd, MIPSInst_FD(ir));
1958 if (fd.bits & 0x1)
1959 SPFROMREG(rv.s, MIPSInst_FT(ir));
1960 else
1961 SPFROMREG(rv.s, MIPSInst_FS(ir));
1962 break;
1963
1964 case fcvtl_op:
1965 if (!cpu_has_mips_3_4_5_64_r2_r6)
1966 return SIGILL;
1967
1968 SPFROMREG(fs, MIPSInst_FS(ir));
1969 rv.l = ieee754sp_tlong(fs);
1970 rfmt = l_fmt;
1971 goto copcsr;
1972
1973 case froundl_op:
1974 case ftruncl_op:
1975 case fceill_op:
1976 case ffloorl_op:
1977 if (!cpu_has_mips_3_4_5_64_r2_r6)
1978 return SIGILL;
1979
1980 oldrm = ieee754_csr.rm;
1981 SPFROMREG(fs, MIPSInst_FS(ir));
1982 ieee754_csr.rm = MIPSInst_FUNC(ir);
1983 rv.l = ieee754sp_tlong(fs);
1984 ieee754_csr.rm = oldrm;
1985 rfmt = l_fmt;
1986 goto copcsr;
1987
1988 default:
1989 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1990 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1991 union ieee754sp fs, ft;
1992
1993 SPFROMREG(fs, MIPSInst_FS(ir));
1994 SPFROMREG(ft, MIPSInst_FT(ir));
1995 rv.w = ieee754sp_cmp(fs, ft,
1996 cmptab[cmpop & 0x7], cmpop & 0x8);
1997 rfmt = -1;
1998 if ((cmpop & 0x8) && ieee754_cxtest
1999 (IEEE754_INVALID_OPERATION))
2000 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2001 else
2002 goto copcsr;
2003
2004 } else
2005 return SIGILL;
2006 break;
2007 }
2008 break;
2009 }
2010
2011 case d_fmt: {
2012 union ieee754dp fd, fs, ft;
2013 union {
2014 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2015 union ieee754dp(*u) (union ieee754dp);
2016 } handler;
2017
2018 switch (MIPSInst_FUNC(ir)) {
2019 /* binary ops */
2020 case fadd_op:
2021 handler.b = ieee754dp_add;
2022 goto dcopbop;
2023 case fsub_op:
2024 handler.b = ieee754dp_sub;
2025 goto dcopbop;
2026 case fmul_op:
2027 handler.b = ieee754dp_mul;
2028 goto dcopbop;
2029 case fdiv_op:
2030 handler.b = ieee754dp_div;
2031 goto dcopbop;
2032
2033 /* unary ops */
2034 case fsqrt_op:
2035 if (!cpu_has_mips_2_3_4_5_r)
2036 return SIGILL;
2037
2038 handler.u = ieee754dp_sqrt;
2039 goto dcopuop;
2040 /*
2041 * Note that on some MIPS IV implementations such as the
2042 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2043 * achieve full IEEE-754 accuracy - however this emulator does.
2044 */
2045 case frsqrt_op:
2046 if (!cpu_has_mips_4_5_64_r2_r6)
2047 return SIGILL;
2048
2049 handler.u = fpemu_dp_rsqrt;
2050 goto dcopuop;
2051 case frecip_op:
2052 if (!cpu_has_mips_4_5_64_r2_r6)
2053 return SIGILL;
2054
2055 handler.u = fpemu_dp_recip;
2056 goto dcopuop;
2057 case fmovc_op:
2058 if (!cpu_has_mips_4_5_r)
2059 return SIGILL;
2060
2061 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2062 if (((ctx->fcr31 & cond) != 0) !=
2063 ((MIPSInst_FT(ir) & 1) != 0))
2064 return 0;
2065 DPFROMREG(rv.d, MIPSInst_FS(ir));
2066 break;
2067 case fmovz_op:
2068 if (!cpu_has_mips_4_5_r)
2069 return SIGILL;
2070
2071 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2072 return 0;
2073 DPFROMREG(rv.d, MIPSInst_FS(ir));
2074 break;
2075 case fmovn_op:
2076 if (!cpu_has_mips_4_5_r)
2077 return SIGILL;
2078
2079 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2080 return 0;
2081 DPFROMREG(rv.d, MIPSInst_FS(ir));
2082 break;
2083
2084 case fseleqz_op:
2085 if (!cpu_has_mips_r6)
2086 return SIGILL;
2087
2088 DPFROMREG(rv.d, MIPSInst_FT(ir));
2089 if (rv.l & 0x1)
2090 rv.l = 0;
2091 else
2092 DPFROMREG(rv.d, MIPSInst_FS(ir));
2093 break;
2094
2095 case fselnez_op:
2096 if (!cpu_has_mips_r6)
2097 return SIGILL;
2098
2099 DPFROMREG(rv.d, MIPSInst_FT(ir));
2100 if (rv.l & 0x1)
2101 DPFROMREG(rv.d, MIPSInst_FS(ir));
2102 else
2103 rv.l = 0;
2104 break;
2105
2106 case fmaddf_op: {
2107 union ieee754dp ft, fs, fd;
2108
2109 if (!cpu_has_mips_r6)
2110 return SIGILL;
2111
2112 DPFROMREG(ft, MIPSInst_FT(ir));
2113 DPFROMREG(fs, MIPSInst_FS(ir));
2114 DPFROMREG(fd, MIPSInst_FD(ir));
2115 rv.d = ieee754dp_maddf(fd, fs, ft);
2116 break;
2117 }
2118
2119 case fmsubf_op: {
2120 union ieee754dp ft, fs, fd;
2121
2122 if (!cpu_has_mips_r6)
2123 return SIGILL;
2124
2125 DPFROMREG(ft, MIPSInst_FT(ir));
2126 DPFROMREG(fs, MIPSInst_FS(ir));
2127 DPFROMREG(fd, MIPSInst_FD(ir));
2128 rv.d = ieee754dp_msubf(fd, fs, ft);
2129 break;
2130 }
2131
2132 case frint_op: {
2133 union ieee754dp fs;
2134
2135 if (!cpu_has_mips_r6)
2136 return SIGILL;
2137
2138 DPFROMREG(fs, MIPSInst_FS(ir));
2139 rv.l = ieee754dp_tlong(fs);
2140 rv.d = ieee754dp_flong(rv.l);
2141 goto copcsr;
2142 }
2143
2144 case fclass_op: {
2145 union ieee754dp fs;
2146
2147 if (!cpu_has_mips_r6)
2148 return SIGILL;
2149
2150 DPFROMREG(fs, MIPSInst_FS(ir));
2151 rv.w = ieee754dp_2008class(fs);
2152 rfmt = w_fmt;
2153 break;
2154 }
2155
2156 case fmin_op: {
2157 union ieee754dp fs, ft;
2158
2159 if (!cpu_has_mips_r6)
2160 return SIGILL;
2161
2162 DPFROMREG(ft, MIPSInst_FT(ir));
2163 DPFROMREG(fs, MIPSInst_FS(ir));
2164 rv.d = ieee754dp_fmin(fs, ft);
2165 break;
2166 }
2167
2168 case fmina_op: {
2169 union ieee754dp fs, ft;
2170
2171 if (!cpu_has_mips_r6)
2172 return SIGILL;
2173
2174 DPFROMREG(ft, MIPSInst_FT(ir));
2175 DPFROMREG(fs, MIPSInst_FS(ir));
2176 rv.d = ieee754dp_fmina(fs, ft);
2177 break;
2178 }
2179
2180 case fmax_op: {
2181 union ieee754dp fs, ft;
2182
2183 if (!cpu_has_mips_r6)
2184 return SIGILL;
2185
2186 DPFROMREG(ft, MIPSInst_FT(ir));
2187 DPFROMREG(fs, MIPSInst_FS(ir));
2188 rv.d = ieee754dp_fmax(fs, ft);
2189 break;
2190 }
2191
2192 case fmaxa_op: {
2193 union ieee754dp fs, ft;
2194
2195 if (!cpu_has_mips_r6)
2196 return SIGILL;
2197
2198 DPFROMREG(ft, MIPSInst_FT(ir));
2199 DPFROMREG(fs, MIPSInst_FS(ir));
2200 rv.d = ieee754dp_fmaxa(fs, ft);
2201 break;
2202 }
2203
2204 case fabs_op:
2205 handler.u = ieee754dp_abs;
2206 goto dcopuop;
2207
2208 case fneg_op:
2209 handler.u = ieee754dp_neg;
2210 goto dcopuop;
2211
2212 case fmov_op:
2213 /* an easy one */
2214 DPFROMREG(rv.d, MIPSInst_FS(ir));
2215 goto copcsr;
2216
2217 /* binary op on handler */
2218 dcopbop:
2219 DPFROMREG(fs, MIPSInst_FS(ir));
2220 DPFROMREG(ft, MIPSInst_FT(ir));
2221
2222 rv.d = (*handler.b) (fs, ft);
2223 goto copcsr;
2224 dcopuop:
2225 DPFROMREG(fs, MIPSInst_FS(ir));
2226 rv.d = (*handler.u) (fs);
2227 goto copcsr;
2228
2229 /*
2230 * unary conv ops
2231 */
2232 case fcvts_op:
2233 DPFROMREG(fs, MIPSInst_FS(ir));
2234 rv.s = ieee754sp_fdp(fs);
2235 rfmt = s_fmt;
2236 goto copcsr;
2237
2238 case fcvtd_op:
2239 return SIGILL; /* not defined */
2240
2241 case fcvtw_op:
2242 DPFROMREG(fs, MIPSInst_FS(ir));
2243 rv.w = ieee754dp_tint(fs); /* wrong */
2244 rfmt = w_fmt;
2245 goto copcsr;
2246
2247 case fround_op:
2248 case ftrunc_op:
2249 case fceil_op:
2250 case ffloor_op:
2251 if (!cpu_has_mips_2_3_4_5_r)
2252 return SIGILL;
2253
2254 oldrm = ieee754_csr.rm;
2255 DPFROMREG(fs, MIPSInst_FS(ir));
2256 ieee754_csr.rm = MIPSInst_FUNC(ir);
2257 rv.w = ieee754dp_tint(fs);
2258 ieee754_csr.rm = oldrm;
2259 rfmt = w_fmt;
2260 goto copcsr;
2261
2262 case fsel_op:
2263 if (!cpu_has_mips_r6)
2264 return SIGILL;
2265
2266 DPFROMREG(fd, MIPSInst_FD(ir));
2267 if (fd.bits & 0x1)
2268 DPFROMREG(rv.d, MIPSInst_FT(ir));
2269 else
2270 DPFROMREG(rv.d, MIPSInst_FS(ir));
2271 break;
2272
2273 case fcvtl_op:
2274 if (!cpu_has_mips_3_4_5_64_r2_r6)
2275 return SIGILL;
2276
2277 DPFROMREG(fs, MIPSInst_FS(ir));
2278 rv.l = ieee754dp_tlong(fs);
2279 rfmt = l_fmt;
2280 goto copcsr;
2281
2282 case froundl_op:
2283 case ftruncl_op:
2284 case fceill_op:
2285 case ffloorl_op:
2286 if (!cpu_has_mips_3_4_5_64_r2_r6)
2287 return SIGILL;
2288
2289 oldrm = ieee754_csr.rm;
2290 DPFROMREG(fs, MIPSInst_FS(ir));
2291 ieee754_csr.rm = MIPSInst_FUNC(ir);
2292 rv.l = ieee754dp_tlong(fs);
2293 ieee754_csr.rm = oldrm;
2294 rfmt = l_fmt;
2295 goto copcsr;
2296
2297 default:
2298 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2299 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2300 union ieee754dp fs, ft;
2301
2302 DPFROMREG(fs, MIPSInst_FS(ir));
2303 DPFROMREG(ft, MIPSInst_FT(ir));
2304 rv.w = ieee754dp_cmp(fs, ft,
2305 cmptab[cmpop & 0x7], cmpop & 0x8);
2306 rfmt = -1;
2307 if ((cmpop & 0x8)
2308 &&
2309 ieee754_cxtest
2310 (IEEE754_INVALID_OPERATION))
2311 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2312 else
2313 goto copcsr;
2314
2315 }
2316 else {
2317 return SIGILL;
2318 }
2319 break;
2320 }
2321 break;
2322 }
2323
2324 case w_fmt: {
2325 union ieee754dp fs;
2326
2327 switch (MIPSInst_FUNC(ir)) {
2328 case fcvts_op:
2329 /* convert word to single precision real */
2330 SPFROMREG(fs, MIPSInst_FS(ir));
2331 rv.s = ieee754sp_fint(fs.bits);
2332 rfmt = s_fmt;
2333 goto copcsr;
2334 case fcvtd_op:
2335 /* convert word to double precision real */
2336 SPFROMREG(fs, MIPSInst_FS(ir));
2337 rv.d = ieee754dp_fint(fs.bits);
2338 rfmt = d_fmt;
2339 goto copcsr;
2340 default: {
2341 /* Emulating the new CMP.condn.fmt R6 instruction */
2342 #define CMPOP_MASK 0x7
2343 #define SIGN_BIT (0x1 << 3)
2344 #define PREDICATE_BIT (0x1 << 4)
2345
2346 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2347 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2348 union ieee754sp fs, ft;
2349
2350 /* This is an R6 only instruction */
2351 if (!cpu_has_mips_r6 ||
2352 (MIPSInst_FUNC(ir) & 0x20))
2353 return SIGILL;
2354
2355 /* fmt is w_fmt for single precision so fix it */
2356 rfmt = s_fmt;
2357 /* default to false */
2358 rv.w = 0;
2359
2360 /* CMP.condn.S */
2361 SPFROMREG(fs, MIPSInst_FS(ir));
2362 SPFROMREG(ft, MIPSInst_FT(ir));
2363
2364 /* positive predicates */
2365 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2366 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2367 sig))
2368 rv.w = -1; /* true, all 1s */
2369 if ((sig) &&
2370 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2371 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2372 else
2373 goto copcsr;
2374 } else {
2375 /* negative predicates */
2376 switch (cmpop) {
2377 case 1:
2378 case 2:
2379 case 3:
2380 if (ieee754sp_cmp(fs, ft,
2381 negative_cmptab[cmpop],
2382 sig))
2383 rv.w = -1; /* true, all 1s */
2384 if (sig &&
2385 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2386 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2387 else
2388 goto copcsr;
2389 break;
2390 default:
2391 /* Reserved R6 ops */
2392 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2393 return SIGILL;
2394 }
2395 }
2396 break;
2397 }
2398 }
2399 }
2400
2401 case l_fmt:
2402
2403 if (!cpu_has_mips_3_4_5_64_r2_r6)
2404 return SIGILL;
2405
2406 DIFROMREG(bits, MIPSInst_FS(ir));
2407
2408 switch (MIPSInst_FUNC(ir)) {
2409 case fcvts_op:
2410 /* convert long to single precision real */
2411 rv.s = ieee754sp_flong(bits);
2412 rfmt = s_fmt;
2413 goto copcsr;
2414 case fcvtd_op:
2415 /* convert long to double precision real */
2416 rv.d = ieee754dp_flong(bits);
2417 rfmt = d_fmt;
2418 goto copcsr;
2419 default: {
2420 /* Emulating the new CMP.condn.fmt R6 instruction */
2421 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2422 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2423 union ieee754dp fs, ft;
2424
2425 if (!cpu_has_mips_r6 ||
2426 (MIPSInst_FUNC(ir) & 0x20))
2427 return SIGILL;
2428
2429 /* fmt is l_fmt for double precision so fix it */
2430 rfmt = d_fmt;
2431 /* default to false */
2432 rv.l = 0;
2433
2434 /* CMP.condn.D */
2435 DPFROMREG(fs, MIPSInst_FS(ir));
2436 DPFROMREG(ft, MIPSInst_FT(ir));
2437
2438 /* positive predicates */
2439 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2440 if (ieee754dp_cmp(fs, ft,
2441 cmptab[cmpop], sig))
2442 rv.l = -1LL; /* true, all 1s */
2443 if (sig &&
2444 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2445 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2446 else
2447 goto copcsr;
2448 } else {
2449 /* negative predicates */
2450 switch (cmpop) {
2451 case 1:
2452 case 2:
2453 case 3:
2454 if (ieee754dp_cmp(fs, ft,
2455 negative_cmptab[cmpop],
2456 sig))
2457 rv.l = -1LL; /* true, all 1s */
2458 if (sig &&
2459 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2460 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2461 else
2462 goto copcsr;
2463 break;
2464 default:
2465 /* Reserved R6 ops */
2466 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2467 return SIGILL;
2468 }
2469 }
2470 break;
2471 }
2472 }
2473 default:
2474 return SIGILL;
2475 }
2476
2477 /*
2478 * Update the fpu CSR register for this operation.
2479 * If an exception is required, generate a tidy SIGFPE exception,
2480 * without updating the result register.
2481 * Note: cause exception bits do not accumulate, they are rewritten
2482 * for each op; only the flag/sticky bits accumulate.
2483 */
2484 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2485 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2486 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2487 return SIGFPE;
2488 }
2489
2490 /*
2491 * Now we can safely write the result back to the register file.
2492 */
2493 switch (rfmt) {
2494 case -1:
2495
2496 if (cpu_has_mips_4_5_r)
2497 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2498 else
2499 cbit = FPU_CSR_COND;
2500 if (rv.w)
2501 ctx->fcr31 |= cbit;
2502 else
2503 ctx->fcr31 &= ~cbit;
2504 break;
2505
2506 case d_fmt:
2507 DPTOREG(rv.d, MIPSInst_FD(ir));
2508 break;
2509 case s_fmt:
2510 SPTOREG(rv.s, MIPSInst_FD(ir));
2511 break;
2512 case w_fmt:
2513 SITOREG(rv.w, MIPSInst_FD(ir));
2514 break;
2515 case l_fmt:
2516 if (!cpu_has_mips_3_4_5_64_r2_r6)
2517 return SIGILL;
2518
2519 DITOREG(rv.l, MIPSInst_FD(ir));
2520 break;
2521 default:
2522 return SIGILL;
2523 }
2524
2525 return 0;
2526 }
2527
2528 /*
2529 * Emulate FPU instructions.
2530 *
2531 * If we use FPU hardware, then we have been typically called to handle
2532 * an unimplemented operation, such as where an operand is a NaN or
2533 * denormalized. In that case exit the emulation loop after a single
2534 * iteration so as to let hardware execute any subsequent instructions.
2535 *
2536 * If we have no FPU hardware or it has been disabled, then continue
2537 * emulating floating-point instructions until one of these conditions
2538 * has occurred:
2539 *
2540 * - a non-FPU instruction has been encountered,
2541 *
2542 * - an attempt to emulate has ended with a signal,
2543 *
2544 * - the ISA mode has been switched.
2545 *
2546 * We need to terminate the emulation loop if we got switched to the
2547 * MIPS16 mode, whether supported or not, so that we do not attempt
2548 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2549 * Similarly if we got switched to the microMIPS mode and only the
2550 * regular MIPS mode is supported, so that we do not attempt to emulate
2551 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2552 * we got switched to the regular MIPS mode and only the microMIPS mode
2553 * is supported, so that we do not attempt to emulate a regular MIPS
2554 * instruction that should cause an Address Error exception instead.
2555 * For simplicity we always terminate upon an ISA mode switch.
2556 */
fpu_emulator_cop1Handler(struct pt_regs * xcp,struct mips_fpu_struct * ctx,int has_fpu,void * __user * fault_addr)2557 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2558 int has_fpu, void *__user *fault_addr)
2559 {
2560 unsigned long oldepc, prevepc;
2561 struct mm_decoded_insn dec_insn;
2562 u16 instr[4];
2563 u16 *instr_ptr;
2564 int sig = 0;
2565
2566 oldepc = xcp->cp0_epc;
2567 do {
2568 prevepc = xcp->cp0_epc;
2569
2570 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2571 /*
2572 * Get next 2 microMIPS instructions and convert them
2573 * into 32-bit instructions.
2574 */
2575 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2576 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2577 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2578 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2579 MIPS_FPU_EMU_INC_STATS(errors);
2580 return SIGBUS;
2581 }
2582 instr_ptr = instr;
2583
2584 /* Get first instruction. */
2585 if (mm_insn_16bit(*instr_ptr)) {
2586 /* Duplicate the half-word. */
2587 dec_insn.insn = (*instr_ptr << 16) |
2588 (*instr_ptr);
2589 /* 16-bit instruction. */
2590 dec_insn.pc_inc = 2;
2591 instr_ptr += 1;
2592 } else {
2593 dec_insn.insn = (*instr_ptr << 16) |
2594 *(instr_ptr+1);
2595 /* 32-bit instruction. */
2596 dec_insn.pc_inc = 4;
2597 instr_ptr += 2;
2598 }
2599 /* Get second instruction. */
2600 if (mm_insn_16bit(*instr_ptr)) {
2601 /* Duplicate the half-word. */
2602 dec_insn.next_insn = (*instr_ptr << 16) |
2603 (*instr_ptr);
2604 /* 16-bit instruction. */
2605 dec_insn.next_pc_inc = 2;
2606 } else {
2607 dec_insn.next_insn = (*instr_ptr << 16) |
2608 *(instr_ptr+1);
2609 /* 32-bit instruction. */
2610 dec_insn.next_pc_inc = 4;
2611 }
2612 dec_insn.micro_mips_mode = 1;
2613 } else {
2614 if ((get_user(dec_insn.insn,
2615 (mips_instruction __user *) xcp->cp0_epc)) ||
2616 (get_user(dec_insn.next_insn,
2617 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2618 MIPS_FPU_EMU_INC_STATS(errors);
2619 return SIGBUS;
2620 }
2621 dec_insn.pc_inc = 4;
2622 dec_insn.next_pc_inc = 4;
2623 dec_insn.micro_mips_mode = 0;
2624 }
2625
2626 if ((dec_insn.insn == 0) ||
2627 ((dec_insn.pc_inc == 2) &&
2628 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2629 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2630 else {
2631 /*
2632 * The 'ieee754_csr' is an alias of ctx->fcr31.
2633 * No need to copy ctx->fcr31 to ieee754_csr.
2634 */
2635 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2636 }
2637
2638 if (has_fpu)
2639 break;
2640 if (sig)
2641 break;
2642 /*
2643 * We have to check for the ISA bit explicitly here,
2644 * because `get_isa16_mode' may return 0 if support
2645 * for code compression has been globally disabled,
2646 * or otherwise we may produce the wrong signal or
2647 * even proceed successfully where we must not.
2648 */
2649 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2650 break;
2651
2652 cond_resched();
2653 } while (xcp->cp0_epc > prevepc);
2654
2655 /* SIGILL indicates a non-fpu instruction */
2656 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2657 /* but if EPC has advanced, then ignore it */
2658 sig = 0;
2659
2660 return sig;
2661 }
2662