1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/page.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/special_insns.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
32
33 /*
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
36 *
37 * Based on this we disable the IP header alignment in network drivers.
38 */
39 #define NET_IP_ALIGN 0
40
41 #define HBP_NUM 4
42 /*
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
45 */
current_text_addr(void)46 static inline void *current_text_addr(void)
47 {
48 void *pc;
49
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
51
52 return pc;
53 }
54
55 #ifdef CONFIG_X86_VSMP
56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
58 #else
59 # define ARCH_MIN_TASKALIGN 16
60 # define ARCH_MIN_MMSTRUCT_ALIGN 0
61 #endif
62
63 enum tlb_infos {
64 ENTRIES,
65 NR_INFO
66 };
67
68 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
69 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
70 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
71 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
72 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
73 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
75
76 /*
77 * CPU type and hardware bug flags. Kept separately for each CPU.
78 * Members of this structure are referenced in head.S, so think twice
79 * before touching them. [mj]
80 */
81
82 struct cpuinfo_x86 {
83 __u8 x86; /* CPU family */
84 __u8 x86_vendor; /* CPU vendor */
85 __u8 x86_model;
86 __u8 x86_mask;
87 #ifdef CONFIG_X86_32
88 char wp_works_ok; /* It doesn't on 386's */
89
90 /* Problems on some 486Dx4's and old 386's: */
91 char rfu;
92 char pad0;
93 char pad1;
94 #else
95 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
96 int x86_tlbsize;
97 #endif
98 __u8 x86_virt_bits;
99 __u8 x86_phys_bits;
100 /* CPUID returned core id bits: */
101 __u8 x86_coreid_bits;
102 /* Max extended CPUID function supported: */
103 __u32 extended_cpuid_level;
104 /* Maximum supported CPUID level, -1=no CPUID: */
105 int cpuid_level;
106 __u32 x86_capability[NCAPINTS + NBUGINTS];
107 char x86_vendor_id[16];
108 char x86_model_id[64];
109 /* in KB - valid for CPUS which support this call: */
110 int x86_cache_size;
111 int x86_cache_alignment; /* In bytes */
112 int x86_power;
113 unsigned long loops_per_jiffy;
114 /* cpuid returned max cores value: */
115 u16 x86_max_cores;
116 u16 apicid;
117 u16 initial_apicid;
118 u16 x86_clflush_size;
119 /* number of cores as seen by the OS: */
120 u16 booted_cores;
121 /* Physical processor id: */
122 u16 phys_proc_id;
123 /* Core id: */
124 u16 cpu_core_id;
125 /* Compute unit id */
126 u8 compute_unit_id;
127 /* Index into per_cpu list: */
128 u16 cpu_index;
129 u32 microcode;
130 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
131
132 #define X86_VENDOR_INTEL 0
133 #define X86_VENDOR_CYRIX 1
134 #define X86_VENDOR_AMD 2
135 #define X86_VENDOR_UMC 3
136 #define X86_VENDOR_CENTAUR 5
137 #define X86_VENDOR_TRANSMETA 7
138 #define X86_VENDOR_NSC 8
139 #define X86_VENDOR_NUM 9
140
141 #define X86_VENDOR_UNKNOWN 0xff
142
143 /*
144 * capabilities of CPUs
145 */
146 extern struct cpuinfo_x86 boot_cpu_data;
147 extern struct cpuinfo_x86 new_cpu_data;
148
149 extern struct tss_struct doublefault_tss;
150 extern __u32 cpu_caps_cleared[NCAPINTS];
151 extern __u32 cpu_caps_set[NCAPINTS];
152
153 #ifdef CONFIG_SMP
154 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
155 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
156 #else
157 #define cpu_info boot_cpu_data
158 #define cpu_data(cpu) boot_cpu_data
159 #endif
160
161 extern const struct seq_operations cpuinfo_op;
162
163 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
164
165 extern void cpu_detect(struct cpuinfo_x86 *c);
166 extern void fpu_detect(struct cpuinfo_x86 *c);
167
168 extern void early_cpu_init(void);
169 extern void identify_boot_cpu(void);
170 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
171 extern void print_cpu_info(struct cpuinfo_x86 *);
172 void print_cpu_msr(struct cpuinfo_x86 *);
173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
176
177 extern void detect_extended_topology(struct cpuinfo_x86 *c);
178 extern void detect_ht(struct cpuinfo_x86 *c);
179
180 #ifdef CONFIG_X86_32
181 extern int have_cpuid_p(void);
182 #else
have_cpuid_p(void)183 static inline int have_cpuid_p(void)
184 {
185 return 1;
186 }
187 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
189 unsigned int *ecx, unsigned int *edx)
190 {
191 /* ecx is often an input as well as an output. */
192 asm volatile("cpuid"
193 : "=a" (*eax),
194 "=b" (*ebx),
195 "=c" (*ecx),
196 "=d" (*edx)
197 : "0" (*eax), "2" (*ecx)
198 : "memory");
199 }
200
load_cr3(pgd_t * pgdir)201 static inline void load_cr3(pgd_t *pgdir)
202 {
203 write_cr3(__pa(pgdir));
204 }
205
206 #ifdef CONFIG_X86_32
207 /* This is the TSS defined by the hardware. */
208 struct x86_hw_tss {
209 unsigned short back_link, __blh;
210 unsigned long sp0;
211 unsigned short ss0, __ss0h;
212 unsigned long sp1;
213 /* ss1 caches MSR_IA32_SYSENTER_CS: */
214 unsigned short ss1, __ss1h;
215 unsigned long sp2;
216 unsigned short ss2, __ss2h;
217 unsigned long __cr3;
218 unsigned long ip;
219 unsigned long flags;
220 unsigned long ax;
221 unsigned long cx;
222 unsigned long dx;
223 unsigned long bx;
224 unsigned long sp;
225 unsigned long bp;
226 unsigned long si;
227 unsigned long di;
228 unsigned short es, __esh;
229 unsigned short cs, __csh;
230 unsigned short ss, __ssh;
231 unsigned short ds, __dsh;
232 unsigned short fs, __fsh;
233 unsigned short gs, __gsh;
234 unsigned short ldt, __ldth;
235 unsigned short trace;
236 unsigned short io_bitmap_base;
237
238 } __attribute__((packed));
239 #else
240 struct x86_hw_tss {
241 u32 reserved1;
242 u64 sp0;
243 u64 sp1;
244 u64 sp2;
245 u64 reserved2;
246 u64 ist[7];
247 u32 reserved3;
248 u32 reserved4;
249 u16 reserved5;
250 u16 io_bitmap_base;
251
252 } __attribute__((packed)) ____cacheline_aligned;
253 #endif
254
255 /*
256 * IO-bitmap sizes:
257 */
258 #define IO_BITMAP_BITS 65536
259 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
260 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
261 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
262 #define INVALID_IO_BITMAP_OFFSET 0x8000
263
264 struct tss_struct {
265 /*
266 * The hardware state:
267 */
268 struct x86_hw_tss x86_tss;
269
270 /*
271 * The extra 1 is there because the CPU will access an
272 * additional byte beyond the end of the IO permission
273 * bitmap. The extra byte must be all 1 bits, and must
274 * be within the limit.
275 */
276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
277
278 /*
279 * .. and then another 0x100 bytes for the emergency kernel stack:
280 */
281 unsigned long stack[64];
282
283 } ____cacheline_aligned;
284
285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
286
287 /*
288 * Save the original ist values for checking stack pointers during debugging
289 */
290 struct orig_ist {
291 unsigned long ist[7];
292 };
293
294 #define MXCSR_DEFAULT 0x1f80
295
296 struct i387_fsave_struct {
297 u32 cwd; /* FPU Control Word */
298 u32 swd; /* FPU Status Word */
299 u32 twd; /* FPU Tag Word */
300 u32 fip; /* FPU IP Offset */
301 u32 fcs; /* FPU IP Selector */
302 u32 foo; /* FPU Operand Pointer Offset */
303 u32 fos; /* FPU Operand Pointer Selector */
304
305 /* 8*10 bytes for each FP-reg = 80 bytes: */
306 u32 st_space[20];
307
308 /* Software status information [not touched by FSAVE ]: */
309 u32 status;
310 };
311
312 struct i387_fxsave_struct {
313 u16 cwd; /* Control Word */
314 u16 swd; /* Status Word */
315 u16 twd; /* Tag Word */
316 u16 fop; /* Last Instruction Opcode */
317 union {
318 struct {
319 u64 rip; /* Instruction Pointer */
320 u64 rdp; /* Data Pointer */
321 };
322 struct {
323 u32 fip; /* FPU IP Offset */
324 u32 fcs; /* FPU IP Selector */
325 u32 foo; /* FPU Operand Offset */
326 u32 fos; /* FPU Operand Selector */
327 };
328 };
329 u32 mxcsr; /* MXCSR Register State */
330 u32 mxcsr_mask; /* MXCSR Mask */
331
332 /* 8*16 bytes for each FP-reg = 128 bytes: */
333 u32 st_space[32];
334
335 /* 16*16 bytes for each XMM-reg = 256 bytes: */
336 u32 xmm_space[64];
337
338 u32 padding[12];
339
340 union {
341 u32 padding1[12];
342 u32 sw_reserved[12];
343 };
344
345 } __attribute__((aligned(16)));
346
347 struct i387_soft_struct {
348 u32 cwd;
349 u32 swd;
350 u32 twd;
351 u32 fip;
352 u32 fcs;
353 u32 foo;
354 u32 fos;
355 /* 8*10 bytes for each FP-reg = 80 bytes: */
356 u32 st_space[20];
357 u8 ftop;
358 u8 changed;
359 u8 lookahead;
360 u8 no_update;
361 u8 rm;
362 u8 alimit;
363 struct math_emu_info *info;
364 u32 entry_eip;
365 };
366
367 struct ymmh_struct {
368 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
369 u32 ymmh_space[64];
370 };
371
372 /* We don't support LWP yet: */
373 struct lwp_struct {
374 u8 reserved[128];
375 };
376
377 struct bndregs_struct {
378 u64 bndregs[8];
379 } __packed;
380
381 struct bndcsr_struct {
382 u64 cfg_reg_u;
383 u64 status_reg;
384 } __packed;
385
386 struct xsave_hdr_struct {
387 u64 xstate_bv;
388 u64 xcomp_bv;
389 u64 reserved[6];
390 } __attribute__((packed));
391
392 struct xsave_struct {
393 struct i387_fxsave_struct i387;
394 struct xsave_hdr_struct xsave_hdr;
395 struct ymmh_struct ymmh;
396 struct lwp_struct lwp;
397 struct bndregs_struct bndregs;
398 struct bndcsr_struct bndcsr;
399 /* new processor state extensions will go here */
400 } __attribute__ ((packed, aligned (64)));
401
402 union thread_xstate {
403 struct i387_fsave_struct fsave;
404 struct i387_fxsave_struct fxsave;
405 struct i387_soft_struct soft;
406 struct xsave_struct xsave;
407 };
408
409 struct fpu {
410 unsigned int last_cpu;
411 unsigned int has_fpu;
412 union thread_xstate *state;
413 };
414
415 #ifdef CONFIG_X86_64
416 DECLARE_PER_CPU(struct orig_ist, orig_ist);
417
418 union irq_stack_union {
419 char irq_stack[IRQ_STACK_SIZE];
420 /*
421 * GCC hardcodes the stack canary as %gs:40. Since the
422 * irq_stack is the object at %gs:0, we reserve the bottom
423 * 48 bytes of the irq stack for the canary.
424 */
425 struct {
426 char gs_base[40];
427 unsigned long stack_canary;
428 };
429 };
430
431 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
432 DECLARE_INIT_PER_CPU(irq_stack_union);
433
434 DECLARE_PER_CPU(char *, irq_stack_ptr);
435 DECLARE_PER_CPU(unsigned int, irq_count);
436 extern asmlinkage void ignore_sysret(void);
437 #else /* X86_64 */
438 #ifdef CONFIG_CC_STACKPROTECTOR
439 /*
440 * Make sure stack canary segment base is cached-aligned:
441 * "For Intel Atom processors, avoid non zero segment base address
442 * that is not aligned to cache line boundary at all cost."
443 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
444 */
445 struct stack_canary {
446 char __pad[20]; /* canary at %gs:20 */
447 unsigned long canary;
448 };
449 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
450 #endif
451 /*
452 * per-CPU IRQ handling stacks
453 */
454 struct irq_stack {
455 u32 stack[THREAD_SIZE/sizeof(u32)];
456 } __aligned(THREAD_SIZE);
457
458 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
459 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
460 #endif /* X86_64 */
461
462 extern unsigned int xstate_size;
463 extern void free_thread_xstate(struct task_struct *);
464 extern struct kmem_cache *task_xstate_cachep;
465
466 struct perf_event;
467
468 struct thread_struct {
469 /* Cached TLS descriptors: */
470 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
471 unsigned long sp0;
472 unsigned long sp;
473 #ifdef CONFIG_X86_32
474 unsigned long sysenter_cs;
475 #else
476 unsigned long usersp; /* Copy from PDA */
477 unsigned short es;
478 unsigned short ds;
479 unsigned short fsindex;
480 unsigned short gsindex;
481 #endif
482 #ifdef CONFIG_X86_32
483 unsigned long ip;
484 #endif
485 #ifdef CONFIG_X86_64
486 unsigned long fs;
487 #endif
488 unsigned long gs;
489 /* Save middle states of ptrace breakpoints */
490 struct perf_event *ptrace_bps[HBP_NUM];
491 /* Debug status used for traps, single steps, etc... */
492 unsigned long debugreg6;
493 /* Keep track of the exact dr7 value set by the user */
494 unsigned long ptrace_dr7;
495 /* Fault info: */
496 unsigned long cr2;
497 unsigned long trap_nr;
498 unsigned long error_code;
499 /* floating point and extended processor state */
500 struct fpu fpu;
501 #ifdef CONFIG_X86_32
502 /* Virtual 86 mode info */
503 struct vm86_struct __user *vm86_info;
504 unsigned long screen_bitmap;
505 unsigned long v86flags;
506 unsigned long v86mask;
507 unsigned long saved_sp0;
508 unsigned int saved_fs;
509 unsigned int saved_gs;
510 #endif
511 /* IO permissions: */
512 unsigned long *io_bitmap_ptr;
513 unsigned long iopl;
514 /* Max allowed port in the bitmap, in bytes: */
515 unsigned io_bitmap_max;
516 /*
517 * fpu_counter contains the number of consecutive context switches
518 * that the FPU is used. If this is over a threshold, the lazy fpu
519 * saving becomes unlazy to save the trap. This is an unsigned char
520 * so that after 256 times the counter wraps and the behavior turns
521 * lazy again; this to deal with bursty apps that only use FPU for
522 * a short time
523 */
524 unsigned char fpu_counter;
525 };
526
527 /*
528 * Set IOPL bits in EFLAGS from given mask
529 */
native_set_iopl_mask(unsigned mask)530 static inline void native_set_iopl_mask(unsigned mask)
531 {
532 #ifdef CONFIG_X86_32
533 unsigned int reg;
534
535 asm volatile ("pushfl;"
536 "popl %0;"
537 "andl %1, %0;"
538 "orl %2, %0;"
539 "pushl %0;"
540 "popfl"
541 : "=&r" (reg)
542 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
543 #endif
544 }
545
546 static inline void
native_load_sp0(struct tss_struct * tss,struct thread_struct * thread)547 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
548 {
549 tss->x86_tss.sp0 = thread->sp0;
550 #ifdef CONFIG_X86_32
551 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
552 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
553 tss->x86_tss.ss1 = thread->sysenter_cs;
554 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
555 }
556 #endif
557 }
558
native_swapgs(void)559 static inline void native_swapgs(void)
560 {
561 #ifdef CONFIG_X86_64
562 asm volatile("swapgs" ::: "memory");
563 #endif
564 }
565
566 #ifdef CONFIG_PARAVIRT
567 #include <asm/paravirt.h>
568 #else
569 #define __cpuid native_cpuid
570 #define paravirt_enabled() 0
571
load_sp0(struct tss_struct * tss,struct thread_struct * thread)572 static inline void load_sp0(struct tss_struct *tss,
573 struct thread_struct *thread)
574 {
575 native_load_sp0(tss, thread);
576 }
577
578 #define set_iopl_mask native_set_iopl_mask
579 #endif /* CONFIG_PARAVIRT */
580
581 typedef struct {
582 unsigned long seg;
583 } mm_segment_t;
584
585
586 /* Free all resources held by a thread. */
587 extern void release_thread(struct task_struct *);
588
589 unsigned long get_wchan(struct task_struct *p);
590
591 /*
592 * Generic CPUID function
593 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
594 * resulting in stale register contents being returned.
595 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)596 static inline void cpuid(unsigned int op,
597 unsigned int *eax, unsigned int *ebx,
598 unsigned int *ecx, unsigned int *edx)
599 {
600 *eax = op;
601 *ecx = 0;
602 __cpuid(eax, ebx, ecx, edx);
603 }
604
605 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)606 static inline void cpuid_count(unsigned int op, int count,
607 unsigned int *eax, unsigned int *ebx,
608 unsigned int *ecx, unsigned int *edx)
609 {
610 *eax = op;
611 *ecx = count;
612 __cpuid(eax, ebx, ecx, edx);
613 }
614
615 /*
616 * CPUID functions returning a single datum
617 */
cpuid_eax(unsigned int op)618 static inline unsigned int cpuid_eax(unsigned int op)
619 {
620 unsigned int eax, ebx, ecx, edx;
621
622 cpuid(op, &eax, &ebx, &ecx, &edx);
623
624 return eax;
625 }
626
cpuid_ebx(unsigned int op)627 static inline unsigned int cpuid_ebx(unsigned int op)
628 {
629 unsigned int eax, ebx, ecx, edx;
630
631 cpuid(op, &eax, &ebx, &ecx, &edx);
632
633 return ebx;
634 }
635
cpuid_ecx(unsigned int op)636 static inline unsigned int cpuid_ecx(unsigned int op)
637 {
638 unsigned int eax, ebx, ecx, edx;
639
640 cpuid(op, &eax, &ebx, &ecx, &edx);
641
642 return ecx;
643 }
644
cpuid_edx(unsigned int op)645 static inline unsigned int cpuid_edx(unsigned int op)
646 {
647 unsigned int eax, ebx, ecx, edx;
648
649 cpuid(op, &eax, &ebx, &ecx, &edx);
650
651 return edx;
652 }
653
654 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
rep_nop(void)655 static inline void rep_nop(void)
656 {
657 asm volatile("rep; nop" ::: "memory");
658 }
659
cpu_relax(void)660 static inline void cpu_relax(void)
661 {
662 rep_nop();
663 }
664
665 #define cpu_relax_lowlatency() cpu_relax()
666
667 /* Stop speculative execution and prefetching of modified code. */
sync_core(void)668 static inline void sync_core(void)
669 {
670 int tmp;
671
672 #ifdef CONFIG_X86_32
673 /*
674 * Do a CPUID if available, otherwise do a jump. The jump
675 * can conveniently enough be the jump around CPUID.
676 */
677 asm volatile("cmpl %2,%1\n\t"
678 "jl 1f\n\t"
679 "cpuid\n"
680 "1:"
681 : "=a" (tmp)
682 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
683 : "ebx", "ecx", "edx", "memory");
684 #else
685 /*
686 * CPUID is a barrier to speculative execution.
687 * Prefetched instructions are automatically
688 * invalidated when modified.
689 */
690 asm volatile("cpuid"
691 : "=a" (tmp)
692 : "0" (1)
693 : "ebx", "ecx", "edx", "memory");
694 #endif
695 }
696
697 extern void select_idle_routine(const struct cpuinfo_x86 *c);
698 extern void init_amd_e400_c1e_mask(void);
699
700 extern unsigned long boot_option_idle_override;
701 extern bool amd_e400_c1e_detected;
702
703 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
704 IDLE_POLL};
705
706 extern void enable_sep_cpu(void);
707 extern int sysenter_setup(void);
708
709 extern void early_trap_init(void);
710 void early_trap_pf_init(void);
711
712 /* Defined in head.S */
713 extern struct desc_ptr early_gdt_descr;
714
715 extern void cpu_set_gdt(int);
716 extern void switch_to_new_gdt(int);
717 extern void load_percpu_segment(int);
718 extern void cpu_init(void);
719
get_debugctlmsr(void)720 static inline unsigned long get_debugctlmsr(void)
721 {
722 unsigned long debugctlmsr = 0;
723
724 #ifndef CONFIG_X86_DEBUGCTLMSR
725 if (boot_cpu_data.x86 < 6)
726 return 0;
727 #endif
728 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
729
730 return debugctlmsr;
731 }
732
update_debugctlmsr(unsigned long debugctlmsr)733 static inline void update_debugctlmsr(unsigned long debugctlmsr)
734 {
735 #ifndef CONFIG_X86_DEBUGCTLMSR
736 if (boot_cpu_data.x86 < 6)
737 return;
738 #endif
739 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
740 }
741
742 extern void set_task_blockstep(struct task_struct *task, bool on);
743
744 /*
745 * from system description table in BIOS. Mostly for MCA use, but
746 * others may find it useful:
747 */
748 extern unsigned int machine_id;
749 extern unsigned int machine_submodel_id;
750 extern unsigned int BIOS_revision;
751
752 /* Boot loader type from the setup header: */
753 extern int bootloader_type;
754 extern int bootloader_version;
755
756 extern char ignore_fpu_irq;
757
758 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
759 #define ARCH_HAS_PREFETCHW
760 #define ARCH_HAS_SPINLOCK_PREFETCH
761
762 #ifdef CONFIG_X86_32
763 # define BASE_PREFETCH ASM_NOP4
764 # define ARCH_HAS_PREFETCH
765 #else
766 # define BASE_PREFETCH "prefetcht0 (%1)"
767 #endif
768
769 /*
770 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
771 *
772 * It's not worth to care about 3dnow prefetches for the K6
773 * because they are microcoded there and very slow.
774 */
prefetch(const void * x)775 static inline void prefetch(const void *x)
776 {
777 alternative_input(BASE_PREFETCH,
778 "prefetchnta (%1)",
779 X86_FEATURE_XMM,
780 "r" (x));
781 }
782
783 /*
784 * 3dnow prefetch to get an exclusive cache line.
785 * Useful for spinlocks to avoid one state transition in the
786 * cache coherency protocol:
787 */
prefetchw(const void * x)788 static inline void prefetchw(const void *x)
789 {
790 alternative_input(BASE_PREFETCH,
791 "prefetchw (%1)",
792 X86_FEATURE_3DNOW,
793 "r" (x));
794 }
795
spin_lock_prefetch(const void * x)796 static inline void spin_lock_prefetch(const void *x)
797 {
798 prefetchw(x);
799 }
800
801 #ifdef CONFIG_X86_32
802 /*
803 * User space process size: 3GB (default).
804 */
805 #define TASK_SIZE PAGE_OFFSET
806 #define TASK_SIZE_MAX TASK_SIZE
807 #define STACK_TOP TASK_SIZE
808 #define STACK_TOP_MAX STACK_TOP
809
810 #define INIT_THREAD { \
811 .sp0 = sizeof(init_stack) + (long)&init_stack, \
812 .vm86_info = NULL, \
813 .sysenter_cs = __KERNEL_CS, \
814 .io_bitmap_ptr = NULL, \
815 }
816
817 /*
818 * Note that the .io_bitmap member must be extra-big. This is because
819 * the CPU will access an additional byte beyond the end of the IO
820 * permission bitmap. The extra byte must be all 1 bits, and must
821 * be within the limit.
822 */
823 #define INIT_TSS { \
824 .x86_tss = { \
825 .sp0 = sizeof(init_stack) + (long)&init_stack, \
826 .ss0 = __KERNEL_DS, \
827 .ss1 = __KERNEL_CS, \
828 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
829 }, \
830 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
831 }
832
833 extern unsigned long thread_saved_pc(struct task_struct *tsk);
834
835 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
836 #define KSTK_TOP(info) \
837 ({ \
838 unsigned long *__ptr = (unsigned long *)(info); \
839 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
840 })
841
842 /*
843 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
844 * This is necessary to guarantee that the entire "struct pt_regs"
845 * is accessible even if the CPU haven't stored the SS/ESP registers
846 * on the stack (interrupt gate does not save these registers
847 * when switching to the same priv ring).
848 * Therefore beware: accessing the ss/esp fields of the
849 * "struct pt_regs" is possible, but they may contain the
850 * completely wrong values.
851 */
852 #define task_pt_regs(task) \
853 ({ \
854 struct pt_regs *__regs__; \
855 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task)) - \
856 TOP_OF_KERNEL_STACK_PADDING); \
857 __regs__ - 1; \
858 })
859
860 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
861
862 #else
863 /*
864 * User space process size. 47bits minus one guard page.
865 */
866 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
867
868 /* This decides where the kernel will search for a free chunk of vm
869 * space during mmap's.
870 */
871 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
872 0xc0000000 : 0xFFFFe000)
873
874 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
875 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
876 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
877 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
878
879 #define STACK_TOP TASK_SIZE
880 #define STACK_TOP_MAX TASK_SIZE_MAX
881
882 #define INIT_THREAD { \
883 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
884 }
885
886 #define INIT_TSS { \
887 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
888 }
889
890 /*
891 * Return saved PC of a blocked thread.
892 * What is this good for? it will be always the scheduler or ret_from_fork.
893 */
894 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
895
896 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
897 extern unsigned long KSTK_ESP(struct task_struct *task);
898
899 /*
900 * User space RSP while inside the SYSCALL fast path
901 */
902 DECLARE_PER_CPU(unsigned long, old_rsp);
903
904 #endif /* CONFIG_X86_64 */
905
906 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
907 unsigned long new_sp);
908
909 /*
910 * This decides where the kernel will search for a free chunk of vm
911 * space during mmap's.
912 */
913 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
914
915 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
916
917 /* Get/set a process' ability to use the timestamp counter instruction */
918 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
919 #define SET_TSC_CTL(val) set_tsc_mode((val))
920
921 extern int get_tsc_mode(unsigned long adr);
922 extern int set_tsc_mode(unsigned int val);
923
924 extern u16 amd_get_nb_id(int cpu);
925
hypervisor_cpuid_base(const char * sig,uint32_t leaves)926 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
927 {
928 uint32_t base, eax, signature[3];
929
930 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
931 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
932
933 if (!memcmp(sig, signature, 12) &&
934 (leaves == 0 || ((eax - base) >= leaves)))
935 return base;
936 }
937
938 return 0;
939 }
940
941 extern unsigned long arch_align_stack(unsigned long sp);
942 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
943
944 void default_idle(void);
945 #ifdef CONFIG_XEN
946 bool xen_set_default_idle(void);
947 #else
948 #define xen_set_default_idle 0
949 #endif
950
951 void stop_this_cpu(void *dummy);
952 void df_debug(struct pt_regs *regs, long error_code);
953 #endif /* _ASM_X86_PROCESSOR_H */
954