1 #ifndef MDP5_XML
2 #define MDP5_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21
22 Copyright (C) 2013-2014 by the following authors:
23 - Rob Clark <robdclark@gmail.com> (robclark)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum mdp5_intf {
48 INTF_DSI = 1,
49 INTF_HDMI = 3,
50 INTF_LCDC = 5,
51 INTF_eDP = 9,
52 };
53
54 enum mdp5_intfnum {
55 NO_INTF = 0,
56 INTF0 = 1,
57 INTF1 = 2,
58 INTF2 = 3,
59 INTF3 = 4,
60 };
61
62 enum mdp5_pipe {
63 SSPP_VIG0 = 0,
64 SSPP_VIG1 = 1,
65 SSPP_VIG2 = 2,
66 SSPP_RGB0 = 3,
67 SSPP_RGB1 = 4,
68 SSPP_RGB2 = 5,
69 SSPP_DMA0 = 6,
70 SSPP_DMA1 = 7,
71 SSPP_VIG3 = 8,
72 SSPP_RGB3 = 9,
73 };
74
75 enum mdp5_ctl_mode {
76 MODE_NONE = 0,
77 MODE_ROT0 = 1,
78 MODE_ROT1 = 2,
79 MODE_WB0 = 3,
80 MODE_WB1 = 4,
81 MODE_WFD = 5,
82 };
83
84 enum mdp5_pack_3d {
85 PACK_3D_FRAME_INT = 0,
86 PACK_3D_H_ROW_INT = 1,
87 PACK_3D_V_ROW_INT = 2,
88 PACK_3D_COL_INT = 3,
89 };
90
91 enum mdp5_chroma_samp_type {
92 CHROMA_RGB = 0,
93 CHROMA_H2V1 = 1,
94 CHROMA_H1V2 = 2,
95 CHROMA_420 = 3,
96 };
97
98 enum mdp5_scale_filter {
99 SCALE_FILTER_NEAREST = 0,
100 SCALE_FILTER_BIL = 1,
101 SCALE_FILTER_PCMN = 2,
102 SCALE_FILTER_CA = 3,
103 };
104
105 enum mdp5_pipe_bwc {
106 BWC_LOSSLESS = 0,
107 BWC_Q_HIGH = 1,
108 BWC_Q_MED = 2,
109 };
110
111 enum mdp5_client_id {
112 CID_UNUSED = 0,
113 CID_VIG0_Y = 1,
114 CID_VIG0_CR = 2,
115 CID_VIG0_CB = 3,
116 CID_VIG1_Y = 4,
117 CID_VIG1_CR = 5,
118 CID_VIG1_CB = 6,
119 CID_VIG2_Y = 7,
120 CID_VIG2_CR = 8,
121 CID_VIG2_CB = 9,
122 CID_DMA0_Y = 10,
123 CID_DMA0_CR = 11,
124 CID_DMA0_CB = 12,
125 CID_DMA1_Y = 13,
126 CID_DMA1_CR = 14,
127 CID_DMA1_CB = 15,
128 CID_RGB0 = 16,
129 CID_RGB1 = 17,
130 CID_RGB2 = 18,
131 CID_VIG3_Y = 19,
132 CID_VIG3_CR = 20,
133 CID_VIG3_CB = 21,
134 CID_RGB3 = 22,
135 CID_MAX = 23,
136 };
137
138 enum mdp5_igc_type {
139 IGC_VIG = 0,
140 IGC_RGB = 1,
141 IGC_DMA = 2,
142 IGC_DSPP = 3,
143 };
144
145 #define MDP5_IRQ_INTF0_WB_ROT_COMP 0x00000001
146 #define MDP5_IRQ_INTF1_WB_ROT_COMP 0x00000002
147 #define MDP5_IRQ_INTF2_WB_ROT_COMP 0x00000004
148 #define MDP5_IRQ_INTF3_WB_ROT_COMP 0x00000008
149 #define MDP5_IRQ_INTF0_WB_WFD 0x00000010
150 #define MDP5_IRQ_INTF1_WB_WFD 0x00000020
151 #define MDP5_IRQ_INTF2_WB_WFD 0x00000040
152 #define MDP5_IRQ_INTF3_WB_WFD 0x00000080
153 #define MDP5_IRQ_INTF0_PING_PONG_COMP 0x00000100
154 #define MDP5_IRQ_INTF1_PING_PONG_COMP 0x00000200
155 #define MDP5_IRQ_INTF2_PING_PONG_COMP 0x00000400
156 #define MDP5_IRQ_INTF3_PING_PONG_COMP 0x00000800
157 #define MDP5_IRQ_INTF0_PING_PONG_RD_PTR 0x00001000
158 #define MDP5_IRQ_INTF1_PING_PONG_RD_PTR 0x00002000
159 #define MDP5_IRQ_INTF2_PING_PONG_RD_PTR 0x00004000
160 #define MDP5_IRQ_INTF3_PING_PONG_RD_PTR 0x00008000
161 #define MDP5_IRQ_INTF0_PING_PONG_WR_PTR 0x00010000
162 #define MDP5_IRQ_INTF1_PING_PONG_WR_PTR 0x00020000
163 #define MDP5_IRQ_INTF2_PING_PONG_WR_PTR 0x00040000
164 #define MDP5_IRQ_INTF3_PING_PONG_WR_PTR 0x00080000
165 #define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF 0x00100000
166 #define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF 0x00200000
167 #define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF 0x00400000
168 #define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF 0x00800000
169 #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
170 #define MDP5_IRQ_INTF0_VSYNC 0x02000000
171 #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
172 #define MDP5_IRQ_INTF1_VSYNC 0x08000000
173 #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
174 #define MDP5_IRQ_INTF2_VSYNC 0x20000000
175 #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
176 #define MDP5_IRQ_INTF3_VSYNC 0x80000000
177 #define REG_MDP5_HW_VERSION 0x00000000
178
179 #define REG_MDP5_HW_INTR_STATUS 0x00000010
180 #define MDP5_HW_INTR_STATUS_INTR_MDP 0x00000001
181 #define MDP5_HW_INTR_STATUS_INTR_DSI0 0x00000010
182 #define MDP5_HW_INTR_STATUS_INTR_DSI1 0x00000020
183 #define MDP5_HW_INTR_STATUS_INTR_HDMI 0x00000100
184 #define MDP5_HW_INTR_STATUS_INTR_EDP 0x00001000
185
186 #define REG_MDP5_MDP_VERSION 0x00000100
187 #define MDP5_MDP_VERSION_MINOR__MASK 0x00ff0000
188 #define MDP5_MDP_VERSION_MINOR__SHIFT 16
MDP5_MDP_VERSION_MINOR(uint32_t val)189 static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
190 {
191 return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK;
192 }
193 #define MDP5_MDP_VERSION_MAJOR__MASK 0xf0000000
194 #define MDP5_MDP_VERSION_MAJOR__SHIFT 28
MDP5_MDP_VERSION_MAJOR(uint32_t val)195 static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val)
196 {
197 return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK;
198 }
199
200 #define REG_MDP5_DISP_INTF_SEL 0x00000104
201 #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
202 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)203 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)
204 {
205 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
206 }
207 #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
208 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)209 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)
210 {
211 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
212 }
213 #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
214 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)215 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)
216 {
217 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
218 }
219 #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
220 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)221 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)
222 {
223 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
224 }
225
226 #define REG_MDP5_INTR_EN 0x00000110
227
228 #define REG_MDP5_INTR_STATUS 0x00000114
229
230 #define REG_MDP5_INTR_CLEAR 0x00000118
231
232 #define REG_MDP5_HIST_INTR_EN 0x0000011c
233
234 #define REG_MDP5_HIST_INTR_STATUS 0x00000120
235
236 #define REG_MDP5_HIST_INTR_CLEAR 0x00000124
237
REG_MDP5_SMP_ALLOC_W(uint32_t i0)238 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }
239
REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0)240 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; }
241 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
242 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)243 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
244 {
245 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
246 }
247 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
248 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)249 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
250 {
251 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
252 }
253 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
254 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)255 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
256 {
257 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
258 }
259
REG_MDP5_SMP_ALLOC_R(uint32_t i0)260 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; }
261
REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0)262 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; }
263 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
264 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)265 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
266 {
267 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
268 }
269 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
270 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)271 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
272 {
273 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
274 }
275 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
276 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)277 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
278 {
279 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
280 }
281
__offset_IGC(enum mdp5_igc_type idx)282 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
283 {
284 switch (idx) {
285 case IGC_VIG: return 0x00000300;
286 case IGC_RGB: return 0x00000310;
287 case IGC_DMA: return 0x00000320;
288 case IGC_DSPP: return 0x00000400;
289 default: return INVALID_IDX(idx);
290 }
291 }
REG_MDP5_IGC(enum mdp5_igc_type i0)292 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
293
REG_MDP5_IGC_LUT(enum mdp5_igc_type i0,uint32_t i1)294 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
295
REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0,uint32_t i1)296 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
297 #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
298 #define MDP5_IGC_LUT_REG_VAL__SHIFT 0
MDP5_IGC_LUT_REG_VAL(uint32_t val)299 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
300 {
301 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
302 }
303 #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
304 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
305 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
306 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
307
__offset_CTL(uint32_t idx)308 static inline uint32_t __offset_CTL(uint32_t idx)
309 {
310 switch (idx) {
311 case 0: return (mdp5_cfg->ctl.base[0]);
312 case 1: return (mdp5_cfg->ctl.base[1]);
313 case 2: return (mdp5_cfg->ctl.base[2]);
314 case 3: return (mdp5_cfg->ctl.base[3]);
315 case 4: return (mdp5_cfg->ctl.base[4]);
316 default: return INVALID_IDX(idx);
317 }
318 }
REG_MDP5_CTL(uint32_t i0)319 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
320
__offset_LAYER(uint32_t idx)321 static inline uint32_t __offset_LAYER(uint32_t idx)
322 {
323 switch (idx) {
324 case 0: return 0x00000000;
325 case 1: return 0x00000004;
326 case 2: return 0x00000008;
327 case 3: return 0x0000000c;
328 case 4: return 0x00000010;
329 case 5: return 0x00000024;
330 default: return INVALID_IDX(idx);
331 }
332 }
REG_MDP5_CTL_LAYER(uint32_t i0,uint32_t i1)333 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
334
REG_MDP5_CTL_LAYER_REG(uint32_t i0,uint32_t i1)335 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
336 #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
337 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)338 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
339 {
340 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
341 }
342 #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
343 #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)344 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
345 {
346 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
347 }
348 #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
349 #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)350 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
351 {
352 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
353 }
354 #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
355 #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)356 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
357 {
358 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
359 }
360 #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
361 #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)362 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
363 {
364 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
365 }
366 #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
367 #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)368 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
369 {
370 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
371 }
372 #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
373 #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)374 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
375 {
376 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
377 }
378 #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
379 #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)380 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
381 {
382 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
383 }
384 #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
385 #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
386 #define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
387 #define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)388 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
389 {
390 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
391 }
392 #define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
393 #define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)394 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
395 {
396 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
397 }
398
REG_MDP5_CTL_OP(uint32_t i0)399 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
400 #define MDP5_CTL_OP_MODE__MASK 0x0000000f
401 #define MDP5_CTL_OP_MODE__SHIFT 0
MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)402 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
403 {
404 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
405 }
406 #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
407 #define MDP5_CTL_OP_INTF_NUM__SHIFT 4
MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)408 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
409 {
410 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
411 }
412 #define MDP5_CTL_OP_CMD_MODE 0x00020000
413 #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
414 #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
415 #define MDP5_CTL_OP_PACK_3D__SHIFT 20
MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)416 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
417 {
418 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
419 }
420
REG_MDP5_CTL_FLUSH(uint32_t i0)421 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
422 #define MDP5_CTL_FLUSH_VIG0 0x00000001
423 #define MDP5_CTL_FLUSH_VIG1 0x00000002
424 #define MDP5_CTL_FLUSH_VIG2 0x00000004
425 #define MDP5_CTL_FLUSH_RGB0 0x00000008
426 #define MDP5_CTL_FLUSH_RGB1 0x00000010
427 #define MDP5_CTL_FLUSH_RGB2 0x00000020
428 #define MDP5_CTL_FLUSH_LM0 0x00000040
429 #define MDP5_CTL_FLUSH_LM1 0x00000080
430 #define MDP5_CTL_FLUSH_LM2 0x00000100
431 #define MDP5_CTL_FLUSH_LM3 0x00000200
432 #define MDP5_CTL_FLUSH_LM4 0x00000400
433 #define MDP5_CTL_FLUSH_DMA0 0x00000800
434 #define MDP5_CTL_FLUSH_DMA1 0x00001000
435 #define MDP5_CTL_FLUSH_DSPP0 0x00002000
436 #define MDP5_CTL_FLUSH_DSPP1 0x00004000
437 #define MDP5_CTL_FLUSH_DSPP2 0x00008000
438 #define MDP5_CTL_FLUSH_CTL 0x00020000
439 #define MDP5_CTL_FLUSH_VIG3 0x00040000
440 #define MDP5_CTL_FLUSH_RGB3 0x00080000
441 #define MDP5_CTL_FLUSH_LM5 0x00100000
442 #define MDP5_CTL_FLUSH_DSPP3 0x00200000
443
REG_MDP5_CTL_START(uint32_t i0)444 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
445
REG_MDP5_CTL_PACK_3D(uint32_t i0)446 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
447
__offset_PIPE(enum mdp5_pipe idx)448 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
449 {
450 switch (idx) {
451 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
452 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
453 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
454 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
455 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
456 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
457 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
458 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
459 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
460 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
461 default: return INVALID_IDX(idx);
462 }
463 }
REG_MDP5_PIPE(enum mdp5_pipe i0)464 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
465
REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0)466 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
467
REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0)468 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
469
REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0)470 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
471
REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0)472 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
473 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
474 #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)475 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
476 {
477 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
478 }
479 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
480 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)481 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
482 {
483 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
484 }
485
REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0)486 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
487 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
488 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)489 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
490 {
491 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
492 }
493 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
494 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)495 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
496 {
497 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
498 }
499
REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0)500 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
501 #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
502 #define MDP5_PIPE_SRC_XY_Y__SHIFT 16
MDP5_PIPE_SRC_XY_Y(uint32_t val)503 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
504 {
505 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
506 }
507 #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
508 #define MDP5_PIPE_SRC_XY_X__SHIFT 0
MDP5_PIPE_SRC_XY_X(uint32_t val)509 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
510 {
511 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
512 }
513
REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0)514 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
515 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
516 #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)517 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
518 {
519 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
520 }
521 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
522 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)523 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
524 {
525 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
526 }
527
REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0)528 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
529 #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
530 #define MDP5_PIPE_OUT_XY_Y__SHIFT 16
MDP5_PIPE_OUT_XY_Y(uint32_t val)531 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
532 {
533 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
534 }
535 #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
536 #define MDP5_PIPE_OUT_XY_X__SHIFT 0
MDP5_PIPE_OUT_XY_X(uint32_t val)537 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
538 {
539 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
540 }
541
REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0)542 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
543
REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0)544 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
545
REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0)546 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
547
REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0)548 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
549
REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0)550 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
551 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
552 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)553 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
554 {
555 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
556 }
557 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
558 #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)559 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
560 {
561 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
562 }
563
REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0)564 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
565 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
566 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)567 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
568 {
569 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
570 }
571 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
572 #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)573 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
574 {
575 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
576 }
577
REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0)578 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
579
REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0)580 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
581 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
582 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)583 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
584 {
585 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
586 }
587 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
588 #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)589 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
590 {
591 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
592 }
593 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
594 #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)595 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
596 {
597 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
598 }
599 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
600 #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)601 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
602 {
603 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
604 }
605 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
606 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
607 #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)608 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
609 {
610 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
611 }
612 #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
613 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
614 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)615 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
616 {
617 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
618 }
619 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
620 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
621 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00780000
622 #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val)623 static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val)
624 {
625 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
626 }
627 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
628 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val)629 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val)
630 {
631 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
632 }
633
REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0)634 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
635 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
636 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)637 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
638 {
639 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
640 }
641 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
642 #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)643 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
644 {
645 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
646 }
647 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
648 #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)649 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
650 {
651 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
652 }
653 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
654 #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)655 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
656 {
657 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
658 }
659
REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0)660 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
661 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
662 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
663 #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)664 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
665 {
666 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
667 }
668 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
669 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
670 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
671 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
672 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
673 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
674 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
675
REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0)676 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
677
REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0)678 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
679
REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0)680 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
681
REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0)682 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
683
REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0)684 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
685
REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0)686 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
687
REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0)688 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
689
REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0)690 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
691
REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0)692 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
693
REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0)694 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
695
REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0)696 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
697
REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0)698 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
699 #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
700 #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
MDP5_PIPE_DECIMATION_VERT(uint32_t val)701 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
702 {
703 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
704 }
705 #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
706 #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
MDP5_PIPE_DECIMATION_HORZ(uint32_t val)707 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
708 {
709 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
710 }
711
REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0)712 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
713 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
714 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
715 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
716 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)717 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
718 {
719 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
720 }
721 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
722 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)723 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
724 {
725 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
726 }
727 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
728 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)729 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
730 {
731 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
732 }
733 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
734 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)735 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
736 {
737 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
738 }
739 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
740 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)741 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
742 {
743 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
744 }
745 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
746 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)747 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
748 {
749 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
750 }
751
REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0)752 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
753
REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0)754 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
755
REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0)756 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
757
REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0)758 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
759
__offset_LM(uint32_t idx)760 static inline uint32_t __offset_LM(uint32_t idx)
761 {
762 switch (idx) {
763 case 0: return (mdp5_cfg->lm.base[0]);
764 case 1: return (mdp5_cfg->lm.base[1]);
765 case 2: return (mdp5_cfg->lm.base[2]);
766 case 3: return (mdp5_cfg->lm.base[3]);
767 case 4: return (mdp5_cfg->lm.base[4]);
768 default: return INVALID_IDX(idx);
769 }
770 }
REG_MDP5_LM(uint32_t i0)771 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
772
REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0)773 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
774 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
775 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
776 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
777 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
778
REG_MDP5_LM_OUT_SIZE(uint32_t i0)779 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
780 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
781 #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)782 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
783 {
784 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
785 }
786 #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
787 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)788 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
789 {
790 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
791 }
792
REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0)793 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
794
REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0)795 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
796
REG_MDP5_LM_BLEND(uint32_t i0,uint32_t i1)797 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
798
REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0,uint32_t i1)799 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
800 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
801 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)802 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
803 {
804 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
805 }
806 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
807 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
808 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
809 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
810 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
811 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)812 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
813 {
814 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
815 }
816 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
817 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
818 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
819 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
820
REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0,uint32_t i1)821 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
822
REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0,uint32_t i1)823 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
824
REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0,uint32_t i1)825 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
826
REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0,uint32_t i1)827 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
828
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)829 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
830
REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)831 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
832
REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0,uint32_t i1)833 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
834
REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0,uint32_t i1)835 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
836
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0,uint32_t i1)837 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
838
REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0,uint32_t i1)839 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
840
REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0)841 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
842
REG_MDP5_LM_CURSOR_SIZE(uint32_t i0)843 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
844
REG_MDP5_LM_CURSOR_XY(uint32_t i0)845 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
846
REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0)847 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
848
REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0)849 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
850
REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0)851 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
852
REG_MDP5_LM_CURSOR_START_XY(uint32_t i0)853 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
854
REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0)855 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
856
REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0)857 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
858
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0)859 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
860
REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0)861 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
862
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0)863 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
864
REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0)865 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
866
REG_MDP5_LM_GC_LUT_BASE(uint32_t i0)867 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
868
__offset_DSPP(uint32_t idx)869 static inline uint32_t __offset_DSPP(uint32_t idx)
870 {
871 switch (idx) {
872 case 0: return (mdp5_cfg->dspp.base[0]);
873 case 1: return (mdp5_cfg->dspp.base[1]);
874 case 2: return (mdp5_cfg->dspp.base[2]);
875 case 3: return (mdp5_cfg->dspp.base[3]);
876 default: return INVALID_IDX(idx);
877 }
878 }
REG_MDP5_DSPP(uint32_t i0)879 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
880
REG_MDP5_DSPP_OP_MODE(uint32_t i0)881 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
882 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
883 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
884 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)885 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
886 {
887 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
888 }
889 #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
890 #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
891 #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
892 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
893 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
894 #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
895 #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
896 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
897
REG_MDP5_DSPP_PCC_BASE(uint32_t i0)898 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
899
REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0)900 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
901
REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0)902 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
903
REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0)904 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
905
REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0)906 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
907
REG_MDP5_DSPP_PA_BASE(uint32_t i0)908 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
909
REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0)910 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
911
REG_MDP5_DSPP_GC_BASE(uint32_t i0)912 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
913
__offset_INTF(uint32_t idx)914 static inline uint32_t __offset_INTF(uint32_t idx)
915 {
916 switch (idx) {
917 case 0: return (mdp5_cfg->intf.base[0]);
918 case 1: return (mdp5_cfg->intf.base[1]);
919 case 2: return (mdp5_cfg->intf.base[2]);
920 case 3: return (mdp5_cfg->intf.base[3]);
921 case 4: return (mdp5_cfg->intf.base[4]);
922 default: return INVALID_IDX(idx);
923 }
924 }
REG_MDP5_INTF(uint32_t i0)925 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
926
REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0)927 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
928
REG_MDP5_INTF_CONFIG(uint32_t i0)929 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
930
REG_MDP5_INTF_HSYNC_CTL(uint32_t i0)931 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
932 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
933 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)934 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
935 {
936 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
937 }
938 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
939 #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)940 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
941 {
942 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
943 }
944
REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0)945 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
946
REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0)947 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
948
REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0)949 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
950
REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0)951 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
952
REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0)953 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
954
REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0)955 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
956
REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0)957 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
958
REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0)959 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
960
REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0)961 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
962 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
963 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)964 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
965 {
966 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
967 }
968 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
969
REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0)970 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
971 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
972 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)973 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
974 {
975 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
976 }
977
REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0)978 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
979
REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0)980 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
981
REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0)982 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
983 #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
984 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)985 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
986 {
987 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
988 }
989 #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
990 #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)991 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
992 {
993 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
994 }
995
REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0)996 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
997 #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
998 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)999 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1000 {
1001 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1002 }
1003 #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1004 #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)1005 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1006 {
1007 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1008 }
1009 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1010
REG_MDP5_INTF_BORDER_COLOR(uint32_t i0)1011 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1012
REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0)1013 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1014
REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0)1015 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1016
REG_MDP5_INTF_POLARITY_CTL(uint32_t i0)1017 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1018 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1019 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1020 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1021
REG_MDP5_INTF_TEST_CTL(uint32_t i0)1022 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1023
REG_MDP5_INTF_TP_COLOR0(uint32_t i0)1024 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1025
REG_MDP5_INTF_TP_COLOR1(uint32_t i0)1026 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1027
REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0)1028 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1029
REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0)1030 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1031
REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0)1032 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1033
REG_MDP5_INTF_FRAME_COUNT(uint32_t i0)1034 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1035
REG_MDP5_INTF_LINE_COUNT(uint32_t i0)1036 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1037
REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0)1038 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1039
REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0)1040 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1041
REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0)1042 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1043
REG_MDP5_INTF_TPG_ENABLE(uint32_t i0)1044 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1045
REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0)1046 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1047
REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0)1048 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1049
REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0)1050 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1051
REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0)1052 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1053
REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0)1054 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1055
REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0)1056 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1057
REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0)1058 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1059
__offset_AD(uint32_t idx)1060 static inline uint32_t __offset_AD(uint32_t idx)
1061 {
1062 switch (idx) {
1063 case 0: return (mdp5_cfg->ad.base[0]);
1064 case 1: return (mdp5_cfg->ad.base[1]);
1065 default: return INVALID_IDX(idx);
1066 }
1067 }
REG_MDP5_AD(uint32_t i0)1068 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1069
REG_MDP5_AD_BYPASS(uint32_t i0)1070 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1071
REG_MDP5_AD_CTRL_0(uint32_t i0)1072 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1073
REG_MDP5_AD_CTRL_1(uint32_t i0)1074 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1075
REG_MDP5_AD_FRAME_SIZE(uint32_t i0)1076 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1077
REG_MDP5_AD_CON_CTRL_0(uint32_t i0)1078 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1079
REG_MDP5_AD_CON_CTRL_1(uint32_t i0)1080 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1081
REG_MDP5_AD_STR_MAN(uint32_t i0)1082 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1083
REG_MDP5_AD_VAR(uint32_t i0)1084 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1085
REG_MDP5_AD_DITH(uint32_t i0)1086 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1087
REG_MDP5_AD_DITH_CTRL(uint32_t i0)1088 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1089
REG_MDP5_AD_AMP_LIM(uint32_t i0)1090 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1091
REG_MDP5_AD_SLOPE(uint32_t i0)1092 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1093
REG_MDP5_AD_BW_LVL(uint32_t i0)1094 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1095
REG_MDP5_AD_LOGO_POS(uint32_t i0)1096 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1097
REG_MDP5_AD_LUT_FI(uint32_t i0)1098 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1099
REG_MDP5_AD_LUT_CC(uint32_t i0)1100 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1101
REG_MDP5_AD_STR_LIM(uint32_t i0)1102 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1103
REG_MDP5_AD_CALIB_AB(uint32_t i0)1104 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1105
REG_MDP5_AD_CALIB_CD(uint32_t i0)1106 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1107
REG_MDP5_AD_MODE_SEL(uint32_t i0)1108 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1109
REG_MDP5_AD_TFILT_CTRL(uint32_t i0)1110 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1111
REG_MDP5_AD_BL_MINMAX(uint32_t i0)1112 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1113
REG_MDP5_AD_BL(uint32_t i0)1114 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1115
REG_MDP5_AD_BL_MAX(uint32_t i0)1116 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1117
REG_MDP5_AD_AL(uint32_t i0)1118 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1119
REG_MDP5_AD_AL_MIN(uint32_t i0)1120 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1121
REG_MDP5_AD_AL_FILT(uint32_t i0)1122 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1123
REG_MDP5_AD_CFG_BUF(uint32_t i0)1124 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1125
REG_MDP5_AD_LUT_AL(uint32_t i0)1126 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1127
REG_MDP5_AD_TARG_STR(uint32_t i0)1128 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1129
REG_MDP5_AD_START_CALC(uint32_t i0)1130 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1131
REG_MDP5_AD_STR_OUT(uint32_t i0)1132 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1133
REG_MDP5_AD_BL_OUT(uint32_t i0)1134 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1135
REG_MDP5_AD_CALC_DONE(uint32_t i0)1136 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1137
1138
1139 #endif /* MDP5_XML */
1140