1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
45
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
48
49 #include "mlx4.h"
50 #include "fw.h"
51 #include "icm.h"
52
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION);
57
58 struct workqueue_struct *mlx4_wq;
59
60 #ifdef CONFIG_MLX4_DEBUG
61
62 int mlx4_debug_level = 0;
63 module_param_named(debug_level, mlx4_debug_level, int, 0644);
64 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66 #endif /* CONFIG_MLX4_DEBUG */
67
68 #ifdef CONFIG_PCI_MSI
69
70 static int msi_x = 1;
71 module_param(msi_x, int, 0444);
72 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74 #else /* CONFIG_PCI_MSI */
75
76 #define msi_x (0)
77
78 #endif /* CONFIG_PCI_MSI */
79
80 static uint8_t num_vfs[3] = {0, 0, 0};
81 static int num_vfs_argc;
82 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
83 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
85
86 static uint8_t probe_vf[3] = {0, 0, 0};
87 static int probe_vfs_argc;
88 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
89 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
91
92 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
93 module_param_named(log_num_mgm_entry_size,
94 mlx4_log_num_mgm_entry_size, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
101
102 static bool enable_64b_cqe_eqe = true;
103 module_param(enable_64b_cqe_eqe, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
106
107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
109
110 static char mlx4_version[] =
111 DRV_NAME ": Mellanox ConnectX core driver v"
112 DRV_VERSION " (" DRV_RELDATE ")\n";
113
114 static struct mlx4_profile default_profile = {
115 .num_qp = 1 << 18,
116 .num_srq = 1 << 16,
117 .rdmarc_per_qp = 1 << 4,
118 .num_cq = 1 << 16,
119 .num_mcg = 1 << 13,
120 .num_mpt = 1 << 19,
121 .num_mtt = 1 << 20, /* It is really num mtt segements */
122 };
123
124 static struct mlx4_profile low_mem_profile = {
125 .num_qp = 1 << 17,
126 .num_srq = 1 << 6,
127 .rdmarc_per_qp = 1 << 4,
128 .num_cq = 1 << 8,
129 .num_mcg = 1 << 8,
130 .num_mpt = 1 << 9,
131 .num_mtt = 1 << 7,
132 };
133
134 static int log_num_mac = 7;
135 module_param_named(log_num_mac, log_num_mac, int, 0444);
136 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
137
138 static int log_num_vlan;
139 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
140 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
141 /* Log2 max number of VLANs per ETH port (0-7) */
142 #define MLX4_LOG_NUM_VLANS 7
143 #define MLX4_MIN_LOG_NUM_VLANS 0
144 #define MLX4_MIN_LOG_NUM_MAC 1
145
146 static bool use_prio;
147 module_param_named(use_prio, use_prio, bool, 0444);
148 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
149
150 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
151 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
152 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
153
154 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
155 static int arr_argc = 2;
156 module_param_array(port_type_array, int, &arr_argc, 0444);
157 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
159
160 struct mlx4_port_config {
161 struct list_head list;
162 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
163 struct pci_dev *pdev;
164 };
165
166 static atomic_t pf_loading = ATOMIC_INIT(0);
167
mlx4_check_port_params(struct mlx4_dev * dev,enum mlx4_port_type * port_type)168 int mlx4_check_port_params(struct mlx4_dev *dev,
169 enum mlx4_port_type *port_type)
170 {
171 int i;
172
173 for (i = 0; i < dev->caps.num_ports - 1; i++) {
174 if (port_type[i] != port_type[i + 1]) {
175 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
176 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
177 return -EINVAL;
178 }
179 }
180 }
181
182 for (i = 0; i < dev->caps.num_ports; i++) {
183 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
184 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
185 i + 1);
186 return -EINVAL;
187 }
188 }
189 return 0;
190 }
191
mlx4_set_port_mask(struct mlx4_dev * dev)192 static void mlx4_set_port_mask(struct mlx4_dev *dev)
193 {
194 int i;
195
196 for (i = 1; i <= dev->caps.num_ports; ++i)
197 dev->caps.port_mask[i] = dev->caps.port_type[i];
198 }
199
mlx4_enable_cqe_eqe_stride(struct mlx4_dev * dev)200 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
201 {
202 struct mlx4_caps *dev_cap = &dev->caps;
203
204 /* FW not supporting or cancelled by user */
205 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
206 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
207 return;
208
209 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
210 * When FW has NCSI it may decide not to report 64B CQE/EQEs
211 */
212 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
213 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
214 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
215 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
216 return;
217 }
218
219 if (cache_line_size() == 128 || cache_line_size() == 256) {
220 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
221 /* Changing the real data inside CQE size to 32B */
222 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
223 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
224
225 if (mlx4_is_master(dev))
226 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
227 } else {
228 mlx4_dbg(dev, "Disabling CQE stride cacheLine unsupported\n");
229 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
230 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
231 }
232 }
233
mlx4_dev_cap(struct mlx4_dev * dev,struct mlx4_dev_cap * dev_cap)234 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
235 {
236 int err;
237 int i;
238
239 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
240 if (err) {
241 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
242 return err;
243 }
244
245 if (dev_cap->min_page_sz > PAGE_SIZE) {
246 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
247 dev_cap->min_page_sz, PAGE_SIZE);
248 return -ENODEV;
249 }
250 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
251 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
252 dev_cap->num_ports, MLX4_MAX_PORTS);
253 return -ENODEV;
254 }
255
256 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
257 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
258 dev_cap->uar_size,
259 (unsigned long long) pci_resource_len(dev->pdev, 2));
260 return -ENODEV;
261 }
262
263 dev->caps.num_ports = dev_cap->num_ports;
264 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
265 for (i = 1; i <= dev->caps.num_ports; ++i) {
266 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
267 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
268 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
269 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
270 /* set gid and pkey table operating lengths by default
271 * to non-sriov values */
272 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
273 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
274 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
275 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
276 dev->caps.def_mac[i] = dev_cap->def_mac[i];
277 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
278 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
279 dev->caps.default_sense[i] = dev_cap->default_sense[i];
280 dev->caps.trans_type[i] = dev_cap->trans_type[i];
281 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
282 dev->caps.wavelength[i] = dev_cap->wavelength[i];
283 dev->caps.trans_code[i] = dev_cap->trans_code[i];
284 }
285
286 dev->caps.uar_page_size = PAGE_SIZE;
287 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
288 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
289 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
290 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
291 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
292 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
293 dev->caps.max_wqes = dev_cap->max_qp_sz;
294 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
295 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
296 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
297 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
298 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
299 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
300 /*
301 * Subtract 1 from the limit because we need to allocate a
302 * spare CQE so the HCA HW can tell the difference between an
303 * empty CQ and a full CQ.
304 */
305 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
306 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
307 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
308 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
309 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
310
311 /* The first 128 UARs are used for EQ doorbells */
312 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
313 dev->caps.reserved_pds = dev_cap->reserved_pds;
314 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
315 dev_cap->reserved_xrcds : 0;
316 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
317 dev_cap->max_xrcds : 0;
318 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
319
320 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
321 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
322 dev->caps.flags = dev_cap->flags;
323 dev->caps.flags2 = dev_cap->flags2;
324 dev->caps.bmme_flags = dev_cap->bmme_flags;
325 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
326 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
327 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
328 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
329
330 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
331 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
332 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
333 /* Don't do sense port on multifunction devices (for now at least) */
334 if (mlx4_is_mfunc(dev))
335 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
336
337 if (mlx4_low_memory_profile()) {
338 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
339 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
340 } else {
341 dev->caps.log_num_macs = log_num_mac;
342 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
343 }
344
345 for (i = 1; i <= dev->caps.num_ports; ++i) {
346 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
347 if (dev->caps.supported_type[i]) {
348 /* if only ETH is supported - assign ETH */
349 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
350 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
351 /* if only IB is supported, assign IB */
352 else if (dev->caps.supported_type[i] ==
353 MLX4_PORT_TYPE_IB)
354 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
355 else {
356 /* if IB and ETH are supported, we set the port
357 * type according to user selection of port type;
358 * if user selected none, take the FW hint */
359 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
360 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
361 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
362 else
363 dev->caps.port_type[i] = port_type_array[i - 1];
364 }
365 }
366 /*
367 * Link sensing is allowed on the port if 3 conditions are true:
368 * 1. Both protocols are supported on the port.
369 * 2. Different types are supported on the port
370 * 3. FW declared that it supports link sensing
371 */
372 mlx4_priv(dev)->sense.sense_allowed[i] =
373 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
374 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
375 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
376
377 /*
378 * If "default_sense" bit is set, we move the port to "AUTO" mode
379 * and perform sense_port FW command to try and set the correct
380 * port type from beginning
381 */
382 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
383 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
384 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
385 mlx4_SENSE_PORT(dev, i, &sensed_port);
386 if (sensed_port != MLX4_PORT_TYPE_NONE)
387 dev->caps.port_type[i] = sensed_port;
388 } else {
389 dev->caps.possible_type[i] = dev->caps.port_type[i];
390 }
391
392 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
393 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
394 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
395 i, 1 << dev->caps.log_num_macs);
396 }
397 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
398 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
399 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
400 i, 1 << dev->caps.log_num_vlans);
401 }
402 }
403
404 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
405
406 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
407 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
408 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
409 (1 << dev->caps.log_num_macs) *
410 (1 << dev->caps.log_num_vlans) *
411 dev->caps.num_ports;
412 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
413
414 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
415 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
416 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
417 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
418
419 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
420
421 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
422 if (dev_cap->flags &
423 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
424 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
425 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
426 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
427 }
428
429 if (dev_cap->flags2 &
430 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
431 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
432 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
433 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
434 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
435 }
436 }
437
438 if ((dev->caps.flags &
439 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
440 mlx4_is_master(dev))
441 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
442
443 if (!mlx4_is_slave(dev))
444 mlx4_enable_cqe_eqe_stride(dev);
445
446 return 0;
447 }
448
mlx4_get_pcie_dev_link_caps(struct mlx4_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)449 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
450 enum pci_bus_speed *speed,
451 enum pcie_link_width *width)
452 {
453 u32 lnkcap1, lnkcap2;
454 int err1, err2;
455
456 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
457
458 *speed = PCI_SPEED_UNKNOWN;
459 *width = PCIE_LNK_WIDTH_UNKNOWN;
460
461 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
462 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
463 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
464 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
465 *speed = PCIE_SPEED_8_0GT;
466 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
467 *speed = PCIE_SPEED_5_0GT;
468 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
469 *speed = PCIE_SPEED_2_5GT;
470 }
471 if (!err1) {
472 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
473 if (!lnkcap2) { /* pre-r3.0 */
474 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
475 *speed = PCIE_SPEED_5_0GT;
476 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
477 *speed = PCIE_SPEED_2_5GT;
478 }
479 }
480
481 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
482 return err1 ? err1 :
483 err2 ? err2 : -EINVAL;
484 }
485 return 0;
486 }
487
mlx4_check_pcie_caps(struct mlx4_dev * dev)488 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
489 {
490 enum pcie_link_width width, width_cap;
491 enum pci_bus_speed speed, speed_cap;
492 int err;
493
494 #define PCIE_SPEED_STR(speed) \
495 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
496 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
497 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
498 "Unknown")
499
500 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
501 if (err) {
502 mlx4_warn(dev,
503 "Unable to determine PCIe device BW capabilities\n");
504 return;
505 }
506
507 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
508 if (err || speed == PCI_SPEED_UNKNOWN ||
509 width == PCIE_LNK_WIDTH_UNKNOWN) {
510 mlx4_warn(dev,
511 "Unable to determine PCI device chain minimum BW\n");
512 return;
513 }
514
515 if (width != width_cap || speed != speed_cap)
516 mlx4_warn(dev,
517 "PCIe BW is different than device's capability\n");
518
519 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
520 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
521 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
522 width, width_cap);
523 return;
524 }
525
526 /*The function checks if there are live vf, return the num of them*/
mlx4_how_many_lives_vf(struct mlx4_dev * dev)527 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
528 {
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_slave_state *s_state;
531 int i;
532 int ret = 0;
533
534 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
535 s_state = &priv->mfunc.master.slave_state[i];
536 if (s_state->active && s_state->last_cmd !=
537 MLX4_COMM_CMD_RESET) {
538 mlx4_warn(dev, "%s: slave: %d is still active\n",
539 __func__, i);
540 ret++;
541 }
542 }
543 return ret;
544 }
545
mlx4_get_parav_qkey(struct mlx4_dev * dev,u32 qpn,u32 * qkey)546 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
547 {
548 u32 qk = MLX4_RESERVED_QKEY_BASE;
549
550 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
551 qpn < dev->phys_caps.base_proxy_sqpn)
552 return -EINVAL;
553
554 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
555 /* tunnel qp */
556 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
557 else
558 qk += qpn - dev->phys_caps.base_proxy_sqpn;
559 *qkey = qk;
560 return 0;
561 }
562 EXPORT_SYMBOL(mlx4_get_parav_qkey);
563
mlx4_sync_pkey_table(struct mlx4_dev * dev,int slave,int port,int i,int val)564 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
565 {
566 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
567
568 if (!mlx4_is_master(dev))
569 return;
570
571 priv->virt2phys_pkey[slave][port - 1][i] = val;
572 }
573 EXPORT_SYMBOL(mlx4_sync_pkey_table);
574
mlx4_put_slave_node_guid(struct mlx4_dev * dev,int slave,__be64 guid)575 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
576 {
577 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
578
579 if (!mlx4_is_master(dev))
580 return;
581
582 priv->slave_node_guids[slave] = guid;
583 }
584 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
585
mlx4_get_slave_node_guid(struct mlx4_dev * dev,int slave)586 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
587 {
588 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
589
590 if (!mlx4_is_master(dev))
591 return 0;
592
593 return priv->slave_node_guids[slave];
594 }
595 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
596
mlx4_is_slave_active(struct mlx4_dev * dev,int slave)597 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
598 {
599 struct mlx4_priv *priv = mlx4_priv(dev);
600 struct mlx4_slave_state *s_slave;
601
602 if (!mlx4_is_master(dev))
603 return 0;
604
605 s_slave = &priv->mfunc.master.slave_state[slave];
606 return !!s_slave->active;
607 }
608 EXPORT_SYMBOL(mlx4_is_slave_active);
609
slave_adjust_steering_mode(struct mlx4_dev * dev,struct mlx4_dev_cap * dev_cap,struct mlx4_init_hca_param * hca_param)610 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
611 struct mlx4_dev_cap *dev_cap,
612 struct mlx4_init_hca_param *hca_param)
613 {
614 dev->caps.steering_mode = hca_param->steering_mode;
615 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
616 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
617 dev->caps.fs_log_max_ucast_qp_range_size =
618 dev_cap->fs_log_max_ucast_qp_range_size;
619 } else
620 dev->caps.num_qp_per_mgm =
621 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
622
623 mlx4_dbg(dev, "Steering mode is: %s\n",
624 mlx4_steering_mode_str(dev->caps.steering_mode));
625 }
626
mlx4_slave_cap(struct mlx4_dev * dev)627 static int mlx4_slave_cap(struct mlx4_dev *dev)
628 {
629 int err;
630 u32 page_size;
631 struct mlx4_dev_cap dev_cap;
632 struct mlx4_func_cap func_cap;
633 struct mlx4_init_hca_param hca_param;
634 int i;
635
636 memset(&hca_param, 0, sizeof(hca_param));
637 err = mlx4_QUERY_HCA(dev, &hca_param);
638 if (err) {
639 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
640 return err;
641 }
642
643 /* fail if the hca has an unknown global capability
644 * at this time global_caps should be always zeroed
645 */
646 if (hca_param.global_caps) {
647 mlx4_err(dev, "Unknown hca global capabilities\n");
648 return -ENOSYS;
649 }
650
651 dev->caps.hca_core_clock = hca_param.hca_core_clock;
652
653 memset(&dev_cap, 0, sizeof(dev_cap));
654 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
655 err = mlx4_dev_cap(dev, &dev_cap);
656 if (err) {
657 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
658 return err;
659 }
660
661 err = mlx4_QUERY_FW(dev);
662 if (err)
663 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
664
665 page_size = ~dev->caps.page_size_cap + 1;
666 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
667 if (page_size > PAGE_SIZE) {
668 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
669 page_size, PAGE_SIZE);
670 return -ENODEV;
671 }
672
673 /* slave gets uar page size from QUERY_HCA fw command */
674 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
675
676 /* TODO: relax this assumption */
677 if (dev->caps.uar_page_size != PAGE_SIZE) {
678 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
679 dev->caps.uar_page_size, PAGE_SIZE);
680 return -ENODEV;
681 }
682
683 memset(&func_cap, 0, sizeof(func_cap));
684 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
685 if (err) {
686 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
687 err);
688 return err;
689 }
690
691 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
692 PF_CONTEXT_BEHAVIOUR_MASK) {
693 mlx4_err(dev, "Unknown pf context behaviour\n");
694 return -ENOSYS;
695 }
696
697 dev->caps.num_ports = func_cap.num_ports;
698 dev->quotas.qp = func_cap.qp_quota;
699 dev->quotas.srq = func_cap.srq_quota;
700 dev->quotas.cq = func_cap.cq_quota;
701 dev->quotas.mpt = func_cap.mpt_quota;
702 dev->quotas.mtt = func_cap.mtt_quota;
703 dev->caps.num_qps = 1 << hca_param.log_num_qps;
704 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
705 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
706 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
707 dev->caps.num_eqs = func_cap.max_eq;
708 dev->caps.reserved_eqs = func_cap.reserved_eq;
709 dev->caps.num_pds = MLX4_NUM_PDS;
710 dev->caps.num_mgms = 0;
711 dev->caps.num_amgms = 0;
712
713 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
714 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
715 dev->caps.num_ports, MLX4_MAX_PORTS);
716 return -ENODEV;
717 }
718
719 dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);
720 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
721 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
722 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
723 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
724
725 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
726 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
727 !dev->caps.qp0_qkey) {
728 err = -ENOMEM;
729 goto err_mem;
730 }
731
732 for (i = 1; i <= dev->caps.num_ports; ++i) {
733 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
734 if (err) {
735 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
736 i, err);
737 goto err_mem;
738 }
739 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
740 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
741 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
742 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
743 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
744 dev->caps.port_mask[i] = dev->caps.port_type[i];
745 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
746 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
747 &dev->caps.gid_table_len[i],
748 &dev->caps.pkey_table_len[i]))
749 goto err_mem;
750 }
751
752 if (dev->caps.uar_page_size * (dev->caps.num_uars -
753 dev->caps.reserved_uars) >
754 pci_resource_len(dev->pdev, 2)) {
755 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
756 dev->caps.uar_page_size * dev->caps.num_uars,
757 (unsigned long long) pci_resource_len(dev->pdev, 2));
758 goto err_mem;
759 }
760
761 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
762 dev->caps.eqe_size = 64;
763 dev->caps.eqe_factor = 1;
764 } else {
765 dev->caps.eqe_size = 32;
766 dev->caps.eqe_factor = 0;
767 }
768
769 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
770 dev->caps.cqe_size = 64;
771 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
772 } else {
773 dev->caps.cqe_size = 32;
774 }
775
776 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
777 dev->caps.eqe_size = hca_param.eqe_size;
778 dev->caps.eqe_factor = 0;
779 }
780
781 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
782 dev->caps.cqe_size = hca_param.cqe_size;
783 /* User still need to know when CQE > 32B */
784 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
785 }
786
787 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
788 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
789
790 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
791
792 return 0;
793
794 err_mem:
795 kfree(dev->caps.qp0_qkey);
796 kfree(dev->caps.qp0_tunnel);
797 kfree(dev->caps.qp0_proxy);
798 kfree(dev->caps.qp1_tunnel);
799 kfree(dev->caps.qp1_proxy);
800 dev->caps.qp0_qkey = NULL;
801 dev->caps.qp0_tunnel = NULL;
802 dev->caps.qp0_proxy = NULL;
803 dev->caps.qp1_tunnel = NULL;
804 dev->caps.qp1_proxy = NULL;
805
806 return err;
807 }
808
mlx4_request_modules(struct mlx4_dev * dev)809 static void mlx4_request_modules(struct mlx4_dev *dev)
810 {
811 int port;
812 int has_ib_port = false;
813 int has_eth_port = false;
814 #define EN_DRV_NAME "mlx4_en"
815 #define IB_DRV_NAME "mlx4_ib"
816
817 for (port = 1; port <= dev->caps.num_ports; port++) {
818 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
819 has_ib_port = true;
820 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
821 has_eth_port = true;
822 }
823
824 if (has_eth_port)
825 request_module_nowait(EN_DRV_NAME);
826 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
827 request_module_nowait(IB_DRV_NAME);
828 }
829
830 /*
831 * Change the port configuration of the device.
832 * Every user of this function must hold the port mutex.
833 */
mlx4_change_port_types(struct mlx4_dev * dev,enum mlx4_port_type * port_types)834 int mlx4_change_port_types(struct mlx4_dev *dev,
835 enum mlx4_port_type *port_types)
836 {
837 int err = 0;
838 int change = 0;
839 int port;
840
841 for (port = 0; port < dev->caps.num_ports; port++) {
842 /* Change the port type only if the new type is different
843 * from the current, and not set to Auto */
844 if (port_types[port] != dev->caps.port_type[port + 1])
845 change = 1;
846 }
847 if (change) {
848 mlx4_unregister_device(dev);
849 for (port = 1; port <= dev->caps.num_ports; port++) {
850 mlx4_CLOSE_PORT(dev, port);
851 dev->caps.port_type[port] = port_types[port - 1];
852 err = mlx4_SET_PORT(dev, port, -1);
853 if (err) {
854 mlx4_err(dev, "Failed to set port %d, aborting\n",
855 port);
856 goto out;
857 }
858 }
859 mlx4_set_port_mask(dev);
860 err = mlx4_register_device(dev);
861 if (err) {
862 mlx4_err(dev, "Failed to register device\n");
863 goto out;
864 }
865 mlx4_request_modules(dev);
866 }
867
868 out:
869 return err;
870 }
871
show_port_type(struct device * dev,struct device_attribute * attr,char * buf)872 static ssize_t show_port_type(struct device *dev,
873 struct device_attribute *attr,
874 char *buf)
875 {
876 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
877 port_attr);
878 struct mlx4_dev *mdev = info->dev;
879 char type[8];
880
881 sprintf(type, "%s",
882 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
883 "ib" : "eth");
884 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
885 sprintf(buf, "auto (%s)\n", type);
886 else
887 sprintf(buf, "%s\n", type);
888
889 return strlen(buf);
890 }
891
set_port_type(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)892 static ssize_t set_port_type(struct device *dev,
893 struct device_attribute *attr,
894 const char *buf, size_t count)
895 {
896 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
897 port_attr);
898 struct mlx4_dev *mdev = info->dev;
899 struct mlx4_priv *priv = mlx4_priv(mdev);
900 enum mlx4_port_type types[MLX4_MAX_PORTS];
901 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
902 int i;
903 int err = 0;
904
905 if (!strcmp(buf, "ib\n"))
906 info->tmp_type = MLX4_PORT_TYPE_IB;
907 else if (!strcmp(buf, "eth\n"))
908 info->tmp_type = MLX4_PORT_TYPE_ETH;
909 else if (!strcmp(buf, "auto\n"))
910 info->tmp_type = MLX4_PORT_TYPE_AUTO;
911 else {
912 mlx4_err(mdev, "%s is not supported port type\n", buf);
913 return -EINVAL;
914 }
915
916 mlx4_stop_sense(mdev);
917 mutex_lock(&priv->port_mutex);
918 /* Possible type is always the one that was delivered */
919 mdev->caps.possible_type[info->port] = info->tmp_type;
920
921 for (i = 0; i < mdev->caps.num_ports; i++) {
922 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
923 mdev->caps.possible_type[i+1];
924 if (types[i] == MLX4_PORT_TYPE_AUTO)
925 types[i] = mdev->caps.port_type[i+1];
926 }
927
928 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
929 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
930 for (i = 1; i <= mdev->caps.num_ports; i++) {
931 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
932 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
933 err = -EINVAL;
934 }
935 }
936 }
937 if (err) {
938 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
939 goto out;
940 }
941
942 mlx4_do_sense_ports(mdev, new_types, types);
943
944 err = mlx4_check_port_params(mdev, new_types);
945 if (err)
946 goto out;
947
948 /* We are about to apply the changes after the configuration
949 * was verified, no need to remember the temporary types
950 * any more */
951 for (i = 0; i < mdev->caps.num_ports; i++)
952 priv->port[i + 1].tmp_type = 0;
953
954 err = mlx4_change_port_types(mdev, new_types);
955
956 out:
957 mlx4_start_sense(mdev);
958 mutex_unlock(&priv->port_mutex);
959 return err ? err : count;
960 }
961
962 enum ibta_mtu {
963 IB_MTU_256 = 1,
964 IB_MTU_512 = 2,
965 IB_MTU_1024 = 3,
966 IB_MTU_2048 = 4,
967 IB_MTU_4096 = 5
968 };
969
int_to_ibta_mtu(int mtu)970 static inline int int_to_ibta_mtu(int mtu)
971 {
972 switch (mtu) {
973 case 256: return IB_MTU_256;
974 case 512: return IB_MTU_512;
975 case 1024: return IB_MTU_1024;
976 case 2048: return IB_MTU_2048;
977 case 4096: return IB_MTU_4096;
978 default: return -1;
979 }
980 }
981
ibta_mtu_to_int(enum ibta_mtu mtu)982 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
983 {
984 switch (mtu) {
985 case IB_MTU_256: return 256;
986 case IB_MTU_512: return 512;
987 case IB_MTU_1024: return 1024;
988 case IB_MTU_2048: return 2048;
989 case IB_MTU_4096: return 4096;
990 default: return -1;
991 }
992 }
993
show_port_ib_mtu(struct device * dev,struct device_attribute * attr,char * buf)994 static ssize_t show_port_ib_mtu(struct device *dev,
995 struct device_attribute *attr,
996 char *buf)
997 {
998 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
999 port_mtu_attr);
1000 struct mlx4_dev *mdev = info->dev;
1001
1002 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1003 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1004
1005 sprintf(buf, "%d\n",
1006 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1007 return strlen(buf);
1008 }
1009
set_port_ib_mtu(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1010 static ssize_t set_port_ib_mtu(struct device *dev,
1011 struct device_attribute *attr,
1012 const char *buf, size_t count)
1013 {
1014 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1015 port_mtu_attr);
1016 struct mlx4_dev *mdev = info->dev;
1017 struct mlx4_priv *priv = mlx4_priv(mdev);
1018 int err, port, mtu, ibta_mtu = -1;
1019
1020 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1021 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1022 return -EINVAL;
1023 }
1024
1025 err = kstrtoint(buf, 0, &mtu);
1026 if (!err)
1027 ibta_mtu = int_to_ibta_mtu(mtu);
1028
1029 if (err || ibta_mtu < 0) {
1030 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1031 return -EINVAL;
1032 }
1033
1034 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1035
1036 mlx4_stop_sense(mdev);
1037 mutex_lock(&priv->port_mutex);
1038 mlx4_unregister_device(mdev);
1039 for (port = 1; port <= mdev->caps.num_ports; port++) {
1040 mlx4_CLOSE_PORT(mdev, port);
1041 err = mlx4_SET_PORT(mdev, port, -1);
1042 if (err) {
1043 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1044 port);
1045 goto err_set_port;
1046 }
1047 }
1048 err = mlx4_register_device(mdev);
1049 err_set_port:
1050 mutex_unlock(&priv->port_mutex);
1051 mlx4_start_sense(mdev);
1052 return err ? err : count;
1053 }
1054
mlx4_load_fw(struct mlx4_dev * dev)1055 static int mlx4_load_fw(struct mlx4_dev *dev)
1056 {
1057 struct mlx4_priv *priv = mlx4_priv(dev);
1058 int err;
1059
1060 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1061 GFP_HIGHUSER | __GFP_NOWARN, 0);
1062 if (!priv->fw.fw_icm) {
1063 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1064 return -ENOMEM;
1065 }
1066
1067 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1068 if (err) {
1069 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1070 goto err_free;
1071 }
1072
1073 err = mlx4_RUN_FW(dev);
1074 if (err) {
1075 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1076 goto err_unmap_fa;
1077 }
1078
1079 return 0;
1080
1081 err_unmap_fa:
1082 mlx4_UNMAP_FA(dev);
1083
1084 err_free:
1085 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1086 return err;
1087 }
1088
mlx4_init_cmpt_table(struct mlx4_dev * dev,u64 cmpt_base,int cmpt_entry_sz)1089 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1090 int cmpt_entry_sz)
1091 {
1092 struct mlx4_priv *priv = mlx4_priv(dev);
1093 int err;
1094 int num_eqs;
1095
1096 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1097 cmpt_base +
1098 ((u64) (MLX4_CMPT_TYPE_QP *
1099 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1100 cmpt_entry_sz, dev->caps.num_qps,
1101 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1102 0, 0);
1103 if (err)
1104 goto err;
1105
1106 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1107 cmpt_base +
1108 ((u64) (MLX4_CMPT_TYPE_SRQ *
1109 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1110 cmpt_entry_sz, dev->caps.num_srqs,
1111 dev->caps.reserved_srqs, 0, 0);
1112 if (err)
1113 goto err_qp;
1114
1115 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1116 cmpt_base +
1117 ((u64) (MLX4_CMPT_TYPE_CQ *
1118 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1119 cmpt_entry_sz, dev->caps.num_cqs,
1120 dev->caps.reserved_cqs, 0, 0);
1121 if (err)
1122 goto err_srq;
1123
1124 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1125 dev->caps.num_eqs;
1126 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1127 cmpt_base +
1128 ((u64) (MLX4_CMPT_TYPE_EQ *
1129 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1130 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1131 if (err)
1132 goto err_cq;
1133
1134 return 0;
1135
1136 err_cq:
1137 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1138
1139 err_srq:
1140 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1141
1142 err_qp:
1143 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1144
1145 err:
1146 return err;
1147 }
1148
mlx4_init_icm(struct mlx4_dev * dev,struct mlx4_dev_cap * dev_cap,struct mlx4_init_hca_param * init_hca,u64 icm_size)1149 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1150 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1151 {
1152 struct mlx4_priv *priv = mlx4_priv(dev);
1153 u64 aux_pages;
1154 int num_eqs;
1155 int err;
1156
1157 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1158 if (err) {
1159 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1160 return err;
1161 }
1162
1163 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1164 (unsigned long long) icm_size >> 10,
1165 (unsigned long long) aux_pages << 2);
1166
1167 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1168 GFP_HIGHUSER | __GFP_NOWARN, 0);
1169 if (!priv->fw.aux_icm) {
1170 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1171 return -ENOMEM;
1172 }
1173
1174 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1175 if (err) {
1176 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1177 goto err_free_aux;
1178 }
1179
1180 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1181 if (err) {
1182 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1183 goto err_unmap_aux;
1184 }
1185
1186
1187 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1188 dev->caps.num_eqs;
1189 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1190 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1191 num_eqs, num_eqs, 0, 0);
1192 if (err) {
1193 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1194 goto err_unmap_cmpt;
1195 }
1196
1197 /*
1198 * Reserved MTT entries must be aligned up to a cacheline
1199 * boundary, since the FW will write to them, while the driver
1200 * writes to all other MTT entries. (The variable
1201 * dev->caps.mtt_entry_sz below is really the MTT segment
1202 * size, not the raw entry size)
1203 */
1204 dev->caps.reserved_mtts =
1205 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1206 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1207
1208 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1209 init_hca->mtt_base,
1210 dev->caps.mtt_entry_sz,
1211 dev->caps.num_mtts,
1212 dev->caps.reserved_mtts, 1, 0);
1213 if (err) {
1214 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1215 goto err_unmap_eq;
1216 }
1217
1218 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1219 init_hca->dmpt_base,
1220 dev_cap->dmpt_entry_sz,
1221 dev->caps.num_mpts,
1222 dev->caps.reserved_mrws, 1, 1);
1223 if (err) {
1224 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1225 goto err_unmap_mtt;
1226 }
1227
1228 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1229 init_hca->qpc_base,
1230 dev_cap->qpc_entry_sz,
1231 dev->caps.num_qps,
1232 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1233 0, 0);
1234 if (err) {
1235 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1236 goto err_unmap_dmpt;
1237 }
1238
1239 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1240 init_hca->auxc_base,
1241 dev_cap->aux_entry_sz,
1242 dev->caps.num_qps,
1243 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1244 0, 0);
1245 if (err) {
1246 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1247 goto err_unmap_qp;
1248 }
1249
1250 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1251 init_hca->altc_base,
1252 dev_cap->altc_entry_sz,
1253 dev->caps.num_qps,
1254 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1255 0, 0);
1256 if (err) {
1257 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1258 goto err_unmap_auxc;
1259 }
1260
1261 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1262 init_hca->rdmarc_base,
1263 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1264 dev->caps.num_qps,
1265 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1266 0, 0);
1267 if (err) {
1268 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1269 goto err_unmap_altc;
1270 }
1271
1272 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1273 init_hca->cqc_base,
1274 dev_cap->cqc_entry_sz,
1275 dev->caps.num_cqs,
1276 dev->caps.reserved_cqs, 0, 0);
1277 if (err) {
1278 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1279 goto err_unmap_rdmarc;
1280 }
1281
1282 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1283 init_hca->srqc_base,
1284 dev_cap->srq_entry_sz,
1285 dev->caps.num_srqs,
1286 dev->caps.reserved_srqs, 0, 0);
1287 if (err) {
1288 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1289 goto err_unmap_cq;
1290 }
1291
1292 /*
1293 * For flow steering device managed mode it is required to use
1294 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1295 * required, but for simplicity just map the whole multicast
1296 * group table now. The table isn't very big and it's a lot
1297 * easier than trying to track ref counts.
1298 */
1299 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1300 init_hca->mc_base,
1301 mlx4_get_mgm_entry_size(dev),
1302 dev->caps.num_mgms + dev->caps.num_amgms,
1303 dev->caps.num_mgms + dev->caps.num_amgms,
1304 0, 0);
1305 if (err) {
1306 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1307 goto err_unmap_srq;
1308 }
1309
1310 return 0;
1311
1312 err_unmap_srq:
1313 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1314
1315 err_unmap_cq:
1316 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1317
1318 err_unmap_rdmarc:
1319 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1320
1321 err_unmap_altc:
1322 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1323
1324 err_unmap_auxc:
1325 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1326
1327 err_unmap_qp:
1328 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1329
1330 err_unmap_dmpt:
1331 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1332
1333 err_unmap_mtt:
1334 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1335
1336 err_unmap_eq:
1337 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1338
1339 err_unmap_cmpt:
1340 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1341 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1342 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1343 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1344
1345 err_unmap_aux:
1346 mlx4_UNMAP_ICM_AUX(dev);
1347
1348 err_free_aux:
1349 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1350
1351 return err;
1352 }
1353
mlx4_free_icms(struct mlx4_dev * dev)1354 static void mlx4_free_icms(struct mlx4_dev *dev)
1355 {
1356 struct mlx4_priv *priv = mlx4_priv(dev);
1357
1358 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1359 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1360 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1361 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1362 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1363 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1364 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1365 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1366 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1367 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1368 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1369 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1370 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1371 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1372
1373 mlx4_UNMAP_ICM_AUX(dev);
1374 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1375 }
1376
mlx4_slave_exit(struct mlx4_dev * dev)1377 static void mlx4_slave_exit(struct mlx4_dev *dev)
1378 {
1379 struct mlx4_priv *priv = mlx4_priv(dev);
1380
1381 mutex_lock(&priv->cmd.slave_cmd_mutex);
1382 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1383 mlx4_warn(dev, "Failed to close slave function\n");
1384 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1385 }
1386
map_bf_area(struct mlx4_dev * dev)1387 static int map_bf_area(struct mlx4_dev *dev)
1388 {
1389 struct mlx4_priv *priv = mlx4_priv(dev);
1390 resource_size_t bf_start;
1391 resource_size_t bf_len;
1392 int err = 0;
1393
1394 if (!dev->caps.bf_reg_size)
1395 return -ENXIO;
1396
1397 bf_start = pci_resource_start(dev->pdev, 2) +
1398 (dev->caps.num_uars << PAGE_SHIFT);
1399 bf_len = pci_resource_len(dev->pdev, 2) -
1400 (dev->caps.num_uars << PAGE_SHIFT);
1401 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1402 if (!priv->bf_mapping)
1403 err = -ENOMEM;
1404
1405 return err;
1406 }
1407
unmap_bf_area(struct mlx4_dev * dev)1408 static void unmap_bf_area(struct mlx4_dev *dev)
1409 {
1410 if (mlx4_priv(dev)->bf_mapping)
1411 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1412 }
1413
mlx4_read_clock(struct mlx4_dev * dev)1414 cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1415 {
1416 u32 clockhi, clocklo, clockhi1;
1417 cycle_t cycles;
1418 int i;
1419 struct mlx4_priv *priv = mlx4_priv(dev);
1420
1421 for (i = 0; i < 10; i++) {
1422 clockhi = swab32(readl(priv->clock_mapping));
1423 clocklo = swab32(readl(priv->clock_mapping + 4));
1424 clockhi1 = swab32(readl(priv->clock_mapping));
1425 if (clockhi == clockhi1)
1426 break;
1427 }
1428
1429 cycles = (u64) clockhi << 32 | (u64) clocklo;
1430
1431 return cycles;
1432 }
1433 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1434
1435
map_internal_clock(struct mlx4_dev * dev)1436 static int map_internal_clock(struct mlx4_dev *dev)
1437 {
1438 struct mlx4_priv *priv = mlx4_priv(dev);
1439
1440 priv->clock_mapping =
1441 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1442 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1443
1444 if (!priv->clock_mapping)
1445 return -ENOMEM;
1446
1447 return 0;
1448 }
1449
unmap_internal_clock(struct mlx4_dev * dev)1450 static void unmap_internal_clock(struct mlx4_dev *dev)
1451 {
1452 struct mlx4_priv *priv = mlx4_priv(dev);
1453
1454 if (priv->clock_mapping)
1455 iounmap(priv->clock_mapping);
1456 }
1457
mlx4_close_hca(struct mlx4_dev * dev)1458 static void mlx4_close_hca(struct mlx4_dev *dev)
1459 {
1460 unmap_internal_clock(dev);
1461 unmap_bf_area(dev);
1462 if (mlx4_is_slave(dev))
1463 mlx4_slave_exit(dev);
1464 else {
1465 mlx4_CLOSE_HCA(dev, 0);
1466 mlx4_free_icms(dev);
1467 mlx4_UNMAP_FA(dev);
1468 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1469 }
1470 }
1471
mlx4_init_slave(struct mlx4_dev * dev)1472 static int mlx4_init_slave(struct mlx4_dev *dev)
1473 {
1474 struct mlx4_priv *priv = mlx4_priv(dev);
1475 u64 dma = (u64) priv->mfunc.vhcr_dma;
1476 int ret_from_reset = 0;
1477 u32 slave_read;
1478 u32 cmd_channel_ver;
1479
1480 if (atomic_read(&pf_loading)) {
1481 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1482 return -EPROBE_DEFER;
1483 }
1484
1485 mutex_lock(&priv->cmd.slave_cmd_mutex);
1486 priv->cmd.max_cmds = 1;
1487 mlx4_warn(dev, "Sending reset\n");
1488 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1489 MLX4_COMM_TIME);
1490 /* if we are in the middle of flr the slave will try
1491 * NUM_OF_RESET_RETRIES times before leaving.*/
1492 if (ret_from_reset) {
1493 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1494 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1495 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1496 return -EPROBE_DEFER;
1497 } else
1498 goto err;
1499 }
1500
1501 /* check the driver version - the slave I/F revision
1502 * must match the master's */
1503 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1504 cmd_channel_ver = mlx4_comm_get_version();
1505
1506 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1507 MLX4_COMM_GET_IF_REV(slave_read)) {
1508 mlx4_err(dev, "slave driver version is not supported by the master\n");
1509 goto err;
1510 }
1511
1512 mlx4_warn(dev, "Sending vhcr0\n");
1513 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1514 MLX4_COMM_TIME))
1515 goto err;
1516 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1517 MLX4_COMM_TIME))
1518 goto err;
1519 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1520 MLX4_COMM_TIME))
1521 goto err;
1522 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1523 goto err;
1524
1525 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1526 return 0;
1527
1528 err:
1529 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1530 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1531 return -EIO;
1532 }
1533
mlx4_parav_master_pf_caps(struct mlx4_dev * dev)1534 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1535 {
1536 int i;
1537
1538 for (i = 1; i <= dev->caps.num_ports; i++) {
1539 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1540 dev->caps.gid_table_len[i] =
1541 mlx4_get_slave_num_gids(dev, 0, i);
1542 else
1543 dev->caps.gid_table_len[i] = 1;
1544 dev->caps.pkey_table_len[i] =
1545 dev->phys_caps.pkey_phys_table_len[i] - 1;
1546 }
1547 }
1548
choose_log_fs_mgm_entry_size(int qp_per_entry)1549 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1550 {
1551 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1552
1553 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1554 i++) {
1555 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1556 break;
1557 }
1558
1559 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1560 }
1561
choose_steering_mode(struct mlx4_dev * dev,struct mlx4_dev_cap * dev_cap)1562 static void choose_steering_mode(struct mlx4_dev *dev,
1563 struct mlx4_dev_cap *dev_cap)
1564 {
1565 if (mlx4_log_num_mgm_entry_size == -1 &&
1566 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1567 (!mlx4_is_mfunc(dev) ||
1568 (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) &&
1569 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1570 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1571 dev->oper_log_mgm_entry_size =
1572 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1573 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1574 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1575 dev->caps.fs_log_max_ucast_qp_range_size =
1576 dev_cap->fs_log_max_ucast_qp_range_size;
1577 } else {
1578 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1579 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1580 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1581 else {
1582 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1583
1584 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1585 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1586 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1587 }
1588 dev->oper_log_mgm_entry_size =
1589 mlx4_log_num_mgm_entry_size > 0 ?
1590 mlx4_log_num_mgm_entry_size :
1591 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1592 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1593 }
1594 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1595 mlx4_steering_mode_str(dev->caps.steering_mode),
1596 dev->oper_log_mgm_entry_size,
1597 mlx4_log_num_mgm_entry_size);
1598 }
1599
choose_tunnel_offload_mode(struct mlx4_dev * dev,struct mlx4_dev_cap * dev_cap)1600 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1601 struct mlx4_dev_cap *dev_cap)
1602 {
1603 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1604 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1605 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1606 else
1607 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1608
1609 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1610 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1611 }
1612
mlx4_init_hca(struct mlx4_dev * dev)1613 static int mlx4_init_hca(struct mlx4_dev *dev)
1614 {
1615 struct mlx4_priv *priv = mlx4_priv(dev);
1616 struct mlx4_adapter adapter;
1617 struct mlx4_dev_cap dev_cap;
1618 struct mlx4_mod_stat_cfg mlx4_cfg;
1619 struct mlx4_profile profile;
1620 struct mlx4_init_hca_param init_hca;
1621 u64 icm_size;
1622 int err;
1623
1624 if (!mlx4_is_slave(dev)) {
1625 err = mlx4_QUERY_FW(dev);
1626 if (err) {
1627 if (err == -EACCES)
1628 mlx4_info(dev, "non-primary physical function, skipping\n");
1629 else
1630 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
1631 return err;
1632 }
1633
1634 err = mlx4_load_fw(dev);
1635 if (err) {
1636 mlx4_err(dev, "Failed to start FW, aborting\n");
1637 return err;
1638 }
1639
1640 mlx4_cfg.log_pg_sz_m = 1;
1641 mlx4_cfg.log_pg_sz = 0;
1642 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1643 if (err)
1644 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1645
1646 err = mlx4_dev_cap(dev, &dev_cap);
1647 if (err) {
1648 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
1649 goto err_stop_fw;
1650 }
1651
1652 choose_steering_mode(dev, &dev_cap);
1653 choose_tunnel_offload_mode(dev, &dev_cap);
1654
1655 err = mlx4_get_phys_port_id(dev);
1656 if (err)
1657 mlx4_err(dev, "Fail to get physical port id\n");
1658
1659 if (mlx4_is_master(dev))
1660 mlx4_parav_master_pf_caps(dev);
1661
1662 if (mlx4_low_memory_profile()) {
1663 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
1664 profile = low_mem_profile;
1665 } else {
1666 profile = default_profile;
1667 }
1668 if (dev->caps.steering_mode ==
1669 MLX4_STEERING_MODE_DEVICE_MANAGED)
1670 profile.num_mcg = MLX4_FS_NUM_MCG;
1671
1672 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1673 &init_hca);
1674 if ((long long) icm_size < 0) {
1675 err = icm_size;
1676 goto err_stop_fw;
1677 }
1678
1679 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1680
1681 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1682 init_hca.uar_page_sz = PAGE_SHIFT - 12;
1683 init_hca.mw_enabled = 0;
1684 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1685 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1686 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
1687
1688 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1689 if (err)
1690 goto err_stop_fw;
1691
1692 err = mlx4_INIT_HCA(dev, &init_hca);
1693 if (err) {
1694 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
1695 goto err_free_icm;
1696 }
1697 /*
1698 * If TS is supported by FW
1699 * read HCA frequency by QUERY_HCA command
1700 */
1701 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1702 memset(&init_hca, 0, sizeof(init_hca));
1703 err = mlx4_QUERY_HCA(dev, &init_hca);
1704 if (err) {
1705 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
1706 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1707 } else {
1708 dev->caps.hca_core_clock =
1709 init_hca.hca_core_clock;
1710 }
1711
1712 /* In case we got HCA frequency 0 - disable timestamping
1713 * to avoid dividing by zero
1714 */
1715 if (!dev->caps.hca_core_clock) {
1716 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1717 mlx4_err(dev,
1718 "HCA frequency is 0 - timestamping is not supported\n");
1719 } else if (map_internal_clock(dev)) {
1720 /*
1721 * Map internal clock,
1722 * in case of failure disable timestamping
1723 */
1724 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1725 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
1726 }
1727 }
1728 } else {
1729 err = mlx4_init_slave(dev);
1730 if (err) {
1731 if (err != -EPROBE_DEFER)
1732 mlx4_err(dev, "Failed to initialize slave\n");
1733 return err;
1734 }
1735
1736 err = mlx4_slave_cap(dev);
1737 if (err) {
1738 mlx4_err(dev, "Failed to obtain slave caps\n");
1739 goto err_close;
1740 }
1741 }
1742
1743 if (map_bf_area(dev))
1744 mlx4_dbg(dev, "Failed to map blue flame area\n");
1745
1746 /*Only the master set the ports, all the rest got it from it.*/
1747 if (!mlx4_is_slave(dev))
1748 mlx4_set_port_mask(dev);
1749
1750 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1751 if (err) {
1752 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
1753 goto unmap_bf;
1754 }
1755
1756 priv->eq_table.inta_pin = adapter.inta_pin;
1757 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
1758
1759 return 0;
1760
1761 unmap_bf:
1762 unmap_internal_clock(dev);
1763 unmap_bf_area(dev);
1764
1765 if (mlx4_is_slave(dev)) {
1766 kfree(dev->caps.qp0_qkey);
1767 kfree(dev->caps.qp0_tunnel);
1768 kfree(dev->caps.qp0_proxy);
1769 kfree(dev->caps.qp1_tunnel);
1770 kfree(dev->caps.qp1_proxy);
1771 }
1772
1773 err_close:
1774 if (mlx4_is_slave(dev))
1775 mlx4_slave_exit(dev);
1776 else
1777 mlx4_CLOSE_HCA(dev, 0);
1778
1779 err_free_icm:
1780 if (!mlx4_is_slave(dev))
1781 mlx4_free_icms(dev);
1782
1783 err_stop_fw:
1784 if (!mlx4_is_slave(dev)) {
1785 mlx4_UNMAP_FA(dev);
1786 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1787 }
1788 return err;
1789 }
1790
mlx4_init_counters_table(struct mlx4_dev * dev)1791 static int mlx4_init_counters_table(struct mlx4_dev *dev)
1792 {
1793 struct mlx4_priv *priv = mlx4_priv(dev);
1794 int nent;
1795
1796 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1797 return -ENOENT;
1798
1799 nent = dev->caps.max_counters;
1800 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1801 }
1802
mlx4_cleanup_counters_table(struct mlx4_dev * dev)1803 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1804 {
1805 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1806 }
1807
__mlx4_counter_alloc(struct mlx4_dev * dev,u32 * idx)1808 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1809 {
1810 struct mlx4_priv *priv = mlx4_priv(dev);
1811
1812 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1813 return -ENOENT;
1814
1815 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1816 if (*idx == -1)
1817 return -ENOMEM;
1818
1819 return 0;
1820 }
1821
mlx4_counter_alloc(struct mlx4_dev * dev,u32 * idx)1822 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1823 {
1824 u64 out_param;
1825 int err;
1826
1827 if (mlx4_is_mfunc(dev)) {
1828 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1829 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1830 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1831 if (!err)
1832 *idx = get_param_l(&out_param);
1833
1834 return err;
1835 }
1836 return __mlx4_counter_alloc(dev, idx);
1837 }
1838 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1839
__mlx4_counter_free(struct mlx4_dev * dev,u32 idx)1840 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1841 {
1842 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
1843 return;
1844 }
1845
mlx4_counter_free(struct mlx4_dev * dev,u32 idx)1846 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1847 {
1848 u64 in_param = 0;
1849
1850 if (mlx4_is_mfunc(dev)) {
1851 set_param_l(&in_param, idx);
1852 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1853 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1854 MLX4_CMD_WRAPPED);
1855 return;
1856 }
1857 __mlx4_counter_free(dev, idx);
1858 }
1859 EXPORT_SYMBOL_GPL(mlx4_counter_free);
1860
mlx4_setup_hca(struct mlx4_dev * dev)1861 static int mlx4_setup_hca(struct mlx4_dev *dev)
1862 {
1863 struct mlx4_priv *priv = mlx4_priv(dev);
1864 int err;
1865 int port;
1866 __be32 ib_port_default_caps;
1867
1868 err = mlx4_init_uar_table(dev);
1869 if (err) {
1870 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
1871 return err;
1872 }
1873
1874 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1875 if (err) {
1876 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
1877 goto err_uar_table_free;
1878 }
1879
1880 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
1881 if (!priv->kar) {
1882 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
1883 err = -ENOMEM;
1884 goto err_uar_free;
1885 }
1886
1887 err = mlx4_init_pd_table(dev);
1888 if (err) {
1889 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
1890 goto err_kar_unmap;
1891 }
1892
1893 err = mlx4_init_xrcd_table(dev);
1894 if (err) {
1895 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
1896 goto err_pd_table_free;
1897 }
1898
1899 err = mlx4_init_mr_table(dev);
1900 if (err) {
1901 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
1902 goto err_xrcd_table_free;
1903 }
1904
1905 if (!mlx4_is_slave(dev)) {
1906 err = mlx4_init_mcg_table(dev);
1907 if (err) {
1908 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
1909 goto err_mr_table_free;
1910 }
1911 err = mlx4_config_mad_demux(dev);
1912 if (err) {
1913 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
1914 goto err_mcg_table_free;
1915 }
1916 }
1917
1918 err = mlx4_init_eq_table(dev);
1919 if (err) {
1920 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
1921 goto err_mcg_table_free;
1922 }
1923
1924 err = mlx4_cmd_use_events(dev);
1925 if (err) {
1926 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
1927 goto err_eq_table_free;
1928 }
1929
1930 err = mlx4_NOP(dev);
1931 if (err) {
1932 if (dev->flags & MLX4_FLAG_MSI_X) {
1933 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
1934 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1935 mlx4_warn(dev, "Trying again without MSI-X\n");
1936 } else {
1937 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
1938 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1939 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
1940 }
1941
1942 goto err_cmd_poll;
1943 }
1944
1945 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1946
1947 err = mlx4_init_cq_table(dev);
1948 if (err) {
1949 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
1950 goto err_cmd_poll;
1951 }
1952
1953 err = mlx4_init_srq_table(dev);
1954 if (err) {
1955 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
1956 goto err_cq_table_free;
1957 }
1958
1959 err = mlx4_init_qp_table(dev);
1960 if (err) {
1961 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
1962 goto err_srq_table_free;
1963 }
1964
1965 err = mlx4_init_counters_table(dev);
1966 if (err && err != -ENOENT) {
1967 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
1968 goto err_qp_table_free;
1969 }
1970
1971 if (!mlx4_is_slave(dev)) {
1972 for (port = 1; port <= dev->caps.num_ports; port++) {
1973 ib_port_default_caps = 0;
1974 err = mlx4_get_port_ib_caps(dev, port,
1975 &ib_port_default_caps);
1976 if (err)
1977 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1978 port, err);
1979 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1980
1981 /* initialize per-slave default ib port capabilities */
1982 if (mlx4_is_master(dev)) {
1983 int i;
1984 for (i = 0; i < dev->num_slaves; i++) {
1985 if (i == mlx4_master_func_num(dev))
1986 continue;
1987 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1988 ib_port_default_caps;
1989 }
1990 }
1991
1992 if (mlx4_is_mfunc(dev))
1993 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1994 else
1995 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
1996
1997 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1998 dev->caps.pkey_table_len[port] : -1);
1999 if (err) {
2000 mlx4_err(dev, "Failed to set port %d, aborting\n",
2001 port);
2002 goto err_counters_table_free;
2003 }
2004 }
2005 }
2006
2007 return 0;
2008
2009 err_counters_table_free:
2010 mlx4_cleanup_counters_table(dev);
2011
2012 err_qp_table_free:
2013 mlx4_cleanup_qp_table(dev);
2014
2015 err_srq_table_free:
2016 mlx4_cleanup_srq_table(dev);
2017
2018 err_cq_table_free:
2019 mlx4_cleanup_cq_table(dev);
2020
2021 err_cmd_poll:
2022 mlx4_cmd_use_polling(dev);
2023
2024 err_eq_table_free:
2025 mlx4_cleanup_eq_table(dev);
2026
2027 err_mcg_table_free:
2028 if (!mlx4_is_slave(dev))
2029 mlx4_cleanup_mcg_table(dev);
2030
2031 err_mr_table_free:
2032 mlx4_cleanup_mr_table(dev);
2033
2034 err_xrcd_table_free:
2035 mlx4_cleanup_xrcd_table(dev);
2036
2037 err_pd_table_free:
2038 mlx4_cleanup_pd_table(dev);
2039
2040 err_kar_unmap:
2041 iounmap(priv->kar);
2042
2043 err_uar_free:
2044 mlx4_uar_free(dev, &priv->driver_uar);
2045
2046 err_uar_table_free:
2047 mlx4_cleanup_uar_table(dev);
2048 return err;
2049 }
2050
mlx4_enable_msi_x(struct mlx4_dev * dev)2051 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2052 {
2053 struct mlx4_priv *priv = mlx4_priv(dev);
2054 struct msix_entry *entries;
2055 int nreq = min_t(int, dev->caps.num_ports *
2056 min_t(int, num_online_cpus() + 1,
2057 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
2058 int i;
2059
2060 if (msi_x) {
2061 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2062 nreq);
2063
2064 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2065 if (!entries)
2066 goto no_msi;
2067
2068 for (i = 0; i < nreq; ++i)
2069 entries[i].entry = i;
2070
2071 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
2072
2073 if (nreq < 0) {
2074 kfree(entries);
2075 goto no_msi;
2076 } else if (nreq < MSIX_LEGACY_SZ +
2077 dev->caps.num_ports * MIN_MSIX_P_PORT) {
2078 /*Working in legacy mode , all EQ's shared*/
2079 dev->caps.comp_pool = 0;
2080 dev->caps.num_comp_vectors = nreq - 1;
2081 } else {
2082 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2083 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2084 }
2085 for (i = 0; i < nreq; ++i)
2086 priv->eq_table.eq[i].irq = entries[i].vector;
2087
2088 dev->flags |= MLX4_FLAG_MSI_X;
2089
2090 kfree(entries);
2091 return;
2092 }
2093
2094 no_msi:
2095 dev->caps.num_comp_vectors = 1;
2096 dev->caps.comp_pool = 0;
2097
2098 for (i = 0; i < 2; ++i)
2099 priv->eq_table.eq[i].irq = dev->pdev->irq;
2100 }
2101
mlx4_init_port_info(struct mlx4_dev * dev,int port)2102 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2103 {
2104 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2105 int err = 0;
2106
2107 info->dev = dev;
2108 info->port = port;
2109 if (!mlx4_is_slave(dev)) {
2110 mlx4_init_mac_table(dev, &info->mac_table);
2111 mlx4_init_vlan_table(dev, &info->vlan_table);
2112 mlx4_init_roce_gid_table(dev, &info->gid_table);
2113 info->base_qpn = mlx4_get_base_qpn(dev, port);
2114 }
2115
2116 sprintf(info->dev_name, "mlx4_port%d", port);
2117 info->port_attr.attr.name = info->dev_name;
2118 if (mlx4_is_mfunc(dev))
2119 info->port_attr.attr.mode = S_IRUGO;
2120 else {
2121 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2122 info->port_attr.store = set_port_type;
2123 }
2124 info->port_attr.show = show_port_type;
2125 sysfs_attr_init(&info->port_attr.attr);
2126
2127 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2128 if (err) {
2129 mlx4_err(dev, "Failed to create file for port %d\n", port);
2130 info->port = -1;
2131 }
2132
2133 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2134 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2135 if (mlx4_is_mfunc(dev))
2136 info->port_mtu_attr.attr.mode = S_IRUGO;
2137 else {
2138 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2139 info->port_mtu_attr.store = set_port_ib_mtu;
2140 }
2141 info->port_mtu_attr.show = show_port_ib_mtu;
2142 sysfs_attr_init(&info->port_mtu_attr.attr);
2143
2144 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2145 if (err) {
2146 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2147 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2148 info->port = -1;
2149 }
2150
2151 return err;
2152 }
2153
mlx4_cleanup_port_info(struct mlx4_port_info * info)2154 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2155 {
2156 if (info->port < 0)
2157 return;
2158
2159 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2160 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2161 }
2162
mlx4_init_steering(struct mlx4_dev * dev)2163 static int mlx4_init_steering(struct mlx4_dev *dev)
2164 {
2165 struct mlx4_priv *priv = mlx4_priv(dev);
2166 int num_entries = dev->caps.num_ports;
2167 int i, j;
2168
2169 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2170 if (!priv->steer)
2171 return -ENOMEM;
2172
2173 for (i = 0; i < num_entries; i++)
2174 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2175 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2176 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2177 }
2178 return 0;
2179 }
2180
mlx4_clear_steering(struct mlx4_dev * dev)2181 static void mlx4_clear_steering(struct mlx4_dev *dev)
2182 {
2183 struct mlx4_priv *priv = mlx4_priv(dev);
2184 struct mlx4_steer_index *entry, *tmp_entry;
2185 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2186 int num_entries = dev->caps.num_ports;
2187 int i, j;
2188
2189 for (i = 0; i < num_entries; i++) {
2190 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2191 list_for_each_entry_safe(pqp, tmp_pqp,
2192 &priv->steer[i].promisc_qps[j],
2193 list) {
2194 list_del(&pqp->list);
2195 kfree(pqp);
2196 }
2197 list_for_each_entry_safe(entry, tmp_entry,
2198 &priv->steer[i].steer_entries[j],
2199 list) {
2200 list_del(&entry->list);
2201 list_for_each_entry_safe(pqp, tmp_pqp,
2202 &entry->duplicates,
2203 list) {
2204 list_del(&pqp->list);
2205 kfree(pqp);
2206 }
2207 kfree(entry);
2208 }
2209 }
2210 }
2211 kfree(priv->steer);
2212 }
2213
extended_func_num(struct pci_dev * pdev)2214 static int extended_func_num(struct pci_dev *pdev)
2215 {
2216 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2217 }
2218
2219 #define MLX4_OWNER_BASE 0x8069c
2220 #define MLX4_OWNER_SIZE 4
2221
mlx4_get_ownership(struct mlx4_dev * dev)2222 static int mlx4_get_ownership(struct mlx4_dev *dev)
2223 {
2224 void __iomem *owner;
2225 u32 ret;
2226
2227 if (pci_channel_offline(dev->pdev))
2228 return -EIO;
2229
2230 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2231 MLX4_OWNER_SIZE);
2232 if (!owner) {
2233 mlx4_err(dev, "Failed to obtain ownership bit\n");
2234 return -ENOMEM;
2235 }
2236
2237 ret = readl(owner);
2238 iounmap(owner);
2239 return (int) !!ret;
2240 }
2241
mlx4_free_ownership(struct mlx4_dev * dev)2242 static void mlx4_free_ownership(struct mlx4_dev *dev)
2243 {
2244 void __iomem *owner;
2245
2246 if (pci_channel_offline(dev->pdev))
2247 return;
2248
2249 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2250 MLX4_OWNER_SIZE);
2251 if (!owner) {
2252 mlx4_err(dev, "Failed to obtain ownership bit\n");
2253 return;
2254 }
2255 writel(0, owner);
2256 msleep(1000);
2257 iounmap(owner);
2258 }
2259
mlx4_load_one(struct pci_dev * pdev,int pci_dev_data,int total_vfs,int * nvfs,struct mlx4_priv * priv)2260 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
2261 int total_vfs, int *nvfs, struct mlx4_priv *priv)
2262 {
2263 struct mlx4_dev *dev;
2264 unsigned sum = 0;
2265 int err;
2266 int port;
2267 int i;
2268 int existing_vfs = 0;
2269
2270 dev = &priv->dev;
2271
2272 INIT_LIST_HEAD(&priv->ctx_list);
2273 spin_lock_init(&priv->ctx_lock);
2274
2275 mutex_init(&priv->port_mutex);
2276
2277 INIT_LIST_HEAD(&priv->pgdir_list);
2278 mutex_init(&priv->pgdir_mutex);
2279
2280 INIT_LIST_HEAD(&priv->bf_list);
2281 mutex_init(&priv->bf_mutex);
2282
2283 dev->rev_id = pdev->revision;
2284 dev->numa_node = dev_to_node(&pdev->dev);
2285
2286 /* Detect if this device is a virtual function */
2287 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2288 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2289 dev->flags |= MLX4_FLAG_SLAVE;
2290 } else {
2291 /* We reset the device and enable SRIOV only for physical
2292 * devices. Try to claim ownership on the device;
2293 * if already taken, skip -- do not allow multiple PFs */
2294 err = mlx4_get_ownership(dev);
2295 if (err) {
2296 if (err < 0)
2297 return err;
2298 else {
2299 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
2300 return -EINVAL;
2301 }
2302 }
2303
2304 if (total_vfs) {
2305 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n",
2306 total_vfs);
2307 dev->dev_vfs = kzalloc(
2308 total_vfs * sizeof(*dev->dev_vfs),
2309 GFP_KERNEL);
2310 if (NULL == dev->dev_vfs) {
2311 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2312 err = -ENOMEM;
2313 goto err_free_own;
2314 } else {
2315 atomic_inc(&pf_loading);
2316 existing_vfs = pci_num_vf(pdev);
2317 if (existing_vfs) {
2318 err = 0;
2319 if (existing_vfs != total_vfs)
2320 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2321 existing_vfs, total_vfs);
2322 } else {
2323 err = pci_enable_sriov(pdev, total_vfs);
2324 }
2325 if (err) {
2326 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2327 err);
2328 atomic_dec(&pf_loading);
2329 } else {
2330 mlx4_warn(dev, "Running in master mode\n");
2331 dev->flags |= MLX4_FLAG_SRIOV |
2332 MLX4_FLAG_MASTER;
2333 dev->num_vfs = total_vfs;
2334 }
2335 }
2336 }
2337
2338 atomic_set(&priv->opreq_count, 0);
2339 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2340
2341 /*
2342 * Now reset the HCA before we touch the PCI capabilities or
2343 * attempt a firmware command, since a boot ROM may have left
2344 * the HCA in an undefined state.
2345 */
2346 err = mlx4_reset(dev);
2347 if (err) {
2348 mlx4_err(dev, "Failed to reset HCA, aborting\n");
2349 goto err_sriov;
2350 }
2351 }
2352
2353 slave_start:
2354 err = mlx4_cmd_init(dev);
2355 if (err) {
2356 mlx4_err(dev, "Failed to init command interface, aborting\n");
2357 goto err_sriov;
2358 }
2359
2360 /* In slave functions, the communication channel must be initialized
2361 * before posting commands. Also, init num_slaves before calling
2362 * mlx4_init_hca */
2363 if (mlx4_is_mfunc(dev)) {
2364 if (mlx4_is_master(dev))
2365 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2366 else {
2367 dev->num_slaves = 0;
2368 err = mlx4_multi_func_init(dev);
2369 if (err) {
2370 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
2371 goto err_cmd;
2372 }
2373 }
2374 }
2375
2376 err = mlx4_init_hca(dev);
2377 if (err) {
2378 if (err == -EACCES) {
2379 /* Not primary Physical function
2380 * Running in slave mode */
2381 mlx4_cmd_cleanup(dev);
2382 dev->flags |= MLX4_FLAG_SLAVE;
2383 dev->flags &= ~MLX4_FLAG_MASTER;
2384 goto slave_start;
2385 } else
2386 goto err_mfunc;
2387 }
2388
2389 /* check if the device is functioning at its maximum possible speed.
2390 * No return code for this call, just warn the user in case of PCI
2391 * express device capabilities are under-satisfied by the bus.
2392 */
2393 if (!mlx4_is_slave(dev))
2394 mlx4_check_pcie_caps(dev);
2395
2396 /* In master functions, the communication channel must be initialized
2397 * after obtaining its address from fw */
2398 if (mlx4_is_master(dev)) {
2399 int ib_ports = 0;
2400
2401 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2402 ib_ports++;
2403
2404 if (ib_ports &&
2405 (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
2406 mlx4_err(dev,
2407 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2408 err = -EINVAL;
2409 goto err_close;
2410 }
2411 if (dev->caps.num_ports < 2 &&
2412 num_vfs_argc > 1) {
2413 err = -EINVAL;
2414 mlx4_err(dev,
2415 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2416 dev->caps.num_ports);
2417 goto err_close;
2418 }
2419 memcpy(dev->nvfs, nvfs, sizeof(dev->nvfs));
2420
2421 for (i = 0; i < sizeof(dev->nvfs)/sizeof(dev->nvfs[0]); i++) {
2422 unsigned j;
2423
2424 for (j = 0; j < dev->nvfs[i]; ++sum, ++j) {
2425 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
2426 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
2427 dev->caps.num_ports;
2428 }
2429 }
2430
2431 /* In master functions, the communication channel
2432 * must be initialized after obtaining its address from fw
2433 */
2434 err = mlx4_multi_func_init(dev);
2435 if (err) {
2436 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
2437 goto err_close;
2438 }
2439 }
2440
2441 err = mlx4_alloc_eq_table(dev);
2442 if (err)
2443 goto err_master_mfunc;
2444
2445 priv->msix_ctl.pool_bm = 0;
2446 mutex_init(&priv->msix_ctl.pool_lock);
2447
2448 mlx4_enable_msi_x(dev);
2449 if ((mlx4_is_mfunc(dev)) &&
2450 !(dev->flags & MLX4_FLAG_MSI_X)) {
2451 err = -ENOSYS;
2452 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
2453 goto err_free_eq;
2454 }
2455
2456 if (!mlx4_is_slave(dev)) {
2457 err = mlx4_init_steering(dev);
2458 if (err)
2459 goto err_disable_msix;
2460 }
2461
2462 err = mlx4_setup_hca(dev);
2463 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2464 !mlx4_is_mfunc(dev)) {
2465 dev->flags &= ~MLX4_FLAG_MSI_X;
2466 dev->caps.num_comp_vectors = 1;
2467 dev->caps.comp_pool = 0;
2468 pci_disable_msix(pdev);
2469 err = mlx4_setup_hca(dev);
2470 }
2471
2472 if (err)
2473 goto err_steer;
2474
2475 mlx4_init_quotas(dev);
2476
2477 for (port = 1; port <= dev->caps.num_ports; port++) {
2478 err = mlx4_init_port_info(dev, port);
2479 if (err)
2480 goto err_port;
2481 }
2482
2483 err = mlx4_register_device(dev);
2484 if (err)
2485 goto err_port;
2486
2487 mlx4_request_modules(dev);
2488
2489 mlx4_sense_init(dev);
2490 mlx4_start_sense(dev);
2491
2492 priv->removed = 0;
2493
2494 if (mlx4_is_master(dev) && dev->num_vfs)
2495 atomic_dec(&pf_loading);
2496
2497 return 0;
2498
2499 err_port:
2500 for (--port; port >= 1; --port)
2501 mlx4_cleanup_port_info(&priv->port[port]);
2502
2503 mlx4_cleanup_counters_table(dev);
2504 mlx4_cleanup_qp_table(dev);
2505 mlx4_cleanup_srq_table(dev);
2506 mlx4_cleanup_cq_table(dev);
2507 mlx4_cmd_use_polling(dev);
2508 mlx4_cleanup_eq_table(dev);
2509 mlx4_cleanup_mcg_table(dev);
2510 mlx4_cleanup_mr_table(dev);
2511 mlx4_cleanup_xrcd_table(dev);
2512 mlx4_cleanup_pd_table(dev);
2513 mlx4_cleanup_uar_table(dev);
2514
2515 err_steer:
2516 if (!mlx4_is_slave(dev))
2517 mlx4_clear_steering(dev);
2518
2519 err_disable_msix:
2520 if (dev->flags & MLX4_FLAG_MSI_X)
2521 pci_disable_msix(pdev);
2522
2523 err_free_eq:
2524 mlx4_free_eq_table(dev);
2525
2526 err_master_mfunc:
2527 if (mlx4_is_master(dev))
2528 mlx4_multi_func_cleanup(dev);
2529
2530 if (mlx4_is_slave(dev)) {
2531 kfree(dev->caps.qp0_qkey);
2532 kfree(dev->caps.qp0_tunnel);
2533 kfree(dev->caps.qp0_proxy);
2534 kfree(dev->caps.qp1_tunnel);
2535 kfree(dev->caps.qp1_proxy);
2536 }
2537
2538 err_close:
2539 mlx4_close_hca(dev);
2540
2541 err_mfunc:
2542 if (mlx4_is_slave(dev))
2543 mlx4_multi_func_cleanup(dev);
2544
2545 err_cmd:
2546 mlx4_cmd_cleanup(dev);
2547
2548 err_sriov:
2549 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs)
2550 pci_disable_sriov(pdev);
2551
2552 if (mlx4_is_master(dev) && dev->num_vfs)
2553 atomic_dec(&pf_loading);
2554
2555 kfree(priv->dev.dev_vfs);
2556
2557 err_free_own:
2558 if (!mlx4_is_slave(dev))
2559 mlx4_free_ownership(dev);
2560
2561 return err;
2562 }
2563
__mlx4_init_one(struct pci_dev * pdev,int pci_dev_data,struct mlx4_priv * priv)2564 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
2565 struct mlx4_priv *priv)
2566 {
2567 int err;
2568 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2569 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2570 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
2571 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2572 unsigned total_vfs = 0;
2573 unsigned int i;
2574
2575 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
2576
2577 err = pci_enable_device(pdev);
2578 if (err) {
2579 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
2580 return err;
2581 }
2582
2583 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2584 * per port, we must limit the number of VFs to 63 (since their are
2585 * 128 MACs)
2586 */
2587 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
2588 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
2589 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
2590 if (nvfs[i] < 0) {
2591 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
2592 err = -EINVAL;
2593 goto err_disable_pdev;
2594 }
2595 }
2596 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
2597 i++) {
2598 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
2599 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
2600 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2601 err = -EINVAL;
2602 goto err_disable_pdev;
2603 }
2604 }
2605 if (total_vfs >= MLX4_MAX_NUM_VF) {
2606 dev_err(&pdev->dev,
2607 "Requested more VF's (%d) than allowed (%d)\n",
2608 total_vfs, MLX4_MAX_NUM_VF - 1);
2609 err = -EINVAL;
2610 goto err_disable_pdev;
2611 }
2612
2613 for (i = 0; i < MLX4_MAX_PORTS; i++) {
2614 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
2615 dev_err(&pdev->dev,
2616 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2617 nvfs[i] + nvfs[2], i + 1,
2618 MLX4_MAX_NUM_VF_P_PORT - 1);
2619 err = -EINVAL;
2620 goto err_disable_pdev;
2621 }
2622 }
2623
2624 /* Check for BARs. */
2625 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
2626 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2627 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2628 pci_dev_data, pci_resource_flags(pdev, 0));
2629 err = -ENODEV;
2630 goto err_disable_pdev;
2631 }
2632 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2633 dev_err(&pdev->dev, "Missing UAR, aborting\n");
2634 err = -ENODEV;
2635 goto err_disable_pdev;
2636 }
2637
2638 err = pci_request_regions(pdev, DRV_NAME);
2639 if (err) {
2640 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
2641 goto err_disable_pdev;
2642 }
2643
2644 pci_set_master(pdev);
2645
2646 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2647 if (err) {
2648 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
2649 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2650 if (err) {
2651 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
2652 goto err_release_regions;
2653 }
2654 }
2655 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2656 if (err) {
2657 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2658 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2659 if (err) {
2660 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
2661 goto err_release_regions;
2662 }
2663 }
2664
2665 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2666 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2667 /* Detect if this device is a virtual function */
2668 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2669 /* When acting as pf, we normally skip vfs unless explicitly
2670 * requested to probe them.
2671 */
2672 if (total_vfs) {
2673 unsigned vfs_offset = 0;
2674
2675 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
2676 vfs_offset + nvfs[i] < extended_func_num(pdev);
2677 vfs_offset += nvfs[i], i++)
2678 ;
2679 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
2680 err = -ENODEV;
2681 goto err_release_regions;
2682 }
2683 if ((extended_func_num(pdev) - vfs_offset)
2684 > prb_vf[i]) {
2685 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
2686 extended_func_num(pdev));
2687 err = -ENODEV;
2688 goto err_release_regions;
2689 }
2690 }
2691 }
2692
2693 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2694 if (err)
2695 goto err_release_regions;
2696 return 0;
2697
2698 err_release_regions:
2699 pci_release_regions(pdev);
2700
2701 err_disable_pdev:
2702 pci_disable_device(pdev);
2703 pci_set_drvdata(pdev, NULL);
2704 return err;
2705 }
2706
mlx4_init_one(struct pci_dev * pdev,const struct pci_device_id * id)2707 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
2708 {
2709 struct mlx4_priv *priv;
2710 struct mlx4_dev *dev;
2711 int ret;
2712
2713 printk_once(KERN_INFO "%s", mlx4_version);
2714
2715 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
2716 if (!priv)
2717 return -ENOMEM;
2718
2719 dev = &priv->dev;
2720 dev->pdev = pdev;
2721 pci_set_drvdata(pdev, dev);
2722 priv->pci_dev_data = id->driver_data;
2723
2724 ret = __mlx4_init_one(pdev, id->driver_data, priv);
2725 if (ret)
2726 kfree(priv);
2727
2728 return ret;
2729 }
2730
mlx4_unload_one(struct pci_dev * pdev)2731 static void mlx4_unload_one(struct pci_dev *pdev)
2732 {
2733 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2734 struct mlx4_priv *priv = mlx4_priv(dev);
2735 int pci_dev_data;
2736 int p;
2737 int active_vfs = 0;
2738
2739 if (priv->removed)
2740 return;
2741
2742 pci_dev_data = priv->pci_dev_data;
2743
2744 /* Disabling SR-IOV is not allowed while there are active vf's */
2745 if (mlx4_is_master(dev)) {
2746 active_vfs = mlx4_how_many_lives_vf(dev);
2747 if (active_vfs) {
2748 pr_warn("Removing PF when there are active VF's !!\n");
2749 pr_warn("Will not disable SR-IOV.\n");
2750 }
2751 }
2752 mlx4_stop_sense(dev);
2753 mlx4_unregister_device(dev);
2754
2755 for (p = 1; p <= dev->caps.num_ports; p++) {
2756 mlx4_cleanup_port_info(&priv->port[p]);
2757 mlx4_CLOSE_PORT(dev, p);
2758 }
2759
2760 if (mlx4_is_master(dev))
2761 mlx4_free_resource_tracker(dev,
2762 RES_TR_FREE_SLAVES_ONLY);
2763
2764 mlx4_cleanup_counters_table(dev);
2765 mlx4_cleanup_qp_table(dev);
2766 mlx4_cleanup_srq_table(dev);
2767 mlx4_cleanup_cq_table(dev);
2768 mlx4_cmd_use_polling(dev);
2769 mlx4_cleanup_eq_table(dev);
2770 mlx4_cleanup_mcg_table(dev);
2771 mlx4_cleanup_mr_table(dev);
2772 mlx4_cleanup_xrcd_table(dev);
2773 mlx4_cleanup_pd_table(dev);
2774
2775 if (mlx4_is_master(dev))
2776 mlx4_free_resource_tracker(dev,
2777 RES_TR_FREE_STRUCTS_ONLY);
2778
2779 iounmap(priv->kar);
2780 mlx4_uar_free(dev, &priv->driver_uar);
2781 mlx4_cleanup_uar_table(dev);
2782 if (!mlx4_is_slave(dev))
2783 mlx4_clear_steering(dev);
2784 mlx4_free_eq_table(dev);
2785 if (mlx4_is_master(dev))
2786 mlx4_multi_func_cleanup(dev);
2787 mlx4_close_hca(dev);
2788 if (mlx4_is_slave(dev))
2789 mlx4_multi_func_cleanup(dev);
2790 mlx4_cmd_cleanup(dev);
2791
2792 if (dev->flags & MLX4_FLAG_MSI_X)
2793 pci_disable_msix(pdev);
2794 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
2795 mlx4_warn(dev, "Disabling SR-IOV\n");
2796 pci_disable_sriov(pdev);
2797 dev->num_vfs = 0;
2798 }
2799
2800 if (!mlx4_is_slave(dev))
2801 mlx4_free_ownership(dev);
2802
2803 kfree(dev->caps.qp0_qkey);
2804 kfree(dev->caps.qp0_tunnel);
2805 kfree(dev->caps.qp0_proxy);
2806 kfree(dev->caps.qp1_tunnel);
2807 kfree(dev->caps.qp1_proxy);
2808 kfree(dev->dev_vfs);
2809
2810 memset(priv, 0, sizeof(*priv));
2811 priv->pci_dev_data = pci_dev_data;
2812 priv->removed = 1;
2813 }
2814
mlx4_remove_one(struct pci_dev * pdev)2815 static void mlx4_remove_one(struct pci_dev *pdev)
2816 {
2817 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2818 struct mlx4_priv *priv = mlx4_priv(dev);
2819
2820 mlx4_unload_one(pdev);
2821 pci_release_regions(pdev);
2822 pci_disable_device(pdev);
2823 kfree(priv);
2824 pci_set_drvdata(pdev, NULL);
2825 }
2826
mlx4_restart_one(struct pci_dev * pdev)2827 int mlx4_restart_one(struct pci_dev *pdev)
2828 {
2829 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2830 struct mlx4_priv *priv = mlx4_priv(dev);
2831 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
2832 int pci_dev_data, err, total_vfs;
2833
2834 pci_dev_data = priv->pci_dev_data;
2835 total_vfs = dev->num_vfs;
2836 memcpy(nvfs, dev->nvfs, sizeof(dev->nvfs));
2837
2838 mlx4_unload_one(pdev);
2839 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv);
2840 if (err) {
2841 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
2842 __func__, pci_name(pdev), err);
2843 return err;
2844 }
2845
2846 return err;
2847 }
2848
2849 static const struct pci_device_id mlx4_pci_table[] = {
2850 /* MT25408 "Hermon" SDR */
2851 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2852 /* MT25408 "Hermon" DDR */
2853 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2854 /* MT25408 "Hermon" QDR */
2855 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2856 /* MT25408 "Hermon" DDR PCIe gen2 */
2857 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2858 /* MT25408 "Hermon" QDR PCIe gen2 */
2859 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2860 /* MT25408 "Hermon" EN 10GigE */
2861 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2862 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2863 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2864 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2865 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2866 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2867 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2868 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2869 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2870 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2871 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2872 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2873 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
2874 /* MT25400 Family [ConnectX-2 Virtual Function] */
2875 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
2876 /* MT27500 Family [ConnectX-3] */
2877 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2878 /* MT27500 Family [ConnectX-3 Virtual Function] */
2879 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
2880 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2881 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2882 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2883 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2884 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2885 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2886 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2887 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2888 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2889 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2890 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2891 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
2892 { 0, }
2893 };
2894
2895 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2896
mlx4_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2897 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2898 pci_channel_state_t state)
2899 {
2900 mlx4_unload_one(pdev);
2901
2902 return state == pci_channel_io_perm_failure ?
2903 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2904 }
2905
mlx4_pci_slot_reset(struct pci_dev * pdev)2906 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2907 {
2908 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2909 struct mlx4_priv *priv = mlx4_priv(dev);
2910 int ret;
2911
2912 ret = __mlx4_init_one(pdev, priv->pci_dev_data, priv);
2913
2914 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2915 }
2916
2917 static const struct pci_error_handlers mlx4_err_handler = {
2918 .error_detected = mlx4_pci_err_detected,
2919 .slot_reset = mlx4_pci_slot_reset,
2920 };
2921
2922 static struct pci_driver mlx4_driver = {
2923 .name = DRV_NAME,
2924 .id_table = mlx4_pci_table,
2925 .probe = mlx4_init_one,
2926 .shutdown = mlx4_unload_one,
2927 .remove = mlx4_remove_one,
2928 .err_handler = &mlx4_err_handler,
2929 };
2930
mlx4_verify_params(void)2931 static int __init mlx4_verify_params(void)
2932 {
2933 if ((log_num_mac < 0) || (log_num_mac > 7)) {
2934 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
2935 return -1;
2936 }
2937
2938 if (log_num_vlan != 0)
2939 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2940 MLX4_LOG_NUM_VLANS);
2941
2942 if (use_prio != 0)
2943 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
2944
2945 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
2946 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
2947 log_mtts_per_seg);
2948 return -1;
2949 }
2950
2951 /* Check if module param for ports type has legal combination */
2952 if (port_type_array[0] == false && port_type_array[1] == true) {
2953 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2954 port_type_array[0] = true;
2955 }
2956
2957 if (mlx4_log_num_mgm_entry_size != -1 &&
2958 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2959 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2960 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2961 mlx4_log_num_mgm_entry_size,
2962 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2963 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2964 return -1;
2965 }
2966
2967 return 0;
2968 }
2969
mlx4_init(void)2970 static int __init mlx4_init(void)
2971 {
2972 int ret;
2973
2974 if (mlx4_verify_params())
2975 return -EINVAL;
2976
2977 mlx4_catas_init();
2978
2979 mlx4_wq = create_singlethread_workqueue("mlx4");
2980 if (!mlx4_wq)
2981 return -ENOMEM;
2982
2983 ret = pci_register_driver(&mlx4_driver);
2984 if (ret < 0)
2985 destroy_workqueue(mlx4_wq);
2986 return ret < 0 ? ret : 0;
2987 }
2988
mlx4_cleanup(void)2989 static void __exit mlx4_cleanup(void)
2990 {
2991 pci_unregister_driver(&mlx4_driver);
2992 destroy_workqueue(mlx4_wq);
2993 }
2994
2995 module_init(mlx4_init);
2996 module_exit(mlx4_cleanup);
2997