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1 /*
2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  *  Rajeshwar Ranga: Interrupt Distribution Unit API's
9  */
10 
11 #ifndef __PLAT_ARCFPGA_SMP_H
12 #define __PLAT_ARCFPGA_SMP_H
13 
14 #ifdef CONFIG_SMP
15 
16 #include <linux/types.h>
17 #include <asm/arcregs.h>
18 
19 #define ARC_AUX_IDU_REG_CMD		0x2000
20 #define ARC_AUX_IDU_REG_PARAM		0x2001
21 
22 #define ARC_AUX_XTL_REG_CMD		0x2002
23 #define ARC_AUX_XTL_REG_PARAM		0x2003
24 
25 #define ARC_REG_MP_BCR			0x2021
26 
27 #define ARC_XTL_CMD_WRITE_PC		0x04
28 #define ARC_XTL_CMD_CLEAR_HALT		0x02
29 
30 /*
31  * Build Configuration Register which identifies the sub-components
32  */
33 struct bcr_mp {
34 #ifdef CONFIG_CPU_BIG_ENDIAN
35 	unsigned int mp_arch:16, pad:5, sdu:1, idu:1, scu:1, ver:8;
36 #else
37 	unsigned int ver:8, scu:1, idu:1, sdu:1, pad:5, mp_arch:16;
38 #endif
39 };
40 
41 /* IDU supports 256 common interrupts */
42 #define NR_IDU_IRQS			256
43 
44 /*
45  * The Aux Regs layout is same bit-by-bit in both BE/LE modes.
46  * However when casted as a bitfield encoded "C" struct, gcc treats it as
47  * memory, generating different code for BE/LE, requiring strcture adj (see
48  * include/asm/arcregs.h)
49  *
50  * However when manually "carving" the value for a Aux, no special handling
51  * of BE is needed because of the property discribed above
52  */
53 #define IDU_SET_COMMAND(irq, cmd)			\
54 do {							\
55 	uint32_t __val;					\
56 	__val = (((irq & 0xFF) << 8) | (cmd & 0xFF));	\
57 	write_aux_reg(ARC_AUX_IDU_REG_CMD, __val);	\
58 } while (0)
59 
60 #define IDU_SET_PARAM(par)  write_aux_reg(ARC_AUX_IDU_REG_PARAM, par)
61 #define IDU_GET_PARAM()     read_aux_reg(ARC_AUX_IDU_REG_PARAM)
62 
63 /* IDU Commands */
64 #define IDU_DISABLE			0x00
65 #define IDU_ENABLE			0x01
66 #define IDU_IRQ_CLEAR			0x02
67 #define IDU_IRQ_ASSERT			0x03
68 #define IDU_IRQ_WMODE			0x04
69 #define IDU_IRQ_STATUS			0x05
70 #define IDU_IRQ_ACK			0x06
71 #define IDU_IRQ_PEND			0x07
72 #define IDU_IRQ_RMODE			0x08
73 #define IDU_IRQ_WBITMASK		0x09
74 #define IDU_IRQ_RBITMASK		0x0A
75 
76 #define idu_enable()		IDU_SET_COMMAND(0, IDU_ENABLE)
77 #define idu_disable()		IDU_SET_COMMAND(0, IDU_DISABLE)
78 
79 #define idu_irq_assert(irq)	IDU_SET_COMMAND((irq), IDU_IRQ_ASSERT)
80 #define idu_irq_clear(irq)	IDU_SET_COMMAND((irq), IDU_IRQ_CLEAR)
81 
82 /* IDU Interrupt Mode - Destination Encoding */
83 #define IDU_IRQ_MOD_DISABLE		0x00
84 #define IDU_IRQ_MOD_ROUND_RECP		0x01
85 #define IDU_IRQ_MOD_TCPU_FIRSTRECP	0x02
86 #define IDU_IRQ_MOD_TCPU_ALLRECP	0x03
87 
88 /* IDU Interrupt Mode  - Triggering Mode */
89 #define IDU_IRQ_MODE_LEVEL_TRIG		0x00
90 #define IDU_IRQ_MODE_PULSE_TRIG		0x01
91 
92 #define IDU_IRQ_MODE_PARAM(dest_mode, trig_mode)   \
93 	(((trig_mode & 0x01) << 15) | (dest_mode & 0xFF))
94 
95 struct idu_irq_config {
96 	uint8_t irq;
97 	uint8_t dest_mode;
98 	uint8_t trig_mode;
99 };
100 
101 struct idu_irq_status {
102 	uint8_t irq;
103 	bool enabled;
104 	bool status;
105 	bool ack;
106 	bool pend;
107 	uint8_t next_rr;
108 };
109 
110 extern void idu_irq_set_tgtcpu(uint8_t irq, uint32_t mask);
111 extern void idu_irq_set_mode(uint8_t irq, uint8_t dest_mode, uint8_t trig_mode);
112 
113 extern void iss_model_init_smp(unsigned int cpu);
114 extern void iss_model_init_early_smp(void);
115 
116 #endif	/* CONFIG_SMP */
117 
118 #endif
119