1 /*
2 * early_printk_intel_mid.c - early consoles for Intel MID platforms
3 *
4 * Copyright (c) 2008-2010, Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11
12 /*
13 * This file implements two early consoles named mrst and hsu.
14 * mrst is based on Maxim3110 spi-uart device, it exists in both
15 * Moorestown and Medfield platforms, while hsu is based on a High
16 * Speed UART device which only exists in the Medfield platform
17 */
18
19 #include <linux/serial_reg.h>
20 #include <linux/serial_mfd.h>
21 #include <linux/kmsg_dump.h>
22 #include <linux/console.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26
27 #include <asm/fixmap.h>
28 #include <asm/pgtable.h>
29 #include <asm/intel-mid.h>
30
31 #define MRST_SPI_TIMEOUT 0x200000
32 #define MRST_REGBASE_SPI0 0xff128000
33 #define MRST_REGBASE_SPI1 0xff128400
34 #define MRST_CLK_SPI0_REG 0xff11d86c
35
36 /* Bit fields in CTRLR0 */
37 #define SPI_DFS_OFFSET 0
38
39 #define SPI_FRF_OFFSET 4
40 #define SPI_FRF_SPI 0x0
41 #define SPI_FRF_SSP 0x1
42 #define SPI_FRF_MICROWIRE 0x2
43 #define SPI_FRF_RESV 0x3
44
45 #define SPI_MODE_OFFSET 6
46 #define SPI_SCPH_OFFSET 6
47 #define SPI_SCOL_OFFSET 7
48 #define SPI_TMOD_OFFSET 8
49 #define SPI_TMOD_TR 0x0 /* xmit & recv */
50 #define SPI_TMOD_TO 0x1 /* xmit only */
51 #define SPI_TMOD_RO 0x2 /* recv only */
52 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
53
54 #define SPI_SLVOE_OFFSET 10
55 #define SPI_SRL_OFFSET 11
56 #define SPI_CFS_OFFSET 12
57
58 /* Bit fields in SR, 7 bits */
59 #define SR_MASK 0x7f /* cover 7 bits */
60 #define SR_BUSY (1 << 0)
61 #define SR_TF_NOT_FULL (1 << 1)
62 #define SR_TF_EMPT (1 << 2)
63 #define SR_RF_NOT_EMPT (1 << 3)
64 #define SR_RF_FULL (1 << 4)
65 #define SR_TX_ERR (1 << 5)
66 #define SR_DCOL (1 << 6)
67
68 struct dw_spi_reg {
69 u32 ctrl0;
70 u32 ctrl1;
71 u32 ssienr;
72 u32 mwcr;
73 u32 ser;
74 u32 baudr;
75 u32 txfltr;
76 u32 rxfltr;
77 u32 txflr;
78 u32 rxflr;
79 u32 sr;
80 u32 imr;
81 u32 isr;
82 u32 risr;
83 u32 txoicr;
84 u32 rxoicr;
85 u32 rxuicr;
86 u32 msticr;
87 u32 icr;
88 u32 dmacr;
89 u32 dmatdlr;
90 u32 dmardlr;
91 u32 idr;
92 u32 version;
93
94 /* Currently operates as 32 bits, though only the low 16 bits matter */
95 u32 dr;
96 } __packed;
97
98 #define dw_readl(dw, name) __raw_readl(&(dw)->name)
99 #define dw_writel(dw, name, val) __raw_writel((val), &(dw)->name)
100
101 /* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
102 static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
103
104 static u32 *pclk_spi0;
105 /* Always contains an accessible address, start with 0 */
106 static struct dw_spi_reg *pspi;
107
108 static struct kmsg_dumper dw_dumper;
109 static int dumper_registered;
110
dw_kmsg_dump(struct kmsg_dumper * dumper,enum kmsg_dump_reason reason)111 static void dw_kmsg_dump(struct kmsg_dumper *dumper,
112 enum kmsg_dump_reason reason)
113 {
114 static char line[1024];
115 size_t len;
116
117 /* When run to this, we'd better re-init the HW */
118 mrst_early_console_init();
119
120 while (kmsg_dump_get_line(dumper, true, line, sizeof(line), &len))
121 early_mrst_console.write(&early_mrst_console, line, len);
122 }
123
124 /* Set the ratio rate to 115200, 8n1, IRQ disabled */
max3110_write_config(void)125 static void max3110_write_config(void)
126 {
127 u16 config;
128
129 config = 0xc001;
130 dw_writel(pspi, dr, config);
131 }
132
133 /* Translate char to a eligible word and send to max3110 */
max3110_write_data(char c)134 static void max3110_write_data(char c)
135 {
136 u16 data;
137
138 data = 0x8000 | c;
139 dw_writel(pspi, dr, data);
140 }
141
mrst_early_console_init(void)142 void mrst_early_console_init(void)
143 {
144 u32 ctrlr0 = 0;
145 u32 spi0_cdiv;
146 u32 freq; /* Freqency info only need be searched once */
147
148 /* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
149 pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
150 MRST_CLK_SPI0_REG);
151 spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
152 freq = 100000000 / (spi0_cdiv + 1);
153
154 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL)
155 mrst_spi_paddr = MRST_REGBASE_SPI1;
156
157 pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
158 mrst_spi_paddr);
159
160 /* Disable SPI controller */
161 dw_writel(pspi, ssienr, 0);
162
163 /* Set control param, 8 bits, transmit only mode */
164 ctrlr0 = dw_readl(pspi, ctrl0);
165
166 ctrlr0 &= 0xfcc0;
167 ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
168 | (SPI_TMOD_TO << SPI_TMOD_OFFSET);
169 dw_writel(pspi, ctrl0, ctrlr0);
170
171 /*
172 * Change the spi0 clk to comply with 115200 bps, use 100000 to
173 * calculate the clk dividor to make the clock a little slower
174 * than real baud rate.
175 */
176 dw_writel(pspi, baudr, freq/100000);
177
178 /* Disable all INT for early phase */
179 dw_writel(pspi, imr, 0x0);
180
181 /* Set the cs to spi-uart */
182 dw_writel(pspi, ser, 0x2);
183
184 /* Enable the HW, the last step for HW init */
185 dw_writel(pspi, ssienr, 0x1);
186
187 /* Set the default configuration */
188 max3110_write_config();
189
190 /* Register the kmsg dumper */
191 if (!dumper_registered) {
192 dw_dumper.dump = dw_kmsg_dump;
193 kmsg_dump_register(&dw_dumper);
194 dumper_registered = 1;
195 }
196 }
197
198 /* Slave select should be called in the read/write function */
early_mrst_spi_putc(char c)199 static void early_mrst_spi_putc(char c)
200 {
201 unsigned int timeout;
202 u32 sr;
203
204 timeout = MRST_SPI_TIMEOUT;
205 /* Early putc needs to make sure the TX FIFO is not full */
206 while (--timeout) {
207 sr = dw_readl(pspi, sr);
208 if (!(sr & SR_TF_NOT_FULL))
209 cpu_relax();
210 else
211 break;
212 }
213
214 if (!timeout)
215 pr_warn("MRST earlycon: timed out\n");
216 else
217 max3110_write_data(c);
218 }
219
220 /* Early SPI only uses polling mode */
early_mrst_spi_write(struct console * con,const char * str,unsigned n)221 static void early_mrst_spi_write(struct console *con, const char *str,
222 unsigned n)
223 {
224 int i;
225
226 for (i = 0; i < n && *str; i++) {
227 if (*str == '\n')
228 early_mrst_spi_putc('\r');
229 early_mrst_spi_putc(*str);
230 str++;
231 }
232 }
233
234 struct console early_mrst_console = {
235 .name = "earlymrst",
236 .write = early_mrst_spi_write,
237 .flags = CON_PRINTBUFFER,
238 .index = -1,
239 };
240
241 /*
242 * Following is the early console based on Medfield HSU (High
243 * Speed UART) device.
244 */
245 #define HSU_PORT_BASE 0xffa28080
246
247 static void __iomem *phsu;
248
hsu_early_console_init(const char * s)249 void hsu_early_console_init(const char *s)
250 {
251 unsigned long paddr, port = 0;
252 u8 lcr;
253
254 /*
255 * Select the early HSU console port if specified by user in the
256 * kernel command line.
257 */
258 if (*s && !kstrtoul(s, 10, &port))
259 port = clamp_val(port, 0, 2);
260
261 paddr = HSU_PORT_BASE + port * 0x80;
262 phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr);
263
264 /* Disable FIFO */
265 writeb(0x0, phsu + UART_FCR);
266
267 /* Set to default 115200 bps, 8n1 */
268 lcr = readb(phsu + UART_LCR);
269 writeb((0x80 | lcr), phsu + UART_LCR);
270 writeb(0x18, phsu + UART_DLL);
271 writeb(lcr, phsu + UART_LCR);
272 writel(0x3600, phsu + UART_MUL*4);
273
274 writeb(0x8, phsu + UART_MCR);
275 writeb(0x7, phsu + UART_FCR);
276 writeb(0x3, phsu + UART_LCR);
277
278 /* Clear IRQ status */
279 readb(phsu + UART_LSR);
280 readb(phsu + UART_RX);
281 readb(phsu + UART_IIR);
282 readb(phsu + UART_MSR);
283
284 /* Enable FIFO */
285 writeb(0x7, phsu + UART_FCR);
286 }
287
288 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
289
early_hsu_putc(char ch)290 static void early_hsu_putc(char ch)
291 {
292 unsigned int timeout = 10000; /* 10ms */
293 u8 status;
294
295 while (--timeout) {
296 status = readb(phsu + UART_LSR);
297 if (status & BOTH_EMPTY)
298 break;
299 udelay(1);
300 }
301
302 /* Only write the char when there was no timeout */
303 if (timeout)
304 writeb(ch, phsu + UART_TX);
305 }
306
early_hsu_write(struct console * con,const char * str,unsigned n)307 static void early_hsu_write(struct console *con, const char *str, unsigned n)
308 {
309 int i;
310
311 for (i = 0; i < n && *str; i++) {
312 if (*str == '\n')
313 early_hsu_putc('\r');
314 early_hsu_putc(*str);
315 str++;
316 }
317 }
318
319 struct console early_hsu_console = {
320 .name = "earlyhsu",
321 .write = early_hsu_write,
322 .flags = CON_PRINTBUFFER,
323 .index = -1,
324 };
325