1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include "../core.h"
25 #include "pinctrl-mxs.h"
26
27 #define SUFFIX_LEN 4
28
29 struct mxs_pinctrl_data {
30 struct device *dev;
31 struct pinctrl_dev *pctl;
32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc;
34 };
35
mxs_get_groups_count(struct pinctrl_dev * pctldev)36 static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37 {
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->ngroups;
41 }
42
mxs_get_group_name(struct pinctrl_dev * pctldev,unsigned group)43 static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group)
45 {
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 return d->soc->groups[group].name;
49 }
50
mxs_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)51 static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins)
53 {
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins;
58
59 return 0;
60 }
61
mxs_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)62 static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset)
64 {
65 seq_printf(s, " %s", dev_name(pctldev->dev));
66 }
67
mxs_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)68 static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps)
71 {
72 struct pinctrl_map *new_map;
73 char *group = NULL;
74 unsigned new_num = 1;
75 unsigned long config = 0;
76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN;
78 bool purecfg = false;
79 u32 val, reg;
80 int ret, i = 0;
81
82 /* Check for pin config node which has no 'reg' property */
83 if (of_property_read_u32(np, "reg", ®))
84 purecfg = true;
85
86 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
87 if (!ret)
88 config = val | MA_PRESENT;
89 ret = of_property_read_u32(np, "fsl,voltage", &val);
90 if (!ret)
91 config |= val << VOL_SHIFT | VOL_PRESENT;
92 ret = of_property_read_u32(np, "fsl,pull-up", &val);
93 if (!ret)
94 config |= val << PULL_SHIFT | PULL_PRESENT;
95
96 /* Check for group node which has both mux and config settings */
97 if (!purecfg && config)
98 new_num = 2;
99
100 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
101 if (!new_map)
102 return -ENOMEM;
103
104 if (!purecfg) {
105 new_map[i].type = PIN_MAP_TYPE_MUX_GROUP;
106 new_map[i].data.mux.function = np->name;
107
108 /* Compose group name */
109 group = kzalloc(length, GFP_KERNEL);
110 if (!group) {
111 ret = -ENOMEM;
112 goto free;
113 }
114 snprintf(group, length, "%s.%d", np->name, reg);
115 new_map[i].data.mux.group = group;
116 i++;
117 }
118
119 if (config) {
120 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
121 if (!pconfig) {
122 ret = -ENOMEM;
123 goto free_group;
124 }
125
126 new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
127 new_map[i].data.configs.group_or_pin = purecfg ? np->name :
128 group;
129 new_map[i].data.configs.configs = pconfig;
130 new_map[i].data.configs.num_configs = 1;
131 }
132
133 *map = new_map;
134 *num_maps = new_num;
135
136 return 0;
137
138 free_group:
139 if (!purecfg)
140 kfree(group);
141 free:
142 kfree(new_map);
143 return ret;
144 }
145
mxs_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)146 static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
147 struct pinctrl_map *map, unsigned num_maps)
148 {
149 u32 i;
150
151 for (i = 0; i < num_maps; i++) {
152 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
153 kfree(map[i].data.mux.group);
154 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
155 kfree(map[i].data.configs.configs);
156 }
157
158 kfree(map);
159 }
160
161 static const struct pinctrl_ops mxs_pinctrl_ops = {
162 .get_groups_count = mxs_get_groups_count,
163 .get_group_name = mxs_get_group_name,
164 .get_group_pins = mxs_get_group_pins,
165 .pin_dbg_show = mxs_pin_dbg_show,
166 .dt_node_to_map = mxs_dt_node_to_map,
167 .dt_free_map = mxs_dt_free_map,
168 };
169
mxs_pinctrl_get_funcs_count(struct pinctrl_dev * pctldev)170 static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
171 {
172 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
173
174 return d->soc->nfunctions;
175 }
176
mxs_pinctrl_get_func_name(struct pinctrl_dev * pctldev,unsigned function)177 static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
178 unsigned function)
179 {
180 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
181
182 return d->soc->functions[function].name;
183 }
184
mxs_pinctrl_get_func_groups(struct pinctrl_dev * pctldev,unsigned group,const char * const ** groups,unsigned * const num_groups)185 static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
186 unsigned group,
187 const char * const **groups,
188 unsigned * const num_groups)
189 {
190 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
191
192 *groups = d->soc->functions[group].groups;
193 *num_groups = d->soc->functions[group].ngroups;
194
195 return 0;
196 }
197
mxs_pinctrl_rmwl(u32 value,u32 mask,u8 shift,void __iomem * reg)198 static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg)
199 {
200 u32 tmp;
201
202 tmp = readl(reg);
203 tmp &= ~(mask << shift);
204 tmp |= value << shift;
205 writel(tmp, reg);
206 }
207
mxs_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)208 static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
209 unsigned group)
210 {
211 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
212 struct mxs_group *g = &d->soc->groups[group];
213 void __iomem *reg;
214 u8 bank, shift;
215 u16 pin;
216 u32 i;
217
218 for (i = 0; i < g->npins; i++) {
219 bank = PINID_TO_BANK(g->pins[i]);
220 pin = PINID_TO_PIN(g->pins[i]);
221 reg = d->base + d->soc->regs->muxsel;
222 reg += bank * 0x20 + pin / 16 * 0x10;
223 shift = pin % 16 * 2;
224
225 mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg);
226 }
227
228 return 0;
229 }
230
231 static const struct pinmux_ops mxs_pinmux_ops = {
232 .get_functions_count = mxs_pinctrl_get_funcs_count,
233 .get_function_name = mxs_pinctrl_get_func_name,
234 .get_function_groups = mxs_pinctrl_get_func_groups,
235 .set_mux = mxs_pinctrl_set_mux,
236 };
237
mxs_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)238 static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
239 unsigned pin, unsigned long *config)
240 {
241 return -ENOTSUPP;
242 }
243
mxs_pinconf_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)244 static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
245 unsigned pin, unsigned long *configs,
246 unsigned num_configs)
247 {
248 return -ENOTSUPP;
249 }
250
mxs_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned group,unsigned long * config)251 static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
252 unsigned group, unsigned long *config)
253 {
254 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
255
256 *config = d->soc->groups[group].config;
257
258 return 0;
259 }
260
mxs_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)261 static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
262 unsigned group, unsigned long *configs,
263 unsigned num_configs)
264 {
265 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
266 struct mxs_group *g = &d->soc->groups[group];
267 void __iomem *reg;
268 u8 ma, vol, pull, bank, shift;
269 u16 pin;
270 u32 i;
271 int n;
272 unsigned long config;
273
274 for (n = 0; n < num_configs; n++) {
275 config = configs[n];
276
277 ma = CONFIG_TO_MA(config);
278 vol = CONFIG_TO_VOL(config);
279 pull = CONFIG_TO_PULL(config);
280
281 for (i = 0; i < g->npins; i++) {
282 bank = PINID_TO_BANK(g->pins[i]);
283 pin = PINID_TO_PIN(g->pins[i]);
284
285 /* drive */
286 reg = d->base + d->soc->regs->drive;
287 reg += bank * 0x40 + pin / 8 * 0x10;
288
289 /* mA */
290 if (config & MA_PRESENT) {
291 shift = pin % 8 * 4;
292 mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
293 }
294
295 /* vol */
296 if (config & VOL_PRESENT) {
297 shift = pin % 8 * 4 + 2;
298 if (vol)
299 writel(1 << shift, reg + SET);
300 else
301 writel(1 << shift, reg + CLR);
302 }
303
304 /* pull */
305 if (config & PULL_PRESENT) {
306 reg = d->base + d->soc->regs->pull;
307 reg += bank * 0x10;
308 shift = pin;
309 if (pull)
310 writel(1 << shift, reg + SET);
311 else
312 writel(1 << shift, reg + CLR);
313 }
314 }
315
316 /* cache the config value for mxs_pinconf_group_get() */
317 g->config = config;
318
319 } /* for each config */
320
321 return 0;
322 }
323
mxs_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin)324 static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
325 struct seq_file *s, unsigned pin)
326 {
327 /* Not support */
328 }
329
mxs_pinconf_group_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned group)330 static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
331 struct seq_file *s, unsigned group)
332 {
333 unsigned long config;
334
335 if (!mxs_pinconf_group_get(pctldev, group, &config))
336 seq_printf(s, "0x%lx", config);
337 }
338
339 static const struct pinconf_ops mxs_pinconf_ops = {
340 .pin_config_get = mxs_pinconf_get,
341 .pin_config_set = mxs_pinconf_set,
342 .pin_config_group_get = mxs_pinconf_group_get,
343 .pin_config_group_set = mxs_pinconf_group_set,
344 .pin_config_dbg_show = mxs_pinconf_dbg_show,
345 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
346 };
347
348 static struct pinctrl_desc mxs_pinctrl_desc = {
349 .pctlops = &mxs_pinctrl_ops,
350 .pmxops = &mxs_pinmux_ops,
351 .confops = &mxs_pinconf_ops,
352 .owner = THIS_MODULE,
353 };
354
mxs_pinctrl_parse_group(struct platform_device * pdev,struct device_node * np,int idx,const char ** out_name)355 static int mxs_pinctrl_parse_group(struct platform_device *pdev,
356 struct device_node *np, int idx,
357 const char **out_name)
358 {
359 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
360 struct mxs_group *g = &d->soc->groups[idx];
361 struct property *prop;
362 const char *propname = "fsl,pinmux-ids";
363 char *group;
364 int length = strlen(np->name) + SUFFIX_LEN;
365 u32 val, i;
366
367 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
368 if (!group)
369 return -ENOMEM;
370 if (of_property_read_u32(np, "reg", &val))
371 snprintf(group, length, "%s", np->name);
372 else
373 snprintf(group, length, "%s.%d", np->name, val);
374 g->name = group;
375
376 prop = of_find_property(np, propname, &length);
377 if (!prop)
378 return -EINVAL;
379 g->npins = length / sizeof(u32);
380
381 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
382 GFP_KERNEL);
383 if (!g->pins)
384 return -ENOMEM;
385
386 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
387 GFP_KERNEL);
388 if (!g->muxsel)
389 return -ENOMEM;
390
391 of_property_read_u32_array(np, propname, g->pins, g->npins);
392 for (i = 0; i < g->npins; i++) {
393 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
394 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
395 }
396
397 if (out_name)
398 *out_name = g->name;
399
400 return 0;
401 }
402
mxs_pinctrl_probe_dt(struct platform_device * pdev,struct mxs_pinctrl_data * d)403 static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
404 struct mxs_pinctrl_data *d)
405 {
406 struct mxs_pinctrl_soc_data *soc = d->soc;
407 struct device_node *np = pdev->dev.of_node;
408 struct device_node *child;
409 struct mxs_function *f;
410 const char *gpio_compat = "fsl,mxs-gpio";
411 const char *fn, *fnull = "";
412 int i = 0, idxf = 0, idxg = 0;
413 int ret;
414 u32 val;
415
416 child = of_get_next_child(np, NULL);
417 if (!child) {
418 dev_err(&pdev->dev, "no group is defined\n");
419 return -ENOENT;
420 }
421
422 /* Count total functions and groups */
423 fn = fnull;
424 for_each_child_of_node(np, child) {
425 if (of_device_is_compatible(child, gpio_compat))
426 continue;
427 soc->ngroups++;
428 /* Skip pure pinconf node */
429 if (of_property_read_u32(child, "reg", &val))
430 continue;
431 if (strcmp(fn, child->name)) {
432 fn = child->name;
433 soc->nfunctions++;
434 }
435 }
436
437 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
438 sizeof(*soc->functions), GFP_KERNEL);
439 if (!soc->functions)
440 return -ENOMEM;
441
442 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
443 sizeof(*soc->groups), GFP_KERNEL);
444 if (!soc->groups)
445 return -ENOMEM;
446
447 /* Count groups for each function */
448 fn = fnull;
449 f = &soc->functions[idxf];
450 for_each_child_of_node(np, child) {
451 if (of_device_is_compatible(child, gpio_compat))
452 continue;
453 if (of_property_read_u32(child, "reg", &val))
454 continue;
455 if (strcmp(fn, child->name)) {
456 f = &soc->functions[idxf++];
457 f->name = fn = child->name;
458 }
459 f->ngroups++;
460 };
461
462 /* Get groups for each function */
463 idxf = 0;
464 fn = fnull;
465 for_each_child_of_node(np, child) {
466 if (of_device_is_compatible(child, gpio_compat))
467 continue;
468 if (of_property_read_u32(child, "reg", &val)) {
469 ret = mxs_pinctrl_parse_group(pdev, child,
470 idxg++, NULL);
471 if (ret)
472 return ret;
473 continue;
474 }
475
476 if (strcmp(fn, child->name)) {
477 f = &soc->functions[idxf++];
478 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
479 sizeof(*f->groups),
480 GFP_KERNEL);
481 if (!f->groups)
482 return -ENOMEM;
483 fn = child->name;
484 i = 0;
485 }
486 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
487 &f->groups[i++]);
488 if (ret)
489 return ret;
490 }
491
492 return 0;
493 }
494
mxs_pinctrl_probe(struct platform_device * pdev,struct mxs_pinctrl_soc_data * soc)495 int mxs_pinctrl_probe(struct platform_device *pdev,
496 struct mxs_pinctrl_soc_data *soc)
497 {
498 struct device_node *np = pdev->dev.of_node;
499 struct mxs_pinctrl_data *d;
500 int ret;
501
502 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
503 if (!d)
504 return -ENOMEM;
505
506 d->dev = &pdev->dev;
507 d->soc = soc;
508
509 d->base = of_iomap(np, 0);
510 if (!d->base)
511 return -EADDRNOTAVAIL;
512
513 mxs_pinctrl_desc.pins = d->soc->pins;
514 mxs_pinctrl_desc.npins = d->soc->npins;
515 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
516
517 platform_set_drvdata(pdev, d);
518
519 ret = mxs_pinctrl_probe_dt(pdev, d);
520 if (ret) {
521 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
522 goto err;
523 }
524
525 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
526 if (!d->pctl) {
527 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
528 ret = -EINVAL;
529 goto err;
530 }
531
532 return 0;
533
534 err:
535 iounmap(d->base);
536 return ret;
537 }
538 EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
539
mxs_pinctrl_remove(struct platform_device * pdev)540 int mxs_pinctrl_remove(struct platform_device *pdev)
541 {
542 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
543
544 pinctrl_unregister(d->pctl);
545 iounmap(d->base);
546
547 return 0;
548 }
549 EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
550