1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/client.h>
26 #include <core/engctx.h>
27 #include <core/ramht.h>
28 #include <nvif/unpack.h>
29 #include <nvif/class.h>
30
31 #include <subdev/timer.h>
32 #include <subdev/bar.h>
33
34 #include <engine/dmaobj.h>
35 #include <engine/fifo.h>
36
37 #include "nv04.h"
38 #include "nv50.h"
39
40 /*******************************************************************************
41 * FIFO channel objects
42 ******************************************************************************/
43
44 static void
nv50_fifo_playlist_update_locked(struct nv50_fifo_priv * priv)45 nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
46 {
47 struct nouveau_bar *bar = nouveau_bar(priv);
48 struct nouveau_gpuobj *cur;
49 int i, p;
50
51 cur = priv->playlist[priv->cur_playlist];
52 priv->cur_playlist = !priv->cur_playlist;
53
54 for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
55 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
56 nv_wo32(cur, p++ * 4, i);
57 }
58
59 bar->flush(bar);
60
61 nv_wr32(priv, 0x0032f4, cur->addr >> 12);
62 nv_wr32(priv, 0x0032ec, p);
63 nv_wr32(priv, 0x002500, 0x00000101);
64 }
65
66 void
nv50_fifo_playlist_update(struct nv50_fifo_priv * priv)67 nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
68 {
69 mutex_lock(&nv_subdev(priv)->mutex);
70 nv50_fifo_playlist_update_locked(priv);
71 mutex_unlock(&nv_subdev(priv)->mutex);
72 }
73
74 static int
nv50_fifo_context_attach(struct nouveau_object * parent,struct nouveau_object * object)75 nv50_fifo_context_attach(struct nouveau_object *parent,
76 struct nouveau_object *object)
77 {
78 struct nouveau_bar *bar = nouveau_bar(parent);
79 struct nv50_fifo_base *base = (void *)parent->parent;
80 struct nouveau_gpuobj *ectx = (void *)object;
81 u64 limit = ectx->addr + ectx->size - 1;
82 u64 start = ectx->addr;
83 u32 addr;
84
85 switch (nv_engidx(object->engine)) {
86 case NVDEV_ENGINE_SW : return 0;
87 case NVDEV_ENGINE_GR : addr = 0x0000; break;
88 case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
89 default:
90 return -EINVAL;
91 }
92
93 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
94 nv_wo32(base->eng, addr + 0x00, 0x00190000);
95 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
96 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
97 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
98 upper_32_bits(start));
99 nv_wo32(base->eng, addr + 0x10, 0x00000000);
100 nv_wo32(base->eng, addr + 0x14, 0x00000000);
101 bar->flush(bar);
102 return 0;
103 }
104
105 static int
nv50_fifo_context_detach(struct nouveau_object * parent,bool suspend,struct nouveau_object * object)106 nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
107 struct nouveau_object *object)
108 {
109 struct nouveau_bar *bar = nouveau_bar(parent);
110 struct nv50_fifo_priv *priv = (void *)parent->engine;
111 struct nv50_fifo_base *base = (void *)parent->parent;
112 struct nv50_fifo_chan *chan = (void *)parent;
113 u32 addr, me;
114 int ret = 0;
115
116 switch (nv_engidx(object->engine)) {
117 case NVDEV_ENGINE_SW : return 0;
118 case NVDEV_ENGINE_GR : addr = 0x0000; break;
119 case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
120 default:
121 return -EINVAL;
122 }
123
124 /* HW bug workaround:
125 *
126 * PFIFO will hang forever if the connected engines don't report
127 * that they've processed the context switch request.
128 *
129 * In order for the kickoff to work, we need to ensure all the
130 * connected engines are in a state where they can answer.
131 *
132 * Newer chipsets don't seem to suffer from this issue, and well,
133 * there's also a "ignore these engines" bitmask reg we can use
134 * if we hit the issue there..
135 */
136 me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
137
138 /* do the kickoff... */
139 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
140 if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
141 nv_error(priv, "channel %d [%s] unload timeout\n",
142 chan->base.chid, nouveau_client_name(chan));
143 if (suspend)
144 ret = -EBUSY;
145 }
146 nv_wr32(priv, 0x00b860, me);
147
148 if (ret == 0) {
149 nv_wo32(base->eng, addr + 0x00, 0x00000000);
150 nv_wo32(base->eng, addr + 0x04, 0x00000000);
151 nv_wo32(base->eng, addr + 0x08, 0x00000000);
152 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
153 nv_wo32(base->eng, addr + 0x10, 0x00000000);
154 nv_wo32(base->eng, addr + 0x14, 0x00000000);
155 bar->flush(bar);
156 }
157
158 return ret;
159 }
160
161 static int
nv50_fifo_object_attach(struct nouveau_object * parent,struct nouveau_object * object,u32 handle)162 nv50_fifo_object_attach(struct nouveau_object *parent,
163 struct nouveau_object *object, u32 handle)
164 {
165 struct nv50_fifo_chan *chan = (void *)parent;
166 u32 context;
167
168 if (nv_iclass(object, NV_GPUOBJ_CLASS))
169 context = nv_gpuobj(object)->node->offset >> 4;
170 else
171 context = 0x00000004; /* just non-zero */
172
173 switch (nv_engidx(object->engine)) {
174 case NVDEV_ENGINE_DMAOBJ:
175 case NVDEV_ENGINE_SW : context |= 0x00000000; break;
176 case NVDEV_ENGINE_GR : context |= 0x00100000; break;
177 case NVDEV_ENGINE_MPEG : context |= 0x00200000; break;
178 default:
179 return -EINVAL;
180 }
181
182 return nouveau_ramht_insert(chan->ramht, 0, handle, context);
183 }
184
185 void
nv50_fifo_object_detach(struct nouveau_object * parent,int cookie)186 nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
187 {
188 struct nv50_fifo_chan *chan = (void *)parent;
189 nouveau_ramht_remove(chan->ramht, cookie);
190 }
191
192 static int
nv50_fifo_chan_ctor_dma(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)193 nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
194 struct nouveau_object *engine,
195 struct nouveau_oclass *oclass, void *data, u32 size,
196 struct nouveau_object **pobject)
197 {
198 union {
199 struct nv03_channel_dma_v0 v0;
200 } *args = data;
201 struct nouveau_bar *bar = nouveau_bar(parent);
202 struct nv50_fifo_base *base = (void *)parent;
203 struct nv50_fifo_chan *chan;
204 int ret;
205
206 nv_ioctl(parent, "create channel dma size %d\n", size);
207 if (nvif_unpack(args->v0, 0, 0, false)) {
208 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
209 "offset %016llx\n", args->v0.version,
210 args->v0.pushbuf, args->v0.offset);
211 } else
212 return ret;
213
214 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
215 0x2000, args->v0.pushbuf,
216 (1ULL << NVDEV_ENGINE_DMAOBJ) |
217 (1ULL << NVDEV_ENGINE_SW) |
218 (1ULL << NVDEV_ENGINE_GR) |
219 (1ULL << NVDEV_ENGINE_MPEG), &chan);
220 *pobject = nv_object(chan);
221 if (ret)
222 return ret;
223
224 args->v0.chid = chan->base.chid;
225
226 nv_parent(chan)->context_attach = nv50_fifo_context_attach;
227 nv_parent(chan)->context_detach = nv50_fifo_context_detach;
228 nv_parent(chan)->object_attach = nv50_fifo_object_attach;
229 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
230
231 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
232 &chan->ramht);
233 if (ret)
234 return ret;
235
236 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
237 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));
238 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));
239 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));
240 nv_wo32(base->ramfc, 0x3c, 0x003f6078);
241 nv_wo32(base->ramfc, 0x44, 0x01003fff);
242 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
243 nv_wo32(base->ramfc, 0x4c, 0xffffffff);
244 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
245 nv_wo32(base->ramfc, 0x78, 0x00000000);
246 nv_wo32(base->ramfc, 0x7c, 0x30000001);
247 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
248 (4 << 24) /* SEARCH_FULL */ |
249 (chan->ramht->base.node->offset >> 4));
250 bar->flush(bar);
251 return 0;
252 }
253
254 static int
nv50_fifo_chan_ctor_ind(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)255 nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
256 struct nouveau_object *engine,
257 struct nouveau_oclass *oclass, void *data, u32 size,
258 struct nouveau_object **pobject)
259 {
260 union {
261 struct nv50_channel_gpfifo_v0 v0;
262 } *args = data;
263 struct nouveau_bar *bar = nouveau_bar(parent);
264 struct nv50_fifo_base *base = (void *)parent;
265 struct nv50_fifo_chan *chan;
266 u64 ioffset, ilength;
267 int ret;
268
269 nv_ioctl(parent, "create channel gpfifo size %d\n", size);
270 if (nvif_unpack(args->v0, 0, 0, false)) {
271 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
272 "ioffset %016llx ilength %08x\n",
273 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
274 args->v0.ilength);
275 } else
276 return ret;
277
278 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
279 0x2000, args->v0.pushbuf,
280 (1ULL << NVDEV_ENGINE_DMAOBJ) |
281 (1ULL << NVDEV_ENGINE_SW) |
282 (1ULL << NVDEV_ENGINE_GR) |
283 (1ULL << NVDEV_ENGINE_MPEG), &chan);
284 *pobject = nv_object(chan);
285 if (ret)
286 return ret;
287
288 args->v0.chid = chan->base.chid;
289
290 nv_parent(chan)->context_attach = nv50_fifo_context_attach;
291 nv_parent(chan)->context_detach = nv50_fifo_context_detach;
292 nv_parent(chan)->object_attach = nv50_fifo_object_attach;
293 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
294
295 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
296 &chan->ramht);
297 if (ret)
298 return ret;
299
300 ioffset = args->v0.ioffset;
301 ilength = order_base_2(args->v0.ilength / 8);
302
303 nv_wo32(base->ramfc, 0x3c, 0x403f6078);
304 nv_wo32(base->ramfc, 0x44, 0x01003fff);
305 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
306 nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
307 nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
308 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
309 nv_wo32(base->ramfc, 0x78, 0x00000000);
310 nv_wo32(base->ramfc, 0x7c, 0x30000001);
311 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
312 (4 << 24) /* SEARCH_FULL */ |
313 (chan->ramht->base.node->offset >> 4));
314 bar->flush(bar);
315 return 0;
316 }
317
318 void
nv50_fifo_chan_dtor(struct nouveau_object * object)319 nv50_fifo_chan_dtor(struct nouveau_object *object)
320 {
321 struct nv50_fifo_chan *chan = (void *)object;
322 nouveau_ramht_ref(NULL, &chan->ramht);
323 nouveau_fifo_channel_destroy(&chan->base);
324 }
325
326 static int
nv50_fifo_chan_init(struct nouveau_object * object)327 nv50_fifo_chan_init(struct nouveau_object *object)
328 {
329 struct nv50_fifo_priv *priv = (void *)object->engine;
330 struct nv50_fifo_base *base = (void *)object->parent;
331 struct nv50_fifo_chan *chan = (void *)object;
332 struct nouveau_gpuobj *ramfc = base->ramfc;
333 u32 chid = chan->base.chid;
334 int ret;
335
336 ret = nouveau_fifo_channel_init(&chan->base);
337 if (ret)
338 return ret;
339
340 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
341 nv50_fifo_playlist_update(priv);
342 return 0;
343 }
344
345 int
nv50_fifo_chan_fini(struct nouveau_object * object,bool suspend)346 nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
347 {
348 struct nv50_fifo_priv *priv = (void *)object->engine;
349 struct nv50_fifo_chan *chan = (void *)object;
350 u32 chid = chan->base.chid;
351
352 /* remove channel from playlist, fifo will unload context */
353 nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
354 nv50_fifo_playlist_update(priv);
355 nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
356
357 return nouveau_fifo_channel_fini(&chan->base, suspend);
358 }
359
360 static struct nouveau_ofuncs
361 nv50_fifo_ofuncs_dma = {
362 .ctor = nv50_fifo_chan_ctor_dma,
363 .dtor = nv50_fifo_chan_dtor,
364 .init = nv50_fifo_chan_init,
365 .fini = nv50_fifo_chan_fini,
366 .map = _nouveau_fifo_channel_map,
367 .rd32 = _nouveau_fifo_channel_rd32,
368 .wr32 = _nouveau_fifo_channel_wr32,
369 .ntfy = _nouveau_fifo_channel_ntfy
370 };
371
372 static struct nouveau_ofuncs
373 nv50_fifo_ofuncs_ind = {
374 .ctor = nv50_fifo_chan_ctor_ind,
375 .dtor = nv50_fifo_chan_dtor,
376 .init = nv50_fifo_chan_init,
377 .fini = nv50_fifo_chan_fini,
378 .map = _nouveau_fifo_channel_map,
379 .rd32 = _nouveau_fifo_channel_rd32,
380 .wr32 = _nouveau_fifo_channel_wr32,
381 .ntfy = _nouveau_fifo_channel_ntfy
382 };
383
384 static struct nouveau_oclass
385 nv50_fifo_sclass[] = {
386 { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma },
387 { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind },
388 {}
389 };
390
391 /*******************************************************************************
392 * FIFO context - basically just the instmem reserved for the channel
393 ******************************************************************************/
394
395 static int
nv50_fifo_context_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)396 nv50_fifo_context_ctor(struct nouveau_object *parent,
397 struct nouveau_object *engine,
398 struct nouveau_oclass *oclass, void *data, u32 size,
399 struct nouveau_object **pobject)
400 {
401 struct nv50_fifo_base *base;
402 int ret;
403
404 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
405 0x1000, NVOBJ_FLAG_HEAP, &base);
406 *pobject = nv_object(base);
407 if (ret)
408 return ret;
409
410 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200,
411 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
412 if (ret)
413 return ret;
414
415 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,
416 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
417 if (ret)
418 return ret;
419
420 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,
421 &base->pgd);
422 if (ret)
423 return ret;
424
425 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
426 if (ret)
427 return ret;
428
429 return 0;
430 }
431
432 void
nv50_fifo_context_dtor(struct nouveau_object * object)433 nv50_fifo_context_dtor(struct nouveau_object *object)
434 {
435 struct nv50_fifo_base *base = (void *)object;
436 nouveau_vm_ref(NULL, &base->vm, base->pgd);
437 nouveau_gpuobj_ref(NULL, &base->pgd);
438 nouveau_gpuobj_ref(NULL, &base->eng);
439 nouveau_gpuobj_ref(NULL, &base->ramfc);
440 nouveau_gpuobj_ref(NULL, &base->cache);
441 nouveau_fifo_context_destroy(&base->base);
442 }
443
444 static struct nouveau_oclass
445 nv50_fifo_cclass = {
446 .handle = NV_ENGCTX(FIFO, 0x50),
447 .ofuncs = &(struct nouveau_ofuncs) {
448 .ctor = nv50_fifo_context_ctor,
449 .dtor = nv50_fifo_context_dtor,
450 .init = _nouveau_fifo_context_init,
451 .fini = _nouveau_fifo_context_fini,
452 .rd32 = _nouveau_fifo_context_rd32,
453 .wr32 = _nouveau_fifo_context_wr32,
454 },
455 };
456
457 /*******************************************************************************
458 * PFIFO engine
459 ******************************************************************************/
460
461 static int
nv50_fifo_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)462 nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
463 struct nouveau_oclass *oclass, void *data, u32 size,
464 struct nouveau_object **pobject)
465 {
466 struct nv50_fifo_priv *priv;
467 int ret;
468
469 ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
470 *pobject = nv_object(priv);
471 if (ret)
472 return ret;
473
474 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
475 &priv->playlist[0]);
476 if (ret)
477 return ret;
478
479 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
480 &priv->playlist[1]);
481 if (ret)
482 return ret;
483
484 nv_subdev(priv)->unit = 0x00000100;
485 nv_subdev(priv)->intr = nv04_fifo_intr;
486 nv_engine(priv)->cclass = &nv50_fifo_cclass;
487 nv_engine(priv)->sclass = nv50_fifo_sclass;
488 priv->base.pause = nv04_fifo_pause;
489 priv->base.start = nv04_fifo_start;
490 return 0;
491 }
492
493 void
nv50_fifo_dtor(struct nouveau_object * object)494 nv50_fifo_dtor(struct nouveau_object *object)
495 {
496 struct nv50_fifo_priv *priv = (void *)object;
497
498 nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
499 nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
500
501 nouveau_fifo_destroy(&priv->base);
502 }
503
504 int
nv50_fifo_init(struct nouveau_object * object)505 nv50_fifo_init(struct nouveau_object *object)
506 {
507 struct nv50_fifo_priv *priv = (void *)object;
508 int ret, i;
509
510 ret = nouveau_fifo_init(&priv->base);
511 if (ret)
512 return ret;
513
514 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
515 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
516 nv_wr32(priv, 0x00250c, 0x6f3cfc34);
517 nv_wr32(priv, 0x002044, 0x01003fff);
518
519 nv_wr32(priv, 0x002100, 0xffffffff);
520 nv_wr32(priv, 0x002140, 0xbfffffff);
521
522 for (i = 0; i < 128; i++)
523 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
524 nv50_fifo_playlist_update_locked(priv);
525
526 nv_wr32(priv, 0x003200, 0x00000001);
527 nv_wr32(priv, 0x003250, 0x00000001);
528 nv_wr32(priv, 0x002500, 0x00000001);
529 return 0;
530 }
531
532 struct nouveau_oclass *
533 nv50_fifo_oclass = &(struct nouveau_oclass) {
534 .handle = NV_ENGINE(FIFO, 0x50),
535 .ofuncs = &(struct nouveau_ofuncs) {
536 .ctor = nv50_fifo_ctor,
537 .dtor = nv50_fifo_dtor,
538 .init = nv50_fifo_init,
539 .fini = _nouveau_fifo_fini,
540 },
541 };
542