1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/bios.h>
26 #include <subdev/bios/bit.h>
27 #include <subdev/bios/pll.h>
28 #include <subdev/bios/perf.h>
29 #include <subdev/bios/timing.h>
30 #include <subdev/clock/pll.h>
31 #include <subdev/fb.h>
32
33 #include <core/option.h>
34 #include <core/mm.h>
35
36 #include "ramseq.h"
37
38 #include "nv50.h"
39
40 struct nv50_ramseq {
41 struct hwsq base;
42 struct hwsq_reg r_0x002504;
43 struct hwsq_reg r_0x004008;
44 struct hwsq_reg r_0x00400c;
45 struct hwsq_reg r_0x00c040;
46 struct hwsq_reg r_0x100210;
47 struct hwsq_reg r_0x1002d0;
48 struct hwsq_reg r_0x1002d4;
49 struct hwsq_reg r_0x1002dc;
50 struct hwsq_reg r_0x100da0[8];
51 struct hwsq_reg r_0x100e20;
52 struct hwsq_reg r_0x100e24;
53 struct hwsq_reg r_0x611200;
54 struct hwsq_reg r_timing[9];
55 struct hwsq_reg r_mr[4];
56 };
57
58 struct nv50_ram {
59 struct nouveau_ram base;
60 struct nv50_ramseq hwsq;
61 };
62
63 #define QFX5800NVA0 1
64
65 static int
nv50_ram_calc(struct nouveau_fb * pfb,u32 freq)66 nv50_ram_calc(struct nouveau_fb *pfb, u32 freq)
67 {
68 struct nouveau_bios *bios = nouveau_bios(pfb);
69 struct nv50_ram *ram = (void *)pfb->ram;
70 struct nv50_ramseq *hwsq = &ram->hwsq;
71 struct nvbios_perfE perfE;
72 struct nvbios_pll mpll;
73 struct {
74 u32 data;
75 u8 size;
76 } ramcfg, timing;
77 u8 ver, hdr, cnt, len, strap;
78 int N1, M1, N2, M2, P;
79 int ret, i;
80
81 /* lookup closest matching performance table entry for frequency */
82 i = 0;
83 do {
84 ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt,
85 &ramcfg.size, &perfE);
86 if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) ||
87 (ramcfg.size < 2)) {
88 nv_error(pfb, "invalid/missing perftab entry\n");
89 return -EINVAL;
90 }
91 } while (perfE.memory < freq);
92
93 /* locate specific data set for the attached memory */
94 strap = nvbios_ramcfg_index(nv_subdev(pfb));
95 if (strap >= cnt) {
96 nv_error(pfb, "invalid ramcfg strap\n");
97 return -EINVAL;
98 }
99
100 ramcfg.data += hdr + (strap * ramcfg.size);
101
102 /* lookup memory timings, if bios says they're present */
103 strap = nv_ro08(bios, ramcfg.data + 0x01);
104 if (strap != 0xff) {
105 timing.data = nvbios_timingEe(bios, strap, &ver, &hdr,
106 &cnt, &len);
107 if (!timing.data || ver != 0x10 || hdr < 0x12) {
108 nv_error(pfb, "invalid/missing timing entry "
109 "%02x %04x %02x %02x\n",
110 strap, timing.data, ver, hdr);
111 return -EINVAL;
112 }
113 } else {
114 timing.data = 0;
115 }
116
117 ret = ram_init(hwsq, nv_subdev(pfb));
118 if (ret)
119 return ret;
120
121 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */
122 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */
123 ram_wr32(hwsq, 0x611200, 0x00003300);
124 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
125 ram_nsec(hwsq, 8000);
126 ram_setf(hwsq, 0x10, 0x00); /* disable fb */
127 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
128
129 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
130 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
131 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
132 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
133 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
134
135 ret = nvbios_pll_parse(bios, 0x004008, &mpll);
136 mpll.vco2.max_freq = 0;
137 if (ret == 0) {
138 ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq,
139 &N1, &M1, &N2, &M2, &P);
140 if (ret == 0)
141 ret = -EINVAL;
142 }
143
144 if (ret < 0)
145 return ret;
146
147 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
148 ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200);
149 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
150 ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) |
151 (P << 22) | (P << 16));
152 #if QFX5800NVA0
153 for (i = 0; i < 8; i++)
154 ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/
155 #endif
156 ram_nsec(hwsq, 96000); /*XXX*/
157 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
158
159 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
160 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
161
162 ram_nsec(hwsq, 12000);
163
164 switch (ram->base.type) {
165 case NV_MEM_TYPE_DDR2:
166 ram_nuke(hwsq, mr[0]); /* force update */
167 ram_mask(hwsq, mr[0], 0x000, 0x000);
168 break;
169 case NV_MEM_TYPE_GDDR3:
170 ram_mask(hwsq, mr[2], 0x000, 0x000);
171 ram_nuke(hwsq, mr[0]); /* force update */
172 ram_mask(hwsq, mr[0], 0x000, 0x000);
173 break;
174 default:
175 break;
176 }
177
178 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/
179 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/
180 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/
181 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/
182 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/
183 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
184 ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/
185 ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/
186 ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/
187
188 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/
189
190 #if QFX5800NVA0
191 ram_nuke(hwsq, 0x100e24);
192 ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000);
193 ram_nuke(hwsq, 0x100e20);
194 ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000);
195 #endif
196
197 ram_mask(hwsq, mr[0], 0x100, 0x100);
198 ram_mask(hwsq, mr[0], 0x100, 0x000);
199
200 ram_setf(hwsq, 0x10, 0x01); /* enable fb */
201 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
202 ram_wr32(hwsq, 0x611200, 0x00003330);
203 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
204 return 0;
205 }
206
207 static int
nv50_ram_prog(struct nouveau_fb * pfb)208 nv50_ram_prog(struct nouveau_fb *pfb)
209 {
210 struct nouveau_device *device = nv_device(pfb);
211 struct nv50_ram *ram = (void *)pfb->ram;
212 struct nv50_ramseq *hwsq = &ram->hwsq;
213
214 ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
215 return 0;
216 }
217
218 static void
nv50_ram_tidy(struct nouveau_fb * pfb)219 nv50_ram_tidy(struct nouveau_fb *pfb)
220 {
221 struct nv50_ram *ram = (void *)pfb->ram;
222 struct nv50_ramseq *hwsq = &ram->hwsq;
223 ram_exec(hwsq, false);
224 }
225
226 void
__nv50_ram_put(struct nouveau_fb * pfb,struct nouveau_mem * mem)227 __nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
228 {
229 struct nouveau_mm_node *this;
230
231 while (!list_empty(&mem->regions)) {
232 this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
233
234 list_del(&this->rl_entry);
235 nouveau_mm_free(&pfb->vram, &this);
236 }
237
238 nouveau_mm_free(&pfb->tags, &mem->tag);
239 }
240
241 void
nv50_ram_put(struct nouveau_fb * pfb,struct nouveau_mem ** pmem)242 nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
243 {
244 struct nouveau_mem *mem = *pmem;
245
246 *pmem = NULL;
247 if (unlikely(mem == NULL))
248 return;
249
250 mutex_lock(&pfb->base.mutex);
251 __nv50_ram_put(pfb, mem);
252 mutex_unlock(&pfb->base.mutex);
253
254 kfree(mem);
255 }
256
257 int
nv50_ram_get(struct nouveau_fb * pfb,u64 size,u32 align,u32 ncmin,u32 memtype,struct nouveau_mem ** pmem)258 nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
259 u32 memtype, struct nouveau_mem **pmem)
260 {
261 struct nouveau_mm *heap = &pfb->vram;
262 struct nouveau_mm *tags = &pfb->tags;
263 struct nouveau_mm_node *r;
264 struct nouveau_mem *mem;
265 int comp = (memtype & 0x300) >> 8;
266 int type = (memtype & 0x07f);
267 int back = (memtype & 0x800);
268 int min, max, ret;
269
270 max = (size >> 12);
271 min = ncmin ? (ncmin >> 12) : max;
272 align >>= 12;
273
274 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
275 if (!mem)
276 return -ENOMEM;
277
278 mutex_lock(&pfb->base.mutex);
279 if (comp) {
280 if (align == 16) {
281 int n = (max >> 4) * comp;
282
283 ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag);
284 if (ret)
285 mem->tag = NULL;
286 }
287
288 if (unlikely(!mem->tag))
289 comp = 0;
290 }
291
292 INIT_LIST_HEAD(&mem->regions);
293 mem->memtype = (comp << 7) | type;
294 mem->size = max;
295
296 type = nv50_fb_memtype[type];
297 do {
298 if (back)
299 ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r);
300 else
301 ret = nouveau_mm_head(heap, 0, type, max, min, align, &r);
302 if (ret) {
303 mutex_unlock(&pfb->base.mutex);
304 pfb->ram->put(pfb, &mem);
305 return ret;
306 }
307
308 list_add_tail(&r->rl_entry, &mem->regions);
309 max -= r->length;
310 } while (max);
311 mutex_unlock(&pfb->base.mutex);
312
313 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
314 mem->offset = (u64)r->offset << 12;
315 *pmem = mem;
316 return 0;
317 }
318
319 static u32
nv50_fb_vram_rblock(struct nouveau_fb * pfb,struct nouveau_ram * ram)320 nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
321 {
322 int colbits, rowbitsa, rowbitsb, banks;
323 u64 rowsize, predicted;
324 u32 r0, r4, rt, rblock_size;
325
326 r0 = nv_rd32(pfb, 0x100200);
327 r4 = nv_rd32(pfb, 0x100204);
328 rt = nv_rd32(pfb, 0x100250);
329 nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt,
330 nv_rd32(pfb, 0x001540));
331
332 colbits = (r4 & 0x0000f000) >> 12;
333 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
334 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
335 banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
336
337 rowsize = ram->parts * banks * (1 << colbits) * 8;
338 predicted = rowsize << rowbitsa;
339 if (r0 & 0x00000004)
340 predicted += rowsize << rowbitsb;
341
342 if (predicted != ram->size) {
343 nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
344 (u32)(ram->size >> 20));
345 }
346
347 rblock_size = rowsize;
348 if (rt & 1)
349 rblock_size *= 3;
350
351 nv_debug(pfb, "rblock %d bytes\n", rblock_size);
352 return rblock_size;
353 }
354
355 int
nv50_ram_create_(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,int length,void ** pobject)356 nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
357 struct nouveau_oclass *oclass, int length, void **pobject)
358 {
359 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
360 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
361 struct nouveau_bios *bios = nouveau_bios(parent);
362 struct nouveau_fb *pfb = nouveau_fb(parent);
363 struct nouveau_ram *ram;
364 int ret;
365
366 ret = nouveau_ram_create_(parent, engine, oclass, length, pobject);
367 ram = *pobject;
368 if (ret)
369 return ret;
370
371 ram->size = nv_rd32(pfb, 0x10020c);
372 ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
373
374 ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16;
375 ram->parts = hweight8(ram->part_mask);
376
377 switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
378 case 0: ram->type = NV_MEM_TYPE_DDR1; break;
379 case 1:
380 if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
381 ram->type = NV_MEM_TYPE_DDR3;
382 else
383 ram->type = NV_MEM_TYPE_DDR2;
384 break;
385 case 2: ram->type = NV_MEM_TYPE_GDDR3; break;
386 case 3: ram->type = NV_MEM_TYPE_GDDR4; break;
387 case 4: ram->type = NV_MEM_TYPE_GDDR5; break;
388 default:
389 break;
390 }
391
392 ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
393 (rsvd_head + rsvd_tail),
394 nv50_fb_vram_rblock(pfb, ram) >> 12);
395 if (ret)
396 return ret;
397
398 ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
399 ram->tags = nv_rd32(pfb, 0x100320);
400 ram->get = nv50_ram_get;
401 ram->put = nv50_ram_put;
402 return 0;
403 }
404
405 static int
nv50_ram_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 datasize,struct nouveau_object ** pobject)406 nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
407 struct nouveau_oclass *oclass, void *data, u32 datasize,
408 struct nouveau_object **pobject)
409 {
410 struct nv50_ram *ram;
411 int ret, i;
412
413 ret = nv50_ram_create(parent, engine, oclass, &ram);
414 *pobject = nv_object(ram);
415 if (ret)
416 return ret;
417
418 switch (ram->base.type) {
419 case NV_MEM_TYPE_DDR2:
420 case NV_MEM_TYPE_GDDR3:
421 ram->base.calc = nv50_ram_calc;
422 ram->base.prog = nv50_ram_prog;
423 ram->base.tidy = nv50_ram_tidy;
424 break;
425 default:
426 nv_warn(ram, "reclocking of this ram type unsupported\n");
427 return 0;
428 }
429
430 ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
431 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
432 ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
433 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
434 ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
435 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
436 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
437 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
438 for (i = 0; i < 8; i++)
439 ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04));
440 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
441 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
442 ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
443
444 for (i = 0; i < 9; i++)
445 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
446
447 if (ram->base.ranks > 1) {
448 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
449 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
450 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
451 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
452 } else {
453 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
454 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
455 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
456 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
457 }
458
459 return 0;
460 }
461
462 struct nouveau_oclass
463 nv50_ram_oclass = {
464 .ofuncs = &(struct nouveau_ofuncs) {
465 .ctor = nv50_ram_ctor,
466 .dtor = _nouveau_ram_dtor,
467 .init = _nouveau_ram_init,
468 .fini = _nouveau_ram_fini,
469 }
470 };
471