1 /*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/at91_pmc.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/wait.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23
24 #include "pmc.h"
25
26 #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
27 #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
28 #define PLL_DIV_MASK 0xff
29 #define PLL_DIV_MAX PLL_DIV_MASK
30 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
31 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
32 (layout)->mul_mask)
33 #define PLL_MUL_MIN 2
34 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
35 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
36 #define PLL_ICPR_SHIFT(id) ((id) * 16)
37 #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
38 #define PLL_MAX_COUNT 0x3f
39 #define PLL_COUNT_SHIFT 8
40 #define PLL_OUT_SHIFT 14
41 #define PLL_MAX_ID 1
42
43 struct clk_pll_characteristics {
44 struct clk_range input;
45 int num_output;
46 struct clk_range *output;
47 u16 *icpll;
48 u8 *out;
49 };
50
51 struct clk_pll_layout {
52 u32 pllr_mask;
53 u16 mul_mask;
54 u8 mul_shift;
55 };
56
57 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
58
59 struct clk_pll {
60 struct clk_hw hw;
61 struct at91_pmc *pmc;
62 unsigned int irq;
63 wait_queue_head_t wait;
64 u8 id;
65 u8 div;
66 u8 range;
67 u16 mul;
68 const struct clk_pll_layout *layout;
69 const struct clk_pll_characteristics *characteristics;
70 };
71
clk_pll_irq_handler(int irq,void * dev_id)72 static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
73 {
74 struct clk_pll *pll = (struct clk_pll *)dev_id;
75
76 wake_up(&pll->wait);
77 disable_irq_nosync(pll->irq);
78
79 return IRQ_HANDLED;
80 }
81
clk_pll_prepare(struct clk_hw * hw)82 static int clk_pll_prepare(struct clk_hw *hw)
83 {
84 struct clk_pll *pll = to_clk_pll(hw);
85 struct at91_pmc *pmc = pll->pmc;
86 const struct clk_pll_layout *layout = pll->layout;
87 const struct clk_pll_characteristics *characteristics =
88 pll->characteristics;
89 u8 id = pll->id;
90 u32 mask = PLL_STATUS_MASK(id);
91 int offset = PLL_REG(id);
92 u8 out = 0;
93 u32 pllr, icpr;
94 u8 div;
95 u16 mul;
96
97 pllr = pmc_read(pmc, offset);
98 div = PLL_DIV(pllr);
99 mul = PLL_MUL(pllr, layout);
100
101 if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
102 (div == pll->div && mul == pll->mul))
103 return 0;
104
105 if (characteristics->out)
106 out = characteristics->out[pll->range];
107 if (characteristics->icpll) {
108 icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
109 icpr |= (characteristics->icpll[pll->range] <<
110 PLL_ICPR_SHIFT(id));
111 pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
112 }
113
114 pllr &= ~layout->pllr_mask;
115 pllr |= layout->pllr_mask &
116 (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
117 (out << PLL_OUT_SHIFT) |
118 ((pll->mul & layout->mul_mask) << layout->mul_shift));
119 pmc_write(pmc, offset, pllr);
120
121 while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
122 enable_irq(pll->irq);
123 wait_event(pll->wait,
124 pmc_read(pmc, AT91_PMC_SR) & mask);
125 }
126
127 return 0;
128 }
129
clk_pll_is_prepared(struct clk_hw * hw)130 static int clk_pll_is_prepared(struct clk_hw *hw)
131 {
132 struct clk_pll *pll = to_clk_pll(hw);
133 struct at91_pmc *pmc = pll->pmc;
134
135 return !!(pmc_read(pmc, AT91_PMC_SR) &
136 PLL_STATUS_MASK(pll->id));
137 }
138
clk_pll_unprepare(struct clk_hw * hw)139 static void clk_pll_unprepare(struct clk_hw *hw)
140 {
141 struct clk_pll *pll = to_clk_pll(hw);
142 struct at91_pmc *pmc = pll->pmc;
143 const struct clk_pll_layout *layout = pll->layout;
144 int offset = PLL_REG(pll->id);
145 u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
146
147 pmc_write(pmc, offset, tmp);
148 }
149
clk_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)150 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
151 unsigned long parent_rate)
152 {
153 struct clk_pll *pll = to_clk_pll(hw);
154
155 if (!pll->div || !pll->mul)
156 return 0;
157
158 return (parent_rate / pll->div) * (pll->mul + 1);
159 }
160
clk_pll_get_best_div_mul(struct clk_pll * pll,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul,u32 * index)161 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
162 unsigned long parent_rate,
163 u32 *div, u32 *mul,
164 u32 *index) {
165 const struct clk_pll_layout *layout = pll->layout;
166 const struct clk_pll_characteristics *characteristics =
167 pll->characteristics;
168 unsigned long bestremainder = ULONG_MAX;
169 unsigned long maxdiv, mindiv, tmpdiv;
170 long bestrate = -ERANGE;
171 unsigned long bestdiv;
172 unsigned long bestmul;
173 int i = 0;
174
175 /* Check if parent_rate is a valid input rate */
176 if (parent_rate < characteristics->input.min)
177 return -ERANGE;
178
179 /*
180 * Calculate minimum divider based on the minimum multiplier, the
181 * parent_rate and the requested rate.
182 * Should always be 2 according to the input and output characteristics
183 * of the PLL blocks.
184 */
185 mindiv = (parent_rate * PLL_MUL_MIN) / rate;
186 if (!mindiv)
187 mindiv = 1;
188
189 if (parent_rate > characteristics->input.max) {
190 tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
191 if (tmpdiv > PLL_DIV_MAX)
192 return -ERANGE;
193
194 if (tmpdiv > mindiv)
195 mindiv = tmpdiv;
196 }
197
198 /*
199 * Calculate the maximum divider which is limited by PLL register
200 * layout (limited by the MUL or DIV field size).
201 */
202 maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX(layout), rate);
203 if (maxdiv > PLL_DIV_MAX)
204 maxdiv = PLL_DIV_MAX;
205
206 /*
207 * Iterate over the acceptable divider values to find the best
208 * divider/multiplier pair (the one that generates the closest
209 * rate to the requested one).
210 */
211 for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
212 unsigned long remainder;
213 unsigned long tmprate;
214 unsigned long tmpmul;
215
216 /*
217 * Calculate the multiplier associated with the current
218 * divider that provide the closest rate to the requested one.
219 */
220 tmpmul = DIV_ROUND_CLOSEST(rate, parent_rate / tmpdiv);
221 tmprate = (parent_rate / tmpdiv) * tmpmul;
222 if (tmprate > rate)
223 remainder = tmprate - rate;
224 else
225 remainder = rate - tmprate;
226
227 /*
228 * Compare the remainder with the best remainder found until
229 * now and elect a new best multiplier/divider pair if the
230 * current remainder is smaller than the best one.
231 */
232 if (remainder < bestremainder) {
233 bestremainder = remainder;
234 bestdiv = tmpdiv;
235 bestmul = tmpmul;
236 bestrate = tmprate;
237 }
238
239 /*
240 * We've found a perfect match!
241 * Stop searching now and use this multiplier/divider pair.
242 */
243 if (!remainder)
244 break;
245 }
246
247 /* We haven't found any multiplier/divider pair => return -ERANGE */
248 if (bestrate < 0)
249 return bestrate;
250
251 /* Check if bestrate is a valid output rate */
252 for (i = 0; i < characteristics->num_output; i++) {
253 if (bestrate >= characteristics->output[i].min &&
254 bestrate <= characteristics->output[i].max)
255 break;
256 }
257
258 if (i >= characteristics->num_output)
259 return -ERANGE;
260
261 if (div)
262 *div = bestdiv;
263 if (mul)
264 *mul = bestmul - 1;
265 if (index)
266 *index = i;
267
268 return bestrate;
269 }
270
clk_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)271 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
272 unsigned long *parent_rate)
273 {
274 struct clk_pll *pll = to_clk_pll(hw);
275
276 return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
277 NULL, NULL, NULL);
278 }
279
clk_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)280 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
281 unsigned long parent_rate)
282 {
283 struct clk_pll *pll = to_clk_pll(hw);
284 long ret;
285 u32 div;
286 u32 mul;
287 u32 index;
288
289 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
290 &div, &mul, &index);
291 if (ret < 0)
292 return ret;
293
294 pll->range = index;
295 pll->div = div;
296 pll->mul = mul;
297
298 return 0;
299 }
300
301 static const struct clk_ops pll_ops = {
302 .prepare = clk_pll_prepare,
303 .unprepare = clk_pll_unprepare,
304 .is_prepared = clk_pll_is_prepared,
305 .recalc_rate = clk_pll_recalc_rate,
306 .round_rate = clk_pll_round_rate,
307 .set_rate = clk_pll_set_rate,
308 };
309
310 static struct clk * __init
at91_clk_register_pll(struct at91_pmc * pmc,unsigned int irq,const char * name,const char * parent_name,u8 id,const struct clk_pll_layout * layout,const struct clk_pll_characteristics * characteristics)311 at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
312 const char *parent_name, u8 id,
313 const struct clk_pll_layout *layout,
314 const struct clk_pll_characteristics *characteristics)
315 {
316 struct clk_pll *pll;
317 struct clk *clk = NULL;
318 struct clk_init_data init;
319 int ret;
320 int offset = PLL_REG(id);
321 u32 tmp;
322
323 if (id > PLL_MAX_ID)
324 return ERR_PTR(-EINVAL);
325
326 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
327 if (!pll)
328 return ERR_PTR(-ENOMEM);
329
330 init.name = name;
331 init.ops = &pll_ops;
332 init.parent_names = &parent_name;
333 init.num_parents = 1;
334 init.flags = CLK_SET_RATE_GATE;
335
336 pll->id = id;
337 pll->hw.init = &init;
338 pll->layout = layout;
339 pll->characteristics = characteristics;
340 pll->pmc = pmc;
341 pll->irq = irq;
342 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
343 pll->div = PLL_DIV(tmp);
344 pll->mul = PLL_MUL(tmp, layout);
345 init_waitqueue_head(&pll->wait);
346 irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
347 ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
348 id ? "clk-pllb" : "clk-plla", pll);
349 if (ret)
350 return ERR_PTR(ret);
351
352 clk = clk_register(NULL, &pll->hw);
353 if (IS_ERR(clk))
354 kfree(pll);
355
356 return clk;
357 }
358
359
360 static const struct clk_pll_layout at91rm9200_pll_layout = {
361 .pllr_mask = 0x7FFFFFF,
362 .mul_shift = 16,
363 .mul_mask = 0x7FF,
364 };
365
366 static const struct clk_pll_layout at91sam9g45_pll_layout = {
367 .pllr_mask = 0xFFFFFF,
368 .mul_shift = 16,
369 .mul_mask = 0xFF,
370 };
371
372 static const struct clk_pll_layout at91sam9g20_pllb_layout = {
373 .pllr_mask = 0x3FFFFF,
374 .mul_shift = 16,
375 .mul_mask = 0x3F,
376 };
377
378 static const struct clk_pll_layout sama5d3_pll_layout = {
379 .pllr_mask = 0x1FFFFFF,
380 .mul_shift = 18,
381 .mul_mask = 0x7F,
382 };
383
384
385 static struct clk_pll_characteristics * __init
of_at91_clk_pll_get_characteristics(struct device_node * np)386 of_at91_clk_pll_get_characteristics(struct device_node *np)
387 {
388 int i;
389 int offset;
390 u32 tmp;
391 int num_output;
392 u32 num_cells;
393 struct clk_range input;
394 struct clk_range *output;
395 u8 *out = NULL;
396 u16 *icpll = NULL;
397 struct clk_pll_characteristics *characteristics;
398
399 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
400 return NULL;
401
402 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
403 &num_cells))
404 return NULL;
405
406 if (num_cells < 2 || num_cells > 4)
407 return NULL;
408
409 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
410 return NULL;
411 num_output = tmp / (sizeof(u32) * num_cells);
412
413 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
414 if (!characteristics)
415 return NULL;
416
417 output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
418 if (!output)
419 goto out_free_characteristics;
420
421 if (num_cells > 2) {
422 out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
423 if (!out)
424 goto out_free_output;
425 }
426
427 if (num_cells > 3) {
428 icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
429 if (!icpll)
430 goto out_free_output;
431 }
432
433 for (i = 0; i < num_output; i++) {
434 offset = i * num_cells;
435 if (of_property_read_u32_index(np,
436 "atmel,pll-clk-output-ranges",
437 offset, &tmp))
438 goto out_free_output;
439 output[i].min = tmp;
440 if (of_property_read_u32_index(np,
441 "atmel,pll-clk-output-ranges",
442 offset + 1, &tmp))
443 goto out_free_output;
444 output[i].max = tmp;
445
446 if (num_cells == 2)
447 continue;
448
449 if (of_property_read_u32_index(np,
450 "atmel,pll-clk-output-ranges",
451 offset + 2, &tmp))
452 goto out_free_output;
453 out[i] = tmp;
454
455 if (num_cells == 3)
456 continue;
457
458 if (of_property_read_u32_index(np,
459 "atmel,pll-clk-output-ranges",
460 offset + 3, &tmp))
461 goto out_free_output;
462 icpll[i] = tmp;
463 }
464
465 characteristics->input = input;
466 characteristics->num_output = num_output;
467 characteristics->output = output;
468 characteristics->out = out;
469 characteristics->icpll = icpll;
470 return characteristics;
471
472 out_free_output:
473 kfree(icpll);
474 kfree(out);
475 kfree(output);
476 out_free_characteristics:
477 kfree(characteristics);
478 return NULL;
479 }
480
481 static void __init
of_at91_clk_pll_setup(struct device_node * np,struct at91_pmc * pmc,const struct clk_pll_layout * layout)482 of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
483 const struct clk_pll_layout *layout)
484 {
485 u32 id;
486 unsigned int irq;
487 struct clk *clk;
488 const char *parent_name;
489 const char *name = np->name;
490 struct clk_pll_characteristics *characteristics;
491
492 if (of_property_read_u32(np, "reg", &id))
493 return;
494
495 parent_name = of_clk_get_parent_name(np, 0);
496
497 of_property_read_string(np, "clock-output-names", &name);
498
499 characteristics = of_at91_clk_pll_get_characteristics(np);
500 if (!characteristics)
501 return;
502
503 irq = irq_of_parse_and_map(np, 0);
504 if (!irq)
505 return;
506
507 clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
508 characteristics);
509 if (IS_ERR(clk))
510 goto out_free_characteristics;
511
512 of_clk_add_provider(np, of_clk_src_simple_get, clk);
513 return;
514
515 out_free_characteristics:
516 kfree(characteristics);
517 }
518
of_at91rm9200_clk_pll_setup(struct device_node * np,struct at91_pmc * pmc)519 void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
520 struct at91_pmc *pmc)
521 {
522 of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
523 }
524
of_at91sam9g45_clk_pll_setup(struct device_node * np,struct at91_pmc * pmc)525 void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
526 struct at91_pmc *pmc)
527 {
528 of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
529 }
530
of_at91sam9g20_clk_pllb_setup(struct device_node * np,struct at91_pmc * pmc)531 void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
532 struct at91_pmc *pmc)
533 {
534 of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
535 }
536
of_sama5d3_clk_pll_setup(struct device_node * np,struct at91_pmc * pmc)537 void __init of_sama5d3_clk_pll_setup(struct device_node *np,
538 struct at91_pmc *pmc)
539 {
540 of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
541 }
542