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1 /*
2  *  linux/arch/arm/mach-omap2/clock.c
3  *
4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
5  *  Copyright (C) 2004-2010 Nokia Corporation
6  *
7  *  Contacts:
8  *  Richard Woodruff <r-woodruff2@ti.com>
9  *  Paul Walmsley
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15 #undef DEBUG
16 
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/clk-provider.h>
24 #include <linux/io.h>
25 #include <linux/bitops.h>
26 #include <linux/clk-private.h>
27 #include <asm/cpu.h>
28 
29 #include <trace/events/power.h>
30 
31 #include "soc.h"
32 #include "clockdomain.h"
33 #include "clock.h"
34 #include "cm.h"
35 #include "cm2xxx.h"
36 #include "cm3xxx.h"
37 #include "cm-regbits-24xx.h"
38 #include "cm-regbits-34xx.h"
39 #include "common.h"
40 
41 /*
42  * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
43  * for a module to indicate that it is no longer in idle
44  */
45 #define MAX_MODULE_ENABLE_WAIT		100000
46 
47 u16 cpu_mask;
48 
49 /*
50  * Clock features setup. Used instead of CPU type checks.
51  */
52 struct ti_clk_features ti_clk_features;
53 
54 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
55 #define OMAP3430_DPLL_FINT_BAND1_MIN	750000
56 #define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
57 #define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
58 #define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
59 
60 /*
61  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
62  * From device data manual section 4.3 "DPLL and DLL Specifications".
63  */
64 #define OMAP3PLUS_DPLL_FINT_MIN		32000
65 #define OMAP3PLUS_DPLL_FINT_MAX		52000000
66 
67 /*
68  * clkdm_control: if true, then when a clock is enabled in the
69  * hardware, its clockdomain will first be enabled; and when a clock
70  * is disabled in the hardware, its clockdomain will be disabled
71  * afterwards.
72  */
73 static bool clkdm_control = true;
74 
75 static LIST_HEAD(clk_hw_omap_clocks);
76 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
77 
omap2_clk_writel(u32 val,struct clk_hw_omap * clk,void __iomem * reg)78 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
79 {
80 	if (clk->flags & MEMMAP_ADDRESSING) {
81 		struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
82 		writel_relaxed(val, clk_memmaps[r->index] + r->offset);
83 	} else {
84 		writel_relaxed(val, reg);
85 	}
86 }
87 
omap2_clk_readl(struct clk_hw_omap * clk,void __iomem * reg)88 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
89 {
90 	u32 val;
91 
92 	if (clk->flags & MEMMAP_ADDRESSING) {
93 		struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
94 		val = readl_relaxed(clk_memmaps[r->index] + r->offset);
95 	} else {
96 		val = readl_relaxed(reg);
97 	}
98 
99 	return val;
100 }
101 
102 /*
103  * OMAP2+ specific clock functions
104  */
105 
106 /* Private functions */
107 
108 
109 /**
110  * _wait_idlest_generic - wait for a module to leave the idle state
111  * @clk: module clock to wait for (needed for register offsets)
112  * @reg: virtual address of module IDLEST register
113  * @mask: value to mask against to determine if the module is active
114  * @idlest: idle state indicator (0 or 1) for the clock
115  * @name: name of the clock (for printk)
116  *
117  * Wait for a module to leave idle, where its idle-status register is
118  * not inside the CM module.  Returns 1 if the module left idle
119  * promptly, or 0 if the module did not leave idle before the timeout
120  * elapsed.  XXX Deprecated - should be moved into drivers for the
121  * individual IP block that the IDLEST register exists in.
122  */
_wait_idlest_generic(struct clk_hw_omap * clk,void __iomem * reg,u32 mask,u8 idlest,const char * name)123 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
124 				u32 mask, u8 idlest, const char *name)
125 {
126 	int i = 0, ena = 0;
127 
128 	ena = (idlest) ? 0 : mask;
129 
130 	omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
131 			  MAX_MODULE_ENABLE_WAIT, i);
132 
133 	if (i < MAX_MODULE_ENABLE_WAIT)
134 		pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
135 			 name, i);
136 	else
137 		pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
138 		       name, MAX_MODULE_ENABLE_WAIT);
139 
140 	return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
141 };
142 
143 /**
144  * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
145  * @clk: struct clk * belonging to the module
146  *
147  * If the necessary clocks for the OMAP hardware IP block that
148  * corresponds to clock @clk are enabled, then wait for the module to
149  * indicate readiness (i.e., to leave IDLE).  This code does not
150  * belong in the clock code and will be moved in the medium term to
151  * module-dependent code.  No return value.
152  */
_omap2_module_wait_ready(struct clk_hw_omap * clk)153 static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
154 {
155 	void __iomem *companion_reg, *idlest_reg;
156 	u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
157 	s16 prcm_mod;
158 	int r;
159 
160 	/* Not all modules have multiple clocks that their IDLEST depends on */
161 	if (clk->ops->find_companion) {
162 		clk->ops->find_companion(clk, &companion_reg, &other_bit);
163 		if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
164 			return;
165 	}
166 
167 	clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
168 	r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
169 	if (r) {
170 		/* IDLEST register not in the CM module */
171 		_wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
172 				     idlest_val, __clk_get_name(clk->hw.clk));
173 	} else {
174 		cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
175 	};
176 }
177 
178 /* Public functions */
179 
180 /**
181  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
182  * @clk: OMAP clock struct ptr to use
183  *
184  * Convert a clockdomain name stored in a struct clk 'clk' into a
185  * clockdomain pointer, and save it into the struct clk.  Intended to be
186  * called during clk_register().  No return value.
187  */
omap2_init_clk_clkdm(struct clk_hw * hw)188 void omap2_init_clk_clkdm(struct clk_hw *hw)
189 {
190 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
191 	struct clockdomain *clkdm;
192 	const char *clk_name;
193 
194 	if (!clk->clkdm_name)
195 		return;
196 
197 	clk_name = __clk_get_name(hw->clk);
198 
199 	clkdm = clkdm_lookup(clk->clkdm_name);
200 	if (clkdm) {
201 		pr_debug("clock: associated clk %s to clkdm %s\n",
202 			 clk_name, clk->clkdm_name);
203 		clk->clkdm = clkdm;
204 	} else {
205 		pr_debug("clock: could not associate clk %s to clkdm %s\n",
206 			 clk_name, clk->clkdm_name);
207 	}
208 }
209 
210 /**
211  * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
212  *
213  * Prevent the OMAP clock code from calling into the clockdomain code
214  * when a hardware clock in that clockdomain is enabled or disabled.
215  * Intended to be called at init time from omap*_clk_init().  No
216  * return value.
217  */
omap2_clk_disable_clkdm_control(void)218 void __init omap2_clk_disable_clkdm_control(void)
219 {
220 	clkdm_control = false;
221 }
222 
223 /**
224  * omap2_clk_dflt_find_companion - find companion clock to @clk
225  * @clk: struct clk * to find the companion clock of
226  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
227  * @other_bit: u8 ** to return the companion clock bit shift in
228  *
229  * Note: We don't need special code here for INVERT_ENABLE for the
230  * time being since INVERT_ENABLE only applies to clocks enabled by
231  * CM_CLKEN_PLL
232  *
233  * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
234  * just a matter of XORing the bits.
235  *
236  * Some clocks don't have companion clocks.  For example, modules with
237  * only an interface clock (such as MAILBOXES) don't have a companion
238  * clock.  Right now, this code relies on the hardware exporting a bit
239  * in the correct companion register that indicates that the
240  * nonexistent 'companion clock' is active.  Future patches will
241  * associate this type of code with per-module data structures to
242  * avoid this issue, and remove the casts.  No return value.
243  */
omap2_clk_dflt_find_companion(struct clk_hw_omap * clk,void __iomem ** other_reg,u8 * other_bit)244 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
245 			void __iomem **other_reg, u8 *other_bit)
246 {
247 	u32 r;
248 
249 	/*
250 	 * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
251 	 * it's just a matter of XORing the bits.
252 	 */
253 	r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
254 
255 	*other_reg = (__force void __iomem *)r;
256 	*other_bit = clk->enable_bit;
257 }
258 
259 /**
260  * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
261  * @clk: struct clk * to find IDLEST info for
262  * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
263  * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
264  * @idlest_val: u8 * to return the idle status indicator
265  *
266  * Return the CM_IDLEST register address and bit shift corresponding
267  * to the module that "owns" this clock.  This default code assumes
268  * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
269  * the IDLEST register address ID corresponds to the CM_*CLKEN
270  * register address ID (e.g., that CM_FCLKEN2 corresponds to
271  * CM_IDLEST2).  This is not true for all modules.  No return value.
272  */
omap2_clk_dflt_find_idlest(struct clk_hw_omap * clk,void __iomem ** idlest_reg,u8 * idlest_bit,u8 * idlest_val)273 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
274 		void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
275 {
276 	u32 r;
277 
278 	r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
279 	*idlest_reg = (__force void __iomem *)r;
280 	*idlest_bit = clk->enable_bit;
281 
282 	/*
283 	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
284 	 * 34xx reverses this, just to keep us on our toes
285 	 * AM35xx uses both, depending on the module.
286 	 */
287 	*idlest_val = ti_clk_features.cm_idlest_val;
288 }
289 
290 /**
291  * omap2_dflt_clk_enable - enable a clock in the hardware
292  * @hw: struct clk_hw * of the clock to enable
293  *
294  * Enable the clock @hw in the hardware.  We first call into the OMAP
295  * clockdomain code to "enable" the corresponding clockdomain if this
296  * is the first enabled user of the clockdomain.  Then program the
297  * hardware to enable the clock.  Then wait for the IP block that uses
298  * this clock to leave idle (if applicable).  Returns the error value
299  * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
300  * if @hw has a null clock enable_reg, or zero upon success.
301  */
omap2_dflt_clk_enable(struct clk_hw * hw)302 int omap2_dflt_clk_enable(struct clk_hw *hw)
303 {
304 	struct clk_hw_omap *clk;
305 	u32 v;
306 	int ret = 0;
307 
308 	clk = to_clk_hw_omap(hw);
309 
310 	if (clkdm_control && clk->clkdm) {
311 		ret = clkdm_clk_enable(clk->clkdm, hw->clk);
312 		if (ret) {
313 			WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
314 			     __func__, __clk_get_name(hw->clk),
315 			     clk->clkdm->name, ret);
316 			return ret;
317 		}
318 	}
319 
320 	if (unlikely(clk->enable_reg == NULL)) {
321 		pr_err("%s: %s missing enable_reg\n", __func__,
322 		       __clk_get_name(hw->clk));
323 		ret = -EINVAL;
324 		goto err;
325 	}
326 
327 	/* FIXME should not have INVERT_ENABLE bit here */
328 	v = omap2_clk_readl(clk, clk->enable_reg);
329 	if (clk->flags & INVERT_ENABLE)
330 		v &= ~(1 << clk->enable_bit);
331 	else
332 		v |= (1 << clk->enable_bit);
333 	omap2_clk_writel(v, clk, clk->enable_reg);
334 	v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
335 
336 	if (clk->ops && clk->ops->find_idlest)
337 		_omap2_module_wait_ready(clk);
338 
339 	return 0;
340 
341 err:
342 	if (clkdm_control && clk->clkdm)
343 		clkdm_clk_disable(clk->clkdm, hw->clk);
344 	return ret;
345 }
346 
347 /**
348  * omap2_dflt_clk_disable - disable a clock in the hardware
349  * @hw: struct clk_hw * of the clock to disable
350  *
351  * Disable the clock @hw in the hardware, and call into the OMAP
352  * clockdomain code to "disable" the corresponding clockdomain if all
353  * clocks/hwmods in that clockdomain are now disabled.  No return
354  * value.
355  */
omap2_dflt_clk_disable(struct clk_hw * hw)356 void omap2_dflt_clk_disable(struct clk_hw *hw)
357 {
358 	struct clk_hw_omap *clk;
359 	u32 v;
360 
361 	clk = to_clk_hw_omap(hw);
362 	if (!clk->enable_reg) {
363 		/*
364 		 * 'independent' here refers to a clock which is not
365 		 * controlled by its parent.
366 		 */
367 		pr_err("%s: independent clock %s has no enable_reg\n",
368 		       __func__, __clk_get_name(hw->clk));
369 		return;
370 	}
371 
372 	v = omap2_clk_readl(clk, clk->enable_reg);
373 	if (clk->flags & INVERT_ENABLE)
374 		v |= (1 << clk->enable_bit);
375 	else
376 		v &= ~(1 << clk->enable_bit);
377 	omap2_clk_writel(v, clk, clk->enable_reg);
378 	/* No OCP barrier needed here since it is a disable operation */
379 
380 	if (clkdm_control && clk->clkdm)
381 		clkdm_clk_disable(clk->clkdm, hw->clk);
382 }
383 
384 /**
385  * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
386  * @hw: struct clk_hw * of the clock being enabled
387  *
388  * Increment the usecount of the clockdomain of the clock pointed to
389  * by @hw; if the usecount is 1, the clockdomain will be "enabled."
390  * Only needed for clocks that don't use omap2_dflt_clk_enable() as
391  * their enable function pointer.  Passes along the return value of
392  * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
393  * clockdomain, or 0 if clock framework-based clockdomain control is
394  * not implemented.
395  */
omap2_clkops_enable_clkdm(struct clk_hw * hw)396 int omap2_clkops_enable_clkdm(struct clk_hw *hw)
397 {
398 	struct clk_hw_omap *clk;
399 	int ret = 0;
400 
401 	clk = to_clk_hw_omap(hw);
402 
403 	if (unlikely(!clk->clkdm)) {
404 		pr_err("%s: %s: no clkdm set ?!\n", __func__,
405 		       __clk_get_name(hw->clk));
406 		return -EINVAL;
407 	}
408 
409 	if (unlikely(clk->enable_reg))
410 		pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
411 		       __clk_get_name(hw->clk));
412 
413 	if (!clkdm_control) {
414 		pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
415 		       __func__, __clk_get_name(hw->clk));
416 		return 0;
417 	}
418 
419 	ret = clkdm_clk_enable(clk->clkdm, hw->clk);
420 	WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
421 	     __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
422 
423 	return ret;
424 }
425 
426 /**
427  * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
428  * @hw: struct clk_hw * of the clock being disabled
429  *
430  * Decrement the usecount of the clockdomain of the clock pointed to
431  * by @hw; if the usecount is 0, the clockdomain will be "disabled."
432  * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
433  * disable function pointer.  No return value.
434  */
omap2_clkops_disable_clkdm(struct clk_hw * hw)435 void omap2_clkops_disable_clkdm(struct clk_hw *hw)
436 {
437 	struct clk_hw_omap *clk;
438 
439 	clk = to_clk_hw_omap(hw);
440 
441 	if (unlikely(!clk->clkdm)) {
442 		pr_err("%s: %s: no clkdm set ?!\n", __func__,
443 		       __clk_get_name(hw->clk));
444 		return;
445 	}
446 
447 	if (unlikely(clk->enable_reg))
448 		pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
449 		       __clk_get_name(hw->clk));
450 
451 	if (!clkdm_control) {
452 		pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
453 		       __func__, __clk_get_name(hw->clk));
454 		return;
455 	}
456 
457 	clkdm_clk_disable(clk->clkdm, hw->clk);
458 }
459 
460 /**
461  * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
462  * @hw: struct clk_hw * to check
463  *
464  * Return 1 if the clock represented by @hw is enabled in the
465  * hardware, or 0 otherwise.  Intended for use in the struct
466  * clk_ops.is_enabled function pointer.
467  */
omap2_dflt_clk_is_enabled(struct clk_hw * hw)468 int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
469 {
470 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
471 	u32 v;
472 
473 	v = omap2_clk_readl(clk, clk->enable_reg);
474 
475 	if (clk->flags & INVERT_ENABLE)
476 		v ^= BIT(clk->enable_bit);
477 
478 	v &= BIT(clk->enable_bit);
479 
480 	return v ? 1 : 0;
481 }
482 
483 static int __initdata mpurate;
484 
485 /*
486  * By default we use the rate set by the bootloader.
487  * You can override this with mpurate= cmdline option.
488  */
omap_clk_setup(char * str)489 static int __init omap_clk_setup(char *str)
490 {
491 	get_option(&str, &mpurate);
492 
493 	if (!mpurate)
494 		return 1;
495 
496 	if (mpurate < 1000)
497 		mpurate *= 1000000;
498 
499 	return 1;
500 }
501 __setup("mpurate=", omap_clk_setup);
502 
503 /**
504  * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
505  * @clk: struct clk * to initialize
506  *
507  * Add an OMAP clock @clk to the internal list of OMAP clocks.  Used
508  * temporarily for autoidle handling, until this support can be
509  * integrated into the common clock framework code in some way.  No
510  * return value.
511  */
omap2_init_clk_hw_omap_clocks(struct clk * clk)512 void omap2_init_clk_hw_omap_clocks(struct clk *clk)
513 {
514 	struct clk_hw_omap *c;
515 
516 	if (__clk_get_flags(clk) & CLK_IS_BASIC)
517 		return;
518 
519 	c = to_clk_hw_omap(__clk_get_hw(clk));
520 	list_add(&c->node, &clk_hw_omap_clocks);
521 }
522 
523 /**
524  * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that
525  * support it
526  *
527  * Enable clock autoidle on all OMAP clocks that have allow_idle
528  * function pointers associated with them.  This function is intended
529  * to be temporary until support for this is added to the common clock
530  * code.  Returns 0.
531  */
omap2_clk_enable_autoidle_all(void)532 int omap2_clk_enable_autoidle_all(void)
533 {
534 	struct clk_hw_omap *c;
535 
536 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
537 		if (c->ops && c->ops->allow_idle)
538 			c->ops->allow_idle(c);
539 
540 	of_ti_clk_allow_autoidle_all();
541 
542 	return 0;
543 }
544 
545 /**
546  * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that
547  * support it
548  *
549  * Disable clock autoidle on all OMAP clocks that have allow_idle
550  * function pointers associated with them.  This function is intended
551  * to be temporary until support for this is added to the common clock
552  * code.  Returns 0.
553  */
omap2_clk_disable_autoidle_all(void)554 int omap2_clk_disable_autoidle_all(void)
555 {
556 	struct clk_hw_omap *c;
557 
558 	list_for_each_entry(c, &clk_hw_omap_clocks, node)
559 		if (c->ops && c->ops->deny_idle)
560 			c->ops->deny_idle(c);
561 
562 	of_ti_clk_deny_autoidle_all();
563 
564 	return 0;
565 }
566 
567 /**
568  * omap2_clk_deny_idle - disable autoidle on an OMAP clock
569  * @clk: struct clk * to disable autoidle for
570  *
571  * Disable autoidle on an OMAP clock.
572  */
omap2_clk_deny_idle(struct clk * clk)573 int omap2_clk_deny_idle(struct clk *clk)
574 {
575 	struct clk_hw_omap *c;
576 
577 	if (__clk_get_flags(clk) & CLK_IS_BASIC)
578 		return -EINVAL;
579 
580 	c = to_clk_hw_omap(__clk_get_hw(clk));
581 	if (c->ops && c->ops->deny_idle)
582 		c->ops->deny_idle(c);
583 	return 0;
584 }
585 
586 /**
587  * omap2_clk_allow_idle - enable autoidle on an OMAP clock
588  * @clk: struct clk * to enable autoidle for
589  *
590  * Enable autoidle on an OMAP clock.
591  */
omap2_clk_allow_idle(struct clk * clk)592 int omap2_clk_allow_idle(struct clk *clk)
593 {
594 	struct clk_hw_omap *c;
595 
596 	if (__clk_get_flags(clk) & CLK_IS_BASIC)
597 		return -EINVAL;
598 
599 	c = to_clk_hw_omap(__clk_get_hw(clk));
600 	if (c->ops && c->ops->allow_idle)
601 		c->ops->allow_idle(c);
602 	return 0;
603 }
604 
605 /**
606  * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
607  * @clk_names: ptr to an array of strings of clock names to enable
608  * @num_clocks: number of clock names in @clk_names
609  *
610  * Prepare and enable a list of clocks, named by @clk_names.  No
611  * return value. XXX Deprecated; only needed until these clocks are
612  * properly claimed and enabled by the drivers or core code that uses
613  * them.  XXX What code disables & calls clk_put on these clocks?
614  */
omap2_clk_enable_init_clocks(const char ** clk_names,u8 num_clocks)615 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
616 {
617 	struct clk *init_clk;
618 	int i;
619 
620 	for (i = 0; i < num_clocks; i++) {
621 		init_clk = clk_get(NULL, clk_names[i]);
622 		clk_prepare_enable(init_clk);
623 	}
624 }
625 
626 const struct clk_hw_omap_ops clkhwops_wait = {
627 	.find_idlest	= omap2_clk_dflt_find_idlest,
628 	.find_companion	= omap2_clk_dflt_find_companion,
629 };
630 
631 /**
632  * omap_clocks_register - register an array of omap_clk
633  * @ocs: pointer to an array of omap_clk to register
634  */
omap_clocks_register(struct omap_clk oclks[],int cnt)635 void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
636 {
637 	struct omap_clk *c;
638 
639 	for (c = oclks; c < oclks + cnt; c++) {
640 		clkdev_add(&c->lk);
641 		if (!__clk_init(NULL, c->lk.clk))
642 			omap2_init_clk_hw_omap_clocks(c->lk.clk);
643 	}
644 }
645 
646 /**
647  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
648  * @mpurate_ck_name: clk name of the clock to change rate
649  *
650  * Change the ARM MPU clock rate to the rate specified on the command
651  * line, if one was specified.  @mpurate_ck_name should be
652  * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
653  * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
654  * handled by the virt_prcm_set clock, but this should be handled by
655  * the OPP layer.  XXX This is intended to be handled by the OPP layer
656  * code in the near future and should be removed from the clock code.
657  * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
658  * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
659  * cannot be found, or 0 upon success.
660  */
omap2_clk_switch_mpurate_at_boot(const char * mpurate_ck_name)661 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
662 {
663 	struct clk *mpurate_ck;
664 	int r;
665 
666 	if (!mpurate)
667 		return -EINVAL;
668 
669 	mpurate_ck = clk_get(NULL, mpurate_ck_name);
670 	if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
671 		return -ENOENT;
672 
673 	r = clk_set_rate(mpurate_ck, mpurate);
674 	if (r < 0) {
675 		WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
676 		     mpurate_ck_name, mpurate, r);
677 		clk_put(mpurate_ck);
678 		return -EINVAL;
679 	}
680 
681 	calibrate_delay();
682 	clk_put(mpurate_ck);
683 
684 	return 0;
685 }
686 
687 /**
688  * omap2_clk_print_new_rates - print summary of current clock tree rates
689  * @hfclkin_ck_name: clk name for the off-chip HF oscillator
690  * @core_ck_name: clk name for the on-chip CORE_CLK
691  * @mpu_ck_name: clk name for the ARM MPU clock
692  *
693  * Prints a short message to the console with the HFCLKIN oscillator
694  * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
695  * Called by the boot-time MPU rate switching code.   XXX This is intended
696  * to be handled by the OPP layer code in the near future and should be
697  * removed from the clock code.  No return value.
698  */
omap2_clk_print_new_rates(const char * hfclkin_ck_name,const char * core_ck_name,const char * mpu_ck_name)699 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
700 				      const char *core_ck_name,
701 				      const char *mpu_ck_name)
702 {
703 	struct clk *hfclkin_ck, *core_ck, *mpu_ck;
704 	unsigned long hfclkin_rate;
705 
706 	mpu_ck = clk_get(NULL, mpu_ck_name);
707 	if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
708 		return;
709 
710 	core_ck = clk_get(NULL, core_ck_name);
711 	if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
712 		return;
713 
714 	hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
715 	if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
716 		return;
717 
718 	hfclkin_rate = clk_get_rate(hfclkin_ck);
719 
720 	pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
721 		(hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
722 		(clk_get_rate(core_ck) / 1000000),
723 		(clk_get_rate(mpu_ck) / 1000000));
724 }
725 
726 /**
727  * ti_clk_init_features - init clock features struct for the SoC
728  *
729  * Initializes the clock features struct based on the SoC type.
730  */
ti_clk_init_features(void)731 void __init ti_clk_init_features(void)
732 {
733 	/* Fint setup for DPLLs */
734 	if (cpu_is_omap3430()) {
735 		ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
736 		ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
737 		ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
738 		ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
739 	} else {
740 		ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
741 		ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
742 	}
743 
744 	/* Bypass value setup for DPLLs */
745 	if (cpu_is_omap24xx()) {
746 		ti_clk_features.dpll_bypass_vals |=
747 			(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
748 			(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
749 	} else if (cpu_is_omap34xx()) {
750 		ti_clk_features.dpll_bypass_vals |=
751 			(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
752 			(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
753 	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
754 		   soc_is_omap54xx() || soc_is_dra7xx()) {
755 		ti_clk_features.dpll_bypass_vals |=
756 			(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
757 			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
758 			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
759 	}
760 
761 	/* Jitter correction only available on OMAP343X */
762 	if (cpu_is_omap343x())
763 		ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
764 
765 	/* Idlest value for interface clocks.
766 	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
767 	 * 34xx reverses this, just to keep us on our toes
768 	 * AM35xx uses both, depending on the module.
769 	 */
770 	if (cpu_is_omap24xx())
771 		ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
772 	else if (cpu_is_omap34xx())
773 		ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
774 }
775