1 /*
2 * OMAP Voltage Controller (VC) interface
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/bug.h>
14 #include <linux/io.h>
15
16 #include <asm/div64.h>
17
18 #include "iomap.h"
19 #include "soc.h"
20 #include "voltage.h"
21 #include "vc.h"
22 #include "prm-regbits-34xx.h"
23 #include "prm-regbits-44xx.h"
24 #include "prm44xx.h"
25 #include "pm.h"
26 #include "scrm44xx.h"
27 #include "control.h"
28
29 /**
30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
31 * @sa: bit for slave address
32 * @rav: bit for voltage configuration register
33 * @rac: bit for command configuration register
34 * @racen: enable bit for RAC
35 * @cmd: bit for command value set selection
36 *
37 * Channel configuration bits, common for OMAP3+
38 * OMAP3 register: PRM_VC_CH_CONF
39 * OMAP4 register: PRM_VC_CFG_CHANNEL
40 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
41 */
42 struct omap_vc_channel_cfg {
43 u8 sa;
44 u8 rav;
45 u8 rac;
46 u8 racen;
47 u8 cmd;
48 };
49
50 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
51 .sa = BIT(0),
52 .rav = BIT(1),
53 .rac = BIT(2),
54 .racen = BIT(3),
55 .cmd = BIT(4),
56 };
57
58 /*
59 * On OMAP3+, all VC channels have the above default bitfield
60 * configuration, except the OMAP4 MPU channel. This appears
61 * to be a freak accident as every other VC channel has the
62 * default configuration, thus creating a mutant channel config.
63 */
64 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
65 .sa = BIT(0),
66 .rav = BIT(2),
67 .rac = BIT(3),
68 .racen = BIT(4),
69 .cmd = BIT(1),
70 };
71
72 static struct omap_vc_channel_cfg *vc_cfg_bits;
73
74 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
75 static u32 sr_i2c_pcb_length = 63;
76 #define CFG_CHANNEL_MASK 0x1f
77
78 /**
79 * omap_vc_config_channel - configure VC channel to PMIC mappings
80 * @voltdm: pointer to voltagdomain defining the desired VC channel
81 *
82 * Configures the VC channel to PMIC mappings for the following
83 * PMIC settings
84 * - i2c slave address (SA)
85 * - voltage configuration address (RAV)
86 * - command configuration address (RAC) and enable bit (RACEN)
87 * - command values for ON, ONLP, RET and OFF (CMD)
88 *
89 * This function currently only allows flexible configuration of the
90 * non-default channel. Starting with OMAP4, there are more than 2
91 * channels, with one defined as the default (on OMAP4, it's MPU.)
92 * Only the non-default channel can be configured.
93 */
omap_vc_config_channel(struct voltagedomain * voltdm)94 static int omap_vc_config_channel(struct voltagedomain *voltdm)
95 {
96 struct omap_vc_channel *vc = voltdm->vc;
97
98 /*
99 * For default channel, the only configurable bit is RACEN.
100 * All others must stay at zero (see function comment above.)
101 */
102 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
103 vc->cfg_channel &= vc_cfg_bits->racen;
104
105 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
106 vc->cfg_channel << vc->cfg_channel_sa_shift,
107 vc->cfg_channel_reg);
108
109 return 0;
110 }
111
112 /* Voltage scale and accessory APIs */
omap_vc_pre_scale(struct voltagedomain * voltdm,unsigned long target_volt,u8 * target_vsel,u8 * current_vsel)113 int omap_vc_pre_scale(struct voltagedomain *voltdm,
114 unsigned long target_volt,
115 u8 *target_vsel, u8 *current_vsel)
116 {
117 struct omap_vc_channel *vc = voltdm->vc;
118 u32 vc_cmdval;
119
120 /* Check if sufficient pmic info is available for this vdd */
121 if (!voltdm->pmic) {
122 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
123 __func__, voltdm->name);
124 return -EINVAL;
125 }
126
127 if (!voltdm->pmic->uv_to_vsel) {
128 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
129 __func__, voltdm->name);
130 return -ENODATA;
131 }
132
133 if (!voltdm->read || !voltdm->write) {
134 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
135 __func__, voltdm->name);
136 return -EINVAL;
137 }
138
139 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
140 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
141
142 /* Setting the ON voltage to the new target voltage */
143 vc_cmdval = voltdm->read(vc->cmdval_reg);
144 vc_cmdval &= ~vc->common->cmd_on_mask;
145 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
146 voltdm->write(vc_cmdval, vc->cmdval_reg);
147
148 voltdm->vc_param->on = target_volt;
149
150 omap_vp_update_errorgain(voltdm, target_volt);
151
152 return 0;
153 }
154
omap_vc_post_scale(struct voltagedomain * voltdm,unsigned long target_volt,u8 target_vsel,u8 current_vsel)155 void omap_vc_post_scale(struct voltagedomain *voltdm,
156 unsigned long target_volt,
157 u8 target_vsel, u8 current_vsel)
158 {
159 u32 smps_steps = 0, smps_delay = 0;
160
161 smps_steps = abs(target_vsel - current_vsel);
162 /* SMPS slew rate / step size. 2us added as buffer. */
163 smps_delay = ((smps_steps * voltdm->pmic->step_size) /
164 voltdm->pmic->slew_rate) + 2;
165 udelay(smps_delay);
166 }
167
168 /* vc_bypass_scale - VC bypass method of voltage scaling */
omap_vc_bypass_scale(struct voltagedomain * voltdm,unsigned long target_volt)169 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
170 unsigned long target_volt)
171 {
172 struct omap_vc_channel *vc = voltdm->vc;
173 u32 loop_cnt = 0, retries_cnt = 0;
174 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
175 u8 target_vsel, current_vsel;
176 int ret;
177
178 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
179 if (ret)
180 return ret;
181
182 vc_valid = vc->common->valid;
183 vc_bypass_val_reg = vc->common->bypass_val_reg;
184 vc_bypass_value = (target_vsel << vc->common->data_shift) |
185 (vc->volt_reg_addr << vc->common->regaddr_shift) |
186 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
187
188 voltdm->write(vc_bypass_value, vc_bypass_val_reg);
189 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
190
191 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
192 /*
193 * Loop till the bypass command is acknowledged from the SMPS.
194 * NOTE: This is legacy code. The loop count and retry count needs
195 * to be revisited.
196 */
197 while (!(vc_bypass_value & vc_valid)) {
198 loop_cnt++;
199
200 if (retries_cnt > 10) {
201 pr_warn("%s: Retry count exceeded\n", __func__);
202 return -ETIMEDOUT;
203 }
204
205 if (loop_cnt > 50) {
206 retries_cnt++;
207 loop_cnt = 0;
208 udelay(10);
209 }
210 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
211 }
212
213 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
214 return 0;
215 }
216
217 /* Convert microsecond value to number of 32kHz clock cycles */
omap_usec_to_32k(u32 usec)218 static inline u32 omap_usec_to_32k(u32 usec)
219 {
220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
221 }
222
223 struct omap3_vc_timings {
224 u32 voltsetup1;
225 u32 voltsetup2;
226 };
227
228 struct omap3_vc {
229 struct voltagedomain *vd;
230 u32 voltctrl;
231 u32 voltsetup1;
232 u32 voltsetup2;
233 struct omap3_vc_timings timings[2];
234 };
235 static struct omap3_vc vc;
236
omap3_vc_set_pmic_signaling(int core_next_state)237 void omap3_vc_set_pmic_signaling(int core_next_state)
238 {
239 struct voltagedomain *vd = vc.vd;
240 struct omap3_vc_timings *c = vc.timings;
241 u32 voltctrl, voltsetup1, voltsetup2;
242
243 voltctrl = vc.voltctrl;
244 voltsetup1 = vc.voltsetup1;
245 voltsetup2 = vc.voltsetup2;
246
247 switch (core_next_state) {
248 case PWRDM_POWER_OFF:
249 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
250 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
251 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
252 if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
253 voltsetup2 = c->voltsetup2;
254 else
255 voltsetup1 = c->voltsetup1;
256 break;
257 case PWRDM_POWER_RET:
258 default:
259 c++;
260 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
261 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
262 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
263 voltsetup1 = c->voltsetup1;
264 break;
265 }
266
267 if (voltctrl != vc.voltctrl) {
268 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
269 vc.voltctrl = voltctrl;
270 }
271 if (voltsetup1 != vc.voltsetup1) {
272 vd->write(c->voltsetup1,
273 OMAP3_PRM_VOLTSETUP1_OFFSET);
274 vc.voltsetup1 = voltsetup1;
275 }
276 if (voltsetup2 != vc.voltsetup2) {
277 vd->write(c->voltsetup2,
278 OMAP3_PRM_VOLTSETUP2_OFFSET);
279 vc.voltsetup2 = voltsetup2;
280 }
281 }
282
283 #define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \
284 OMAP3430_PRM_POLCTRL_CLKREQ_POL)
285 #define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL
286
287 /*
288 * Configure signal polarity for sys_clkreq and sys_off_mode pins
289 * as the default values are wrong and can cause the system to hang
290 * if any twl4030 scripts are loaded.
291 */
omap3_vc_init_pmic_signaling(struct voltagedomain * voltdm)292 static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
293 {
294 u32 val;
295
296 if (vc.vd)
297 return;
298
299 vc.vd = voltdm;
300
301 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
302 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
303 (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
304 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
305 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
306 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
307 val);
308 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
309 }
310
311 /*
312 * By default let's use I2C4 signaling for retention idle
313 * and sys_off_mode pin signaling for off idle. This way we
314 * have sys_clk_req pin go down for retention and both
315 * sys_clk_req and sys_off_mode pins will go down for off
316 * idle. And we can also scale voltages to zero for off-idle.
317 * Note that no actual voltage scaling during off-idle will
318 * happen unless the board specific twl4030 PMIC scripts are
319 * loaded. See also omap_vc_i2c_init for comments regarding
320 * erratum i531.
321 */
322 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
323 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
324 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
325 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
326 val);
327 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
328 }
329 vc.voltctrl = val;
330
331 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
332 }
333
omap3_init_voltsetup1(struct voltagedomain * voltdm,struct omap3_vc_timings * c,u32 idle)334 static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
335 struct omap3_vc_timings *c, u32 idle)
336 {
337 unsigned long val;
338
339 val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
340 val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
341 val <<= __ffs(voltdm->vfsm->voltsetup_mask);
342 c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
343 c->voltsetup1 |= val;
344 }
345
346 /**
347 * omap3_set_i2c_timings - sets i2c sleep timings for a channel
348 * @voltdm: channel to configure
349 * @off_mode: select whether retention or off mode values used
350 *
351 * Calculates and sets up voltage controller to use I2C based
352 * voltage scaling for sleep modes. This can be used for either off mode
353 * or retention. Off mode has additionally an option to use sys_off_mode
354 * pad, which uses a global signal to program the whole power IC to
355 * off-mode.
356 *
357 * Note that pmic is not controlling the voltage scaling during
358 * retention signaled over I2C4, so we can keep voltsetup2 as 0.
359 * And the oscillator is not shut off over I2C4, so no need to
360 * set clksetup.
361 */
omap3_set_i2c_timings(struct voltagedomain * voltdm)362 static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
363 {
364 struct omap3_vc_timings *c = vc.timings;
365
366 /* Configure PRWDM_POWER_OFF over I2C4 */
367 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
368 c++;
369 /* Configure PRWDM_POWER_RET over I2C4 */
370 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
371 }
372
373 /**
374 * omap3_set_off_timings - sets off-mode timings for a channel
375 * @voltdm: channel to configure
376 *
377 * Calculates and sets up off-mode timings for a channel. Off-mode
378 * can use either I2C based voltage scaling, or alternatively
379 * sys_off_mode pad can be used to send a global command to power IC.n,
380 * sys_off_mode has the additional benefit that voltages can be
381 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
382 * scale to 600mV.
383 *
384 * Note that omap is not controlling the voltage scaling during
385 * off idle signaled by sys_off_mode, so we can keep voltsetup1
386 * as 0.
387 */
omap3_set_off_timings(struct voltagedomain * voltdm)388 static void omap3_set_off_timings(struct voltagedomain *voltdm)
389 {
390 struct omap3_vc_timings *c = vc.timings;
391 u32 tstart, tshut, clksetup, voltoffset;
392
393 if (c->voltsetup2)
394 return;
395
396 omap_pm_get_oscillator(&tstart, &tshut);
397 if (tstart == ULONG_MAX) {
398 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
399 clksetup = omap_usec_to_32k(10000);
400 } else {
401 clksetup = omap_usec_to_32k(tstart);
402 }
403
404 /*
405 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
406 * switch from HFCLKIN to internal oscillator. That means timings
407 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
408 * that means we can calculate the value based on the oscillator
409 * start-up time since voltoffset2 = clksetup - voltoffset.
410 */
411 voltoffset = omap_usec_to_32k(488);
412 c->voltsetup2 = clksetup - voltoffset;
413 voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
414 voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
415 }
416
omap3_vc_init_channel(struct voltagedomain * voltdm)417 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
418 {
419 omap3_vc_init_pmic_signaling(voltdm);
420 omap3_set_off_timings(voltdm);
421 omap3_set_i2c_timings(voltdm);
422 }
423
424 /**
425 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
426 * @voltdm: channel to calculate values for
427 * @voltage_diff: voltage difference in microvolts
428 *
429 * Calculates voltage ramp prescaler + counter values for a voltage
430 * difference on omap4. Returns a field value suitable for writing to
431 * VOLTSETUP register for a channel in following format:
432 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
433 */
omap4_calc_volt_ramp(struct voltagedomain * voltdm,u32 voltage_diff)434 static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
435 {
436 u32 prescaler;
437 u32 cycles;
438 u32 time;
439
440 time = voltage_diff / voltdm->pmic->slew_rate;
441
442 cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
443
444 cycles /= 64;
445 prescaler = 0;
446
447 /* shift to next prescaler until no overflow */
448
449 /* scale for div 256 = 64 * 4 */
450 if (cycles > 63) {
451 cycles /= 4;
452 prescaler++;
453 }
454
455 /* scale for div 512 = 256 * 2 */
456 if (cycles > 63) {
457 cycles /= 2;
458 prescaler++;
459 }
460
461 /* scale for div 2048 = 512 * 4 */
462 if (cycles > 63) {
463 cycles /= 4;
464 prescaler++;
465 }
466
467 /* check for overflow => invalid ramp time */
468 if (cycles > 63) {
469 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
470 voltdm->name);
471 return 0;
472 }
473
474 cycles++;
475
476 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
477 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
478 }
479
480 /**
481 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
482 * @usec: microseconds
483 * @shift: number of bits to shift left
484 * @mask: bitfield mask
485 *
486 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
487 * shifted to requested position, and checked agains the mask value.
488 * If larger, forced to the max value of the field (i.e. the mask itself.)
489 * Returns the SCRM bitfield value.
490 */
omap4_usec_to_val_scrm(u32 usec,int shift,u32 mask)491 static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
492 {
493 u32 val;
494
495 val = omap_usec_to_32k(usec) << shift;
496
497 /* Check for overflow, if yes, force to max value */
498 if (val > mask)
499 val = mask;
500
501 return val;
502 }
503
504 /**
505 * omap4_set_timings - set voltage ramp timings for a channel
506 * @voltdm: channel to configure
507 * @off_mode: whether off-mode values are used
508 *
509 * Calculates and sets the voltage ramp up / down values for a channel.
510 */
omap4_set_timings(struct voltagedomain * voltdm,bool off_mode)511 static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
512 {
513 u32 val;
514 u32 ramp;
515 int offset;
516 u32 tstart, tshut;
517
518 if (off_mode) {
519 ramp = omap4_calc_volt_ramp(voltdm,
520 voltdm->vc_param->on - voltdm->vc_param->off);
521 offset = voltdm->vfsm->voltsetup_off_reg;
522 } else {
523 ramp = omap4_calc_volt_ramp(voltdm,
524 voltdm->vc_param->on - voltdm->vc_param->ret);
525 offset = voltdm->vfsm->voltsetup_reg;
526 }
527
528 if (!ramp)
529 return;
530
531 val = voltdm->read(offset);
532
533 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
534
535 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
536
537 voltdm->write(val, offset);
538
539 omap_pm_get_oscillator(&tstart, &tshut);
540
541 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
542 OMAP4_SETUPTIME_MASK);
543 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
544 OMAP4_DOWNTIME_MASK);
545
546 writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
547 }
548
549 /* OMAP4 specific voltage init functions */
omap4_vc_init_channel(struct voltagedomain * voltdm)550 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
551 {
552 omap4_set_timings(voltdm, true);
553 omap4_set_timings(voltdm, false);
554 }
555
556 struct i2c_init_data {
557 u8 loadbits;
558 u8 load;
559 u8 hsscll_38_4;
560 u8 hsscll_26;
561 u8 hsscll_19_2;
562 u8 hsscll_16_8;
563 u8 hsscll_12;
564 };
565
566 static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
567 {
568 .load = 50,
569 .loadbits = 0x3,
570 .hsscll_38_4 = 13,
571 .hsscll_26 = 11,
572 .hsscll_19_2 = 9,
573 .hsscll_16_8 = 9,
574 .hsscll_12 = 8,
575 },
576 {
577 .load = 25,
578 .loadbits = 0x2,
579 .hsscll_38_4 = 13,
580 .hsscll_26 = 11,
581 .hsscll_19_2 = 9,
582 .hsscll_16_8 = 9,
583 .hsscll_12 = 8,
584 },
585 {
586 .load = 12,
587 .loadbits = 0x1,
588 .hsscll_38_4 = 11,
589 .hsscll_26 = 10,
590 .hsscll_19_2 = 9,
591 .hsscll_16_8 = 9,
592 .hsscll_12 = 8,
593 },
594 {
595 .load = 0,
596 .loadbits = 0x0,
597 .hsscll_38_4 = 12,
598 .hsscll_26 = 10,
599 .hsscll_19_2 = 9,
600 .hsscll_16_8 = 8,
601 .hsscll_12 = 8,
602 },
603 };
604
605 /**
606 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
607 * @voltdm: voltagedomain pointer to get data from
608 *
609 * Use PMIC + board supplied settings for calculating the total I2C
610 * channel capacitance and set the timing parameters based on this.
611 * Pre-calculated values are provided in data tables, as it is not
612 * too straightforward to calculate these runtime.
613 */
omap4_vc_i2c_timing_init(struct voltagedomain * voltdm)614 static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
615 {
616 u32 capacitance;
617 u32 val;
618 u16 hsscll;
619 const struct i2c_init_data *i2c_data;
620
621 if (!voltdm->pmic->i2c_high_speed) {
622 pr_warn("%s: only high speed supported!\n", __func__);
623 return;
624 }
625
626 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
627 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
628
629 /* OMAP pad capacitance */
630 capacitance += 4;
631
632 /* PMIC pad capacitance */
633 capacitance += voltdm->pmic->i2c_pad_load;
634
635 /* Search for capacitance match in the table */
636 i2c_data = omap4_i2c_timing_data;
637
638 while (i2c_data->load > capacitance)
639 i2c_data++;
640
641 /* Select proper values based on sysclk frequency */
642 switch (voltdm->sys_clk.rate) {
643 case 38400000:
644 hsscll = i2c_data->hsscll_38_4;
645 break;
646 case 26000000:
647 hsscll = i2c_data->hsscll_26;
648 break;
649 case 19200000:
650 hsscll = i2c_data->hsscll_19_2;
651 break;
652 case 16800000:
653 hsscll = i2c_data->hsscll_16_8;
654 break;
655 case 12000000:
656 hsscll = i2c_data->hsscll_12;
657 break;
658 default:
659 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
660 voltdm->sys_clk.rate);
661 return;
662 }
663
664 /* Loadbits define pull setup for the I2C channels */
665 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
666
667 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
668 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
669 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
670
671 /* HSSCLH can always be zero */
672 val = hsscll << OMAP4430_HSSCLL_SHIFT;
673 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
674
675 /* Write setup times to I2C config register */
676 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
677 }
678
679
680
681 /**
682 * omap_vc_i2c_init - initialize I2C interface to PMIC
683 * @voltdm: voltage domain containing VC data
684 *
685 * Use PMIC supplied settings for I2C high-speed mode and
686 * master code (if set) and program the VC I2C configuration
687 * register.
688 *
689 * The VC I2C configuration is common to all VC channels,
690 * so this function only configures I2C for the first VC
691 * channel registers. All other VC channels will use the
692 * same configuration.
693 */
omap_vc_i2c_init(struct voltagedomain * voltdm)694 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
695 {
696 struct omap_vc_channel *vc = voltdm->vc;
697 static bool initialized;
698 static bool i2c_high_speed;
699 u8 mcode;
700
701 if (initialized) {
702 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
703 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
704 __func__, voltdm->name, i2c_high_speed);
705 return;
706 }
707
708 /*
709 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
710 * erratum i531 "Extra Power Consumed When Repeated Start Operation
711 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
712 * Otherwise I2C4 eventually leads into about 23mW extra power being
713 * consumed even during off idle using VMODE.
714 */
715 i2c_high_speed = voltdm->pmic->i2c_high_speed;
716 if (i2c_high_speed)
717 voltdm->rmw(vc->common->i2c_cfg_clear_mask,
718 vc->common->i2c_cfg_hsen_mask,
719 vc->common->i2c_cfg_reg);
720
721 mcode = voltdm->pmic->i2c_mcode;
722 if (mcode)
723 voltdm->rmw(vc->common->i2c_mcode_mask,
724 mcode << __ffs(vc->common->i2c_mcode_mask),
725 vc->common->i2c_cfg_reg);
726
727 if (cpu_is_omap44xx())
728 omap4_vc_i2c_timing_init(voltdm);
729
730 initialized = true;
731 }
732
733 /**
734 * omap_vc_calc_vsel - calculate vsel value for a channel
735 * @voltdm: channel to calculate value for
736 * @uvolt: microvolt value to convert to vsel
737 *
738 * Converts a microvolt value to vsel value for the used PMIC.
739 * This checks whether the microvolt value is out of bounds, and
740 * adjusts the value accordingly. If unsupported value detected,
741 * warning is thrown.
742 */
omap_vc_calc_vsel(struct voltagedomain * voltdm,u32 uvolt)743 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
744 {
745 if (voltdm->pmic->vddmin > uvolt)
746 uvolt = voltdm->pmic->vddmin;
747 if (voltdm->pmic->vddmax < uvolt) {
748 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
749 __func__, uvolt, voltdm->pmic->vddmax);
750 /* Lets try maximum value anyway */
751 uvolt = voltdm->pmic->vddmax;
752 }
753
754 return voltdm->pmic->uv_to_vsel(uvolt);
755 }
756
757 #ifdef CONFIG_PM
758 /**
759 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
760 * @mm: length of the PCB trace in millimetres
761 *
762 * Sets the PCB trace length for the I2C channel. By default uses 63mm.
763 * This is needed for properly calculating the capacitance value for
764 * the PCB trace, and for setting the SR I2C channel timing parameters.
765 */
omap_pm_setup_sr_i2c_pcb_length(u32 mm)766 void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
767 {
768 sr_i2c_pcb_length = mm;
769 }
770 #endif
771
omap_vc_init_channel(struct voltagedomain * voltdm)772 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
773 {
774 struct omap_vc_channel *vc = voltdm->vc;
775 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
776 u32 val;
777
778 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
779 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
780 return;
781 }
782
783 if (!voltdm->read || !voltdm->write) {
784 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
785 __func__, voltdm->name);
786 return;
787 }
788
789 vc->cfg_channel = 0;
790 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
791 vc_cfg_bits = &vc_mutant_channel_cfg;
792 else
793 vc_cfg_bits = &vc_default_channel_cfg;
794
795 /* get PMIC/board specific settings */
796 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
797 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
798 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
799
800 /* Configure the i2c slave address for this VC */
801 voltdm->rmw(vc->smps_sa_mask,
802 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
803 vc->smps_sa_reg);
804 vc->cfg_channel |= vc_cfg_bits->sa;
805
806 /*
807 * Configure the PMIC register addresses.
808 */
809 voltdm->rmw(vc->smps_volra_mask,
810 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
811 vc->smps_volra_reg);
812 vc->cfg_channel |= vc_cfg_bits->rav;
813
814 if (vc->cmd_reg_addr) {
815 voltdm->rmw(vc->smps_cmdra_mask,
816 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
817 vc->smps_cmdra_reg);
818 vc->cfg_channel |= vc_cfg_bits->rac;
819 }
820
821 if (vc->cmd_reg_addr == vc->volt_reg_addr)
822 vc->cfg_channel |= vc_cfg_bits->racen;
823
824 /* Set up the on, inactive, retention and off voltage */
825 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
826 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
827 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
828 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
829
830 val = ((on_vsel << vc->common->cmd_on_shift) |
831 (onlp_vsel << vc->common->cmd_onlp_shift) |
832 (ret_vsel << vc->common->cmd_ret_shift) |
833 (off_vsel << vc->common->cmd_off_shift));
834 voltdm->write(val, vc->cmdval_reg);
835 vc->cfg_channel |= vc_cfg_bits->cmd;
836
837 /* Channel configuration */
838 omap_vc_config_channel(voltdm);
839
840 omap_vc_i2c_init(voltdm);
841
842 if (cpu_is_omap34xx())
843 omap3_vc_init_channel(voltdm);
844 else if (cpu_is_omap44xx())
845 omap4_vc_init_channel(voltdm);
846 }
847
848